ICS843252AG-45LFT [IDT]
Clock Generator, 156.25MHz, PDSO16, 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16;
| 型号： | ICS843252AG-45LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 156.25MHz, PDSO16, 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
FEMTOCLOCK CRYSTAL-TO-
ICS843252-45
3.3V LVPECL FREQUENCY SYNTHESIZER
General Description
Features
The ICS843252-45 is a 2 LVPECL output
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from IDT. Using a 25MHz, 18pF parallel
• Two differential LVPECL output pairs
S
IC
• Crystal oscillator interface designed for a 25MHz, 18pF parallel
HiPerClockS™
resonant crystal
• A 25MHz crystal generates output frequencies of: 156.25MHz
and 125MHz
resonant crystal, the following frequencies can be generated:
156.25MHz and 125MHz. The ICS843252-45 uses IDT’s 3rd
generation low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS843252-45 is packaged in a small 16-pin
TSSOP package.
• VCO frequency: 625MHz
• RMS Phase Jitter @ 156.25MHz, (1.875MHz – 20MHz) using a
25MHz crystal: 0.54ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Pullup
CLK_EN_A
CLK_EN_A
VEE
1
2
16 CLK_EN_B
125MHz
QA
15
VEE
25MHz
÷5
14
QA
QB
nQA
3
4
XTAL_IN
Phase
Detector
13
VCO
nQA
nQB
OSC
156.25MHz
QB
625MHz
12
11
10
VCCOA
nc
VCCA
VCC
VCCOB
5
6
7
8
XTAL_OUT
CLK_EN_B
÷4
XTAL_IN
XTAL_OUT
nQB
9
VEE
Feedback Divider
÷25
Pullup
ICS843252-45
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
CLK_EN_A
VEE
Type
Description
1
Input
Power
Output
Power
Unused
Power
Power
Pullup
Output enable pin. LVCMOS/LVTTL interface levels. See Table 3A.
Negative supply pins.
2, 9, 15
3, 4
5
QA, nQA
VCCOA
nc
Differential output pair. LVPECL interface levels.
Output supply pin for QA/nQA outputs.
No connect.
6
7
VCCA
Analog supply pin.
8
VCC
Power supply pin.
10
11
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
12
13, 14
16
VCCOB
nQB, QB
Power
Output
Input
Output supply pin for QB/nQB outputs.
Differential output pair. LVPECL interface levels.
Output enable pin. LVCMOS/LVTTL interface levels. See Table 3B.
CLK_EN_B
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
kΩ
Function Tables
Table 3A. CLK_EN_A Function Table
Table 3B. CLK_EN_B Function Table
Input
CLK_EN_A
0
Outputs
Input
CLK_EN_B
0
Outputs
QA
nQA
HIGH
Active
QB
nQB
HIGH
Active
LOW
Active
LOW
Active
1 (default)
1 (default)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
92.4°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCOA = VCCOB = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
Power Supply Voltage
Analog Supply Voltage
V
V
VCCA
VCC – 0.15
3.3
VCC
VCCOA,
VCCOB
Power Supply Voltage
3.135
3.3
3.465
V
ICCA
IEE
Analog Supply Current
Power Supply Current
15
75
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,VCC = VCCOA = VCCOB = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
0.8
Units
VIH
VIL
Input High Voltage
2
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN_A,
CLK_EN_B
IIH
IIL
VCC = VIN = 3.465V
5
µA
µA
CLK_EN_A,
CLK_EN_B
Input Low Current
VCC = 3.465V, VIN = 0V
-150
Table 4C. LVPECL DC Characteristics, VCC = VCCOA = VCCOB = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO – 2.0
0.6
Typical
Maximum
VCCO – 0.9
VCCO – 1.7
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Output termination with 50Ω to VCCOA,B – 2V.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCOA = VCCOB = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
125
Maximum
Units
MHz
MHz
QA/nQA
QB/nQB
fOUT
Output Frequency
156.25
125MHz,
0.56
0.54
ps
ps
Integration Range: 1.875MHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
156.25MHz,
Integration Range: 1.875MHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
300
49
700
51
ps
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal
equilibrium has been reached under these conditions.
Using a 25MHz, 18pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plots.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS843252AG-45 REV. A OCTOBER 23, 2008
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Typical Phase Noise at 125MHz
Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.56ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
an Ethernet filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz
Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.54ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
an Ethernet filter to raw data
Offset Frequency (Hz)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS843252AG-45 REV. A OCTOBER 23, 2008
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FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Parameter Measurement Information
2V
Phase Noise Plot
2V
SCOPE
V
Qx
CC,
V
V
Phase Noise Mask
CCOA,
CCOB
V
CCA
LVPECL
nQx
Offset Frequency
f1
f2
VEE
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.3V 0.165V
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
nQA, nQB
QA, QB
nQA, nQB
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
tPW
20ꢀ
tPERIOD
QA, QB
tPW
odc =
x 100ꢀ
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Application Information
Recommendations for Unused Input Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS843252-45
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, VCCOA, and
VCCOB should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VCC pin and also
shows that VCCA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VCCA pin.
3.3V
VCC
.01µF
10Ω
VCCA
.01µF
10µF
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843252-45 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS843252AG-45 REV. A OCTOBER 23, 2008
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FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Schematic Example
Figure 5 shows an example of ICS843252-45 application
optimizing frequency accuracy. Two examples of LVPECL
schematic. In this example, the device is operated at VCC = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF
and C2 = 27pF are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted for
terminations are shown in this schematic. Additional termination
approaches are shown in the LVPECL Termination Application
Note.
3.3V
R1
R2
133
133
Zo = 50 Ohm
QA
TL1
+
-
Zo = 50 Ohm
nQA
U1
TL2
CLK_ENB
CLK_ENA
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R3
R4
CLK_EN_A
VEE
CLK_EN_B
VEE
82.5
82.5
QB
QA
QB
nQB
VCCO_A
nQA
nQB
VCCOA
nc
VCCO_B
XTAL_IN
XTAL_OUT
VEE
VCCO_B
0.1u
C4
VCCA
VCC
0.1u
C7
Zo = 50 Ohm
VCC
R5
+
VCCA
10
C3
0.1u
C5
Zo = 50 Ohm
0.1u
C6
-
10u
C1
27pF
R7
50
R8
50
VCC=3.3V
X1 25MHz
18pF
VCCO_A=3.3V
VCCO_B=3.3V
R9
50
Logic Input Pin Examples
Set Logic
Optional
LVPECL
C2
Set Logic
Input to
'0'
Y-Termination
VCC
VCC
27pF
Input to
'1'
RU1
1K
RU2
Not Install
To Logic
Input
To Logic
Input
pins
pins
RD1
RD2
1K
Not Install
Figure 5. ICS843252-45 Schematic Example
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS843252AG-45 REV. A OCTOBER 23, 2008
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843252-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843252-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA = 259.9mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 259.9mW + 60mW = 319.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 92.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.320W * 92.4°C/W = 99.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 7. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.4°C/W
88.0°C/W
85.9°C/W
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Reliability Information
Table 8. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.4°C/W
88.0°C/W
85.9°C/W
Transistor Count
The transistor count for ICS843252-45 is: 2039
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 9. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Ordering Information
Table 10. Ordering Information
Part/Order Number
843252AG-45
843252AG-45T
843252AG-45LF
843252AG-45LFT
Marking
43252A45
43252A45
3252A45L
3252A45L
Package
16 Lead TSSOP
16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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Clock Generator, 333.33MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
ICS843256AGIT
Clock Generator, 333.33MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
ICS843256AGLF
FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICSI
ICS843256AGLFT
FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICSI
ICS843256AGT
FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICSI
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