ICS664G-02T [IDT]
Video Clock Generator, 74.25MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16;
| 型号： | ICS664G-02T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Video Clock Generator, 74.25MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
PECL DIGITAL VIDEO CLOCK SOURCE
ICS664-02
Description
Features
The ICS664-02 provides clock generation and conversion
for clock rates commonly needed in HDTV digital video
equipment. The ICS664-02 uses the latest Phase-Locked
Loop (PLL) technology to provide excellent phase noise
and long-term jitter performance for superior
• Packaged in 16-pin TSSOP
• Available in Pb (lead) free package
• Clock or crystal input
• Low phase noise
• Low jitter
• Exact (0 ppm) multiplication ratios
• Power-down control
• Improved phase noise over ICS660
• Differential outputs
synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use the
ICS661.
Please contact IDT if you have a requirement for an input
and output frequency not included in this document. IDT
can rapidly modify this product to meet special
requirements.
• Supports SMTE 292M HD-SDI standard for HDTV
broadcast
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD (P2)
VDD (P3)
VDDO
VDD (P10)
X2
Crystal
Oscillator
X1/REFIN
SELIN
PLL Clock
Synthesis
CLK
CLK
S3:0
4
GND (P12)
GND (P6)
GND (P5)
IDT™ / ICS™ PECL DIGITAL VIDEO CLOCK SOURCE
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PECL CLOCK SYNTHESIZER
Pin Assignment
Output Clock Selection Table
Input
Frequency
Output
Frequency
(MHz)
X1/REFIN
VDD
VDD
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
S3
S2
S1
S0
(MHz)
VDDO
CLK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Power down
Input Freq
74.25
Pass thru
27
CLK
27
74.175824
74.25
GND
GND
S3
GND
13.5
SELIN
VDD
S1
13.5
74.175824
RESERVED
RESERVED
54
RESERVED
RESERVED
74.25
S2
74.175824
RESERVED
RESERVED
54
54
RESERVED
RESERVED
74.25
16-pin 4.40 mil body, 0.65 mm pitch TSSOP
54
74.175824
13.5
54
27
13.5
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Connect this pin to a crystal or clock input
1
2
X1/REFIN
VDD
VDD
S0
Input
Power Power supply for crystal oscillator.
Power Power supply for PLL.
3
4
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
5
GND
GND
S3
Power Ground for PLL.
6
Power Ground for oscillator.
7
Input
Input
Input
Power
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
8
S2
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Power supply.
9
S1
10
11
12
13
14
15
16
VDD
SELIN
GND
CLK
CLK
VDDO
X2
Low for clock input, high for crystal. On chip pull-up.
Power Ground for output stage
Output Complimentary clock output.
Output Clock output.
Power Power supply for output stage.
Input
Connect this pin to a crystal. Leave open if using a clock input.
IDT™ / ICS™ PECL DIGITAL VIDEO CLOCK SOURCE
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PECL CLOCK SYNTHESIZER
Application Information
to ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally required
crystal load capacitance. To reduce possible noise pickup,
use very short PCB traces (and no vias) been the crystal
and device.
Termination Resistor
Terminate the outputs with 50Ω to ground.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS664-02 must be isolated from system power supply
noise to perform optimally.
The value of the load capacitors can be roughly determined
by the formula C = 2(C - 6) where C is the load capacitor
L
connected to X1 and X2, and C is the specified value of the
L
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
ICS664-02 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
load capacitance for the crystal. A typical crystal C is 18 pF,
L
so C = 2(18 - 6) = 24 pF. Because these capacitors adjust
the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Recommended Power Supply Connection for
Optimal Device Performance
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
VDD Pin
Ferrite
Bead
Connection to 3.3V
VDD Pin
Power Plane
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
VDD Pin
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
0.01 F Decoupling Capacitors
3) To minimize EMI, and obtain the best signal integrity, the
50Ω series termination resistor should be placed close to
the clock output.
All power supply pins must be connected to the same
voltage, except VDDO, which may be connected to a lower
voltage in order to change the output level.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS664-02. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
To achieve the absolute minimum jitter, power the part with
a dedicated LDO regulator, which will provide high isolation
from power supply noise. Many companies produce very
small, inexpensive regulators; an example is the National
Semiconductor LP2985.
Crystal Load Capacitors
If a crystal is used, the device crystal connections should
include pads for capacitors from X1 to ground and from X2
IDT™ / ICS™ PECL DIGITAL VIDEO CLOCK SOURCE
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PECL CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS664-02. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
5.5 V
-0.5V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260° C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+3.6
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C
Parameter
Symbol
VDD
Conditions
Min.
3.0
Typ.
Max.
Units
3.6
V
V
Operating Voltage
VDDO
IDD
2.5
VDD
Supply Current
No Load
25
75
mA
µA
V
Standby Supply Current
Input High Voltage
Input Low Voltage
IDDPD
V
2
IH
V
0.8
V
IL
Output High Voltage
Output Low Voltage
Input Capacitance
Internal Pull-up Resistor
V
VDDO-1.5
VDDO-2.0
VDDO-1.1
VDDO-1.8
V
OH
V
V
OL
C
R
input pins
7
pF
kΩ
IN
120
PU
IDT™ / ICS™ PECL DIGITAL VIDEO CLOCK SOURCE
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PECL CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70° C
Parameter
Crystal Frequency
Symbol
Conditions
Min.
Typ.
Max. Units
28
1.5
1.5
60
MHz
ns
Output Clock Rise Time
Output Clock Fall Time
Output Duty Cycle
t
20% to 80%, 15 pF load
80% to 20%, 15 pF load
at VDD/2, 15 pF load
OR
t
ns
OF
t
40
49 to 51
%
OD
Inputs out of PD state
to clocks stable
Power-up Time
t
t
10
1
ms
µs
PU
PD
Inputs in PD state to
clocks off
Power-down Time
Jitter, Short term
Jitter, Long term
70
ps p-p
ps p-p
10 µs delay
300
Single Sideband Phase
Noise
10 kHz offset
-120
0
dBc
Actual Mean Frequency
Error versus Target
ppm
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
IDT™ / ICS™ PECL DIGITAL VIDEO CLOCK SOURCE
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PECL CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
E1
e
L
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
D
0.45
0.75
0.018
0.030
α
0°
8°
0°
8°
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
664G-02*
Marking
664G-02
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
664G-02T*
664G-02
Tape and Reel
Tubes
664G-02LF
664G02LF
664G02LF
664G-02LFT
Tape and Reel
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ PECL DIGITAL VIDEO CLOCK SOURCE
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ICS664-02
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ICS664-02
PECL DIGITAL VIDEO CLOCK SOURCE
PECL CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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