ICS513MLFT [IDT]
Clock Generator, 140MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8;
| 型号： | ICS513MLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 140MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
LOCO™ PLL CLOCK GENERATOR
ICS513
Description
Features
TM
The ICS513 LOCO is the most cost effective way to
• Packaged as 8-pin SOIC or die
• Pb (lead) free package
generate a high quality, high frequency clock output
from a 14.31818 MHz crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked-Loop (PLL) techniques,
the device uses a standard, inexpensive crystal to
produce output clocks up to 100 MHz.
• IDT’s lowest cost PLL clock plus reference
• Produces common computer frequencies
• Input crystal frequency typically 14.3182 MHz
• Output clock frequencies up to 100 MHz from a
14.3182 MHz crystal or input clock
Stored in the chip’s ROM is the ability to generate five
different output frequencies, allowing one chip to work
in different speed processor systems.
• Low jitter of 40 ps (one sigma)
• Compatible with all popular CPUs
• Duty cycle of 45/55 up to 200 MHz
• Custom frequencies available
The device also has a power-down mode that turns off
the clock outputs when both select pins are low. In this
mode, the internal PLL is not running.
• Operating voltage of 3.3 V to 5.5 V
• Power-down mode turns off chip
• 25 mA drive capability at TTL levels
• Advanced, low-power CMOS process
Block Diagram
VDD
2
PLL Clock
Synthesis
S1:0
CLK
and Control
Circuitry
X1/ICLK
14.31818 MHz crystal
Crystal
Oscillator
REF
or clock input
X2
GND
Optional crystal capacitors
IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR
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Pin Assignment
Clock Decoding Table (MHz) with
14.31818 MHz Crystal or Clock Input
X1/ I CLK
VDD
8
7
6
5
1
2
3
4
X2
S1 S0
CLK
Multiplier
—
Accuracy
—
0
0
0
1
0
1
0
1
Power-down CLK
S1
100
24
6.984
1.676
1
1 ppm
1 ppm
0 ppm
0.017%
0.044%
GND
S0
M
M
1
REF
CLK
14.31818
48
3.353
0.2576
8-pi n (150 mi l ) SOI C
1
3.6864
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
CLK and REF stop low in power-down state
Pin Descriptions
Pin
Pin
Pin
Type
Pin Description
Number Name
1
2
3
4
5
6
XI/ICLK
VDD
GND
REF
CLK
Input
Power
Power
Output
Output
Crystal connection to a 14.31818 MHz crystal or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
S0
Tri-level Input Select 0 for output clock. Connect to GND or VDD or float. See
table above.
7
8
S1
X2
Tri-level Input Select 1 for output clock. Connect to GND or VDD or float. See
table above.
Output
Crystal connection to a 14.31818 MHz crystal. Leave unconnected
for clock input.
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X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS513 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close
to the ICS513 to minimize lead inductance. No external
power supply filtering is required for the ICS513.
The value (in pF) of these crystal caps should equal (C
L
-12 pF)*2. In this equation, C = crystal load capacitance
L
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
Series Termination Resistor
A 33Ωterminating resistor can be used next to the CLK
and REF pins for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS513. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
260°C
Soldering Temperature
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Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
+70
+3.0
+5.5
V
DC Electrical Characteristics
VDD=5.0 V 5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
V
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
V
ICLK (pin 1)
(VDD/2)+1 VDD/2
IH
V
ICLK (pin 1)
VDD/2 (VDD/2)-1
0.8
V
IL
V
S0
S0
S1
S1
S1
2.0
V
IH
Input Low Voltage
V
V
IL
IH
IM
Input High Voltage
V
VDD-0.5
V
Input Mid Voltage
V
VDD/2
0.5
V
Input Low Voltage
V
V
IL
Output High Voltage
Output Low Voltage
V
I
I
= -25 mA
= 25 mA
2.4
V
OH
OH
OL
V
0.4
V
OL
IDD Operating Supply Current
No load, 100MHz
S1=S0=0
20
mA
mA
IDD Power-down Supply
Current, 3.3 V
1.5
Short Circuit Current
CLK output
Pin 6
+70
270
4
mA
kΩ
pF
On-Chip Pull-up Resistor
Input Capacitance, S1, S0
Pins 6, 7
AC Electrical Characteristics
VDD = 5.0 V 5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
5
Typ.
14.31818
14.31818
100
Max. Units
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5 V
Output Frequency, VDD = 3.0 to 3.6 V
Output Clock Rise Time
F
F
27
50
MHz
MHz
MHz
MHz
ns
IN
2
IN
F
F
14
14
140
100
OUT
OUT
100
t
0.8 to 2.0 V
1
OR
Output Clock Fall Time
t
2.0 to 8.0 V
1
ns
OF
Output Clock Duty Cycle
t
1.5 V,up to 140 MHz
45
49-51
55
%
OD
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Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Power-up time, from PD to outputs
stable
Power-down time, from running to PD
state
Absolute Clock Period Jitter
5
10
ms
ns
ps
ps
50
t
t
Deviation from
mean
+140
50
ja
One Sigma Clock Period Jitter
js
Thermal Characteristics
Parameter
Symbol
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
150
140
120
40
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
Marking Diagram
8
5
ICS513ML
YYWW
######
1
4
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year and the week.
3. “L” designates Pb (lead) fee package.
IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
H
h
L
5.80
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
1
2
0.25
0.40
0°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
513MLF
Marking
ICS513ML
ICS513ML
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
513MLFT
Tape and Reel
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Deviec Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR
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For Sales
800-345-7015
For Tech Support
www.idt.com/go/clockhelp
408-284-8200
Fax: 408-284-2775
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Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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