ICS307G-03 [IDT]
Clock Generator, 270MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16;
| 型号： | ICS307G-03 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 270MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SERIALLY PROGRAMMABLE CLOCK SOURCE
ICS307-03
Description
Features
The ICS307-03 is a dynamic, serially programmable clock
source which is flexible and takes up minimal board space.
Output frequencies are programmed via a 3-wire SPI port.
• Crystal or clock reference input
• 3.3 V CMOS outputs
• Three outputs can be individually configured or shut off
• Small 16-pin TSSOP package
An advanced PLL coupled to an array of configurable
output dividers and three outputs allows low-jitter
generation of frequencies from 200 Hz to 270 MHz.
• Reprogrammable during operation
• 3-wire SPI serial interface
The device can be reprogrammed during operation, making
it ideal for applications where many different frequencies
are required, or where the output frequency must be
determined at run time. Glitch-free frequency transitions,
where the clock period changes slightly over many cycles,
are possible.
• Glitch-free output frequency switching
• User selectable charge pump current and damping
resistor
• Power-down control via hardware pin or software control
bit
• Programming word can be generated by IDT VersaClock
II Software
• Directly programmable via VersaClock II Software and a
Windows PC parallel port
• Available in Pb (lead) free package, RoHS 5/6 compliant
• Industrial temperature range available
Block Diagram
Charge Pump
(Table 3)
(Table 1)
Resistor
(Table 4)
REF Divide
CP
300
pF
Divider
2 - 8232
CLK1
11pF
X1
X2
1-2055
[Bit 110]
[Bit 122]
(Table 5)
VCO DIVIDE
12-2055
(Table 2)
1
0
Divider
2 - 34
CLK2
CLK3
[Bit 111]
[Bit 129]
DIN
CS
[Bit 123]
(Table 6)
Programming
Register
(132 bits)
SCLK
1
0
Divider
2 - 34
[Bit 124]
(Table 7)
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
1
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Pin Assignment
X1
VDD
VDD
VDD
GND
GND
GND
CLK1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
PD
CLK3
GND
CLK2
DIN
CS
SCLK
16-pin TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Connect to input reference clock or crystal.
1
2
X1
VDD
VDD
VDD
GND
GND
GND
CLK1
SCLK
CS
XI
Power Power connection for crystal oscillator.
Power Power connection for PLL.
3
4
Power Power connection for inputs and outputs.
Power Ground connection for crystal oscillator.
Power Ground connection for PLL.
5
6
7
Power Ground connection for inputs and outputs.
Output Clock 1 output.
8
9
Input
Input
Input
Programming interface - Serial clock input. Internal pull-up.
10
11
12
13
14
15
16
Programming interface - LOAD input. Internal pull-down.
Programming interface - Serial data input. Internal pull-up.
DIN
CLK2
GND
CLK3
PD
Output Clock 2 output.
Power Ground connection.
Output Clock 3 output.
Input
-
Crystal, PLL, and outputs are powered-down when low. Internal pull-up.
Connect to crystal. Leave open if reference clock input is used.
X2
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
2
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 1. Input Divider
Bits
Divide Value 12
11
10
9
8
7
6
5
4
3
2
1
0
Rule
1
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
X
X
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
X
X
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1+ Bit 0
1 + Bit 0
3
subtract 2 from the
desired value, convert to
binary, invert, and apply
to bits 5...2
4
5
Bits [1..0] = 10
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
subtract 8 from the
desired divide value,
convert to binary, and
apply to bits 11...2
Bits [1..0] = 11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2054
2055
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
Table 2. VCO Divider
Bits
18
0
Divide Value
23
0
22
0
21
20
0
19
17
16
0
15
1
14
0
13
0
Rule
12
13
14
0
0
0
0
0
0
0
0
0
subtract 8 from the desired
divide value, convert to
binary, and apply to bits
23...13
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
2054
2055
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
3
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 3. Charge Pump Current
Bits
Charge Pump Current (µA)
93
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
92
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
91
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
128
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
127 Rule
Icp = ([128...127]+1)*1.25µA*([93 92 91] + 1)
1.25
2.5
2.5
3.75
3.75
5
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
1
5
5
6.25
7.5
7.5
7.5
8.75
10
10
10
11.25
12.5
15
15
15
17.5
18.75
20
20
22.5
25
26.25
30
30
35
40
Table 4. Loop Filter Resistor
Bits
Resistor Value
90
0
89
0
64 k
52 k
16 k
4 k
0
1
1
0
1
1
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
4
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 5. Output Divider for Output 1
Divide
Bits
Value 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 Rule
2
3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
0
0
0
1
1
0
1
1
1
0
0
1
X
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
0
4
5
6
7
8
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
9
X
1
X
1
X
0
10
11
12
13
14
15
X
1
X
1
X
0
X
1
X
0
X
1
subtract 6 from the desired divide
value, convert to binary, invert, and
apply to bits 102..98
1
0
1
set bits [97..95] = 100
36
37
38
X
X
0
X
X
0
X
X
0
X
X
0
X
X
1
X
X
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
output divide =
((([109..101]+3)*2)+[98])*2^[100..99]
set bits [95..97] = 101
set bits [95..97] = 101 †
(† this Rule applies to Divide Values
38-8232)
39
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
(increments of 1)
1029
1030
1032
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
(increments of 2)
2056
2058
2060
2064
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
(increments of 4)
4112
4116
4120
4128
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
(increments of 8)
8224
8232
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
5
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 6. Output Divider for Output 2
Bits
Divide Value
117
1
116
1
115
1
114
1
113 Rule
output divide = ([117..114]+2)*2^[113])
2
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
6
1
1
1
0
8
1
1
0
1
10
12
14
16
18
20
22
24
26
28
30
32
34
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Table 7. Output Divider for Output 3
Bits
Divide Value
121
1
120
1
119
1
118
1
94
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rule
output divide = ([121..118]+2)*2^[94])
2
4
1
1
1
1
6
1
1
1
0
8
1
1
0
1
10
12
14
16
18
20
22
24
26
28
30
32
34
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
6
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 8. Miscellaneous Control Bits
Bit
24~88
110
111
112
122
123
124
125
126
129
130
131
Function
Reserved—set to 0
OE1—set to 1 to enable CLK1
OE2—set to 1 to enable CLK2
1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO
Crystal Input = 1, Clock Input = 0
Selects source for CLK2 (see block diagram)
Selects source for CLK3 (see block diagram)
Reserved—set to 0
Reserved—set to 0
OE3—set to 1 to enable CLK3
Reserved—set to 0
Reserved—set to 0
External Components
The ICS307-03 requires a minimum number of external components for proper operation.
Decoupling Capacitors
TheICS307-03 requires 0.01µF decoupling capacitors to be connected between each VDD pin and the Ground Plane. The
0.01µF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead inductance.
Output Termination
The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation with single
ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50 Ohm transmission
line without the need for any series resistors.
Crystal Selection
A parallel resonant, fundamental mode crystal with a load
(correlation) capacitance of 12 pF should be used. For
crystals with a specified load capacitance greater than 12
pF, additional crystal capacitors may be connected from
each of the pins X1 and X2 to ground as shown in the Block
Diagram on page 1. The value (in pF) of these crystal caps
should be = (C -12)*2, where C is the crystal load
L
L
capacitance in pF.
For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.
Initial Output Frequency
ICS307-03 on-chip registers are initially configured to
provide a 1x output clock on the CLK1 output, and 0.5x clock
on CLK2 and CLK3. The output frequency will be the same
as the input clock or crystal for input frequencies from 10 -
50 MHz. This is useful when the ICS307-03 needs to
provide an initial system clock at power-up.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
7
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Determining and Controlling the Output Frequency with VersaClockTM II
The ICS307-03 is directly supported by the IDT provided
software called VersaClock II. Complete programming
words for this device can be calculated on any Windows PC
by running the VersaClock II software and simple inputting
desired input and output frequencies. Once the software
generates an appropriate programming word, it may then be
either copied to the Windows clipboard or even directly
programmed into the ICS307-03 via the host computers
parallel port.
For more information on VersaClock II, please visit
www.icst.com or send an e-mail to ics-mk@icst.com.
Manually Determining the Output Frequency
The user has full control over the desired output frequency
as long as it is operated within the limits shown in the AC
Electrical Characteristics.
Also, the following operating ranges should be observed.
V
R
VCOmin < InputFrequency ⋅ --- < VCOmaxfreq
The output of the ICS307-03 can be determined by the
following equation:
Input Frequency
20kHz < ------------------------------------------ < 100MHz
R
V
--------------------
CLK1Frequency = InputFrequency ⋅
R ⋅ OD
To determine the best combination of VCO, reference, and
output dividers, please use the VersaClock II software
mentioned above.
Where:
VCO Divider (V) = 12 to 2055
Reference Divider Word (R) = 1 to 2055
Output Divider = values in tables 5, 6, 7
Default Register Values
At power-up, the registers are set to:
ref divide = 5
VCO divide = 50
output divide = 10 (CLK1)
output divide = 2 (CLK2)
output divide = 2 (CLK3)
bit 123, 124 = 1
ICP = 3.75 µA
R = 16k
Default programming word is:
0x31FFDFFEE3BFFFFFFFFFFFFFFFF055FF2
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
8
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Programming Interface
The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time after
power is properly applied. If V or R values are changed, the frequency will transition smoothly to the new value
without glitches or short cycles. However, changing any divider or mux in the output signal path may generate a
glitch.
The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data bit value in
the rising edge. It latches the most recently shifted 132 bit values into the control register of device whenever CS is
high. Care must be taken to ensure that CS is always low until the system is ready to load in a new register value
and that SCLK is never toggled high when CS is high.
The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit 112 held
low) with the waveform and timing shown below:.
Figure 2: ICS307-03 Programming Timing Diagram
DIN
131
130
129
thold
128
1
0
2
tsetup
SCLK
CS
tw
ts
Table 8: AC Parameters for Programming the ICS307-03
Parameter
Condition
Setup time
Min.
2.5
2.5
2.5
10
Max.
Units
ns
t
SETUP
t
Hold time after SCLK
Data wait time
ns
HOLD
t
ns
W
t
Strobe pulse width
SCLK Frequency
ns
S
200
MHz
Programming with VersaClock Software
The VersaClock II Software not only generates the programming word for the user, it can also be used to program the device
via the host computer’s parallel port. Demonstration boards are available from IDT that allows the VersaClock II S/W to
directly connect the ICS307-03 to a Windows based PC’s DB-25 parallel port connector and programmed simply by pressing
the “Program Part” button.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
9
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS307-03. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability.
Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
Storage Temperature
Soldering Temperature
5 V
-0.5 V to VDD+0.5 V
-65 to +150° C
260°C
Recommended Operating Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+3.6
V
DC Electrical Characteristics
VDD=3.3 V 0.3 V, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Symbol
Conditions
Min.
3.0
2
Typ.
Max.
Units
VDD
3.6
0.8
0.4
V
V
V
V
V
V
V
IH
V
IL
V
I
I
I
= -4 mA
= 4 mA
2.4
OH
OH
OL
OH
V
OL
Output High Voltage,
CMOS level
V
= -6.5 mA
VDD-0.4
OH
Tri-state Output Leakage
1
µA
Operating Supply Current
IDD
27 MHz crystal
24
mA
No load, 100 MHz out,
all outputs enabled
Short Circuit Current
Input Capacitance
CLK outputs
60
4
mA
pF
C
R
IN
On-Chip Pull-up Resistor
240
100
kΩ
kΩ
PU
PD
On-Chip Pull-down
Resistor
R
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
10
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
AC Electrical Characteristics
VDD = 3.3 V 0.3 V, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
F
Fundamental crystal
Clock
3
27
MHz
MHz
IN
0.1
300
Clock Output Frequency
F
5 pF load
0.0002
0.0002
270
200
MHz
MHz
ns
OUT
15 pF load
Output Clock Rise/Fall Time
Output Clock Duty Cycle
t
t
20 to 80% (5 pF load)
Output Divides <> 3
Output Divide = 3
1.5
R, F
45
40
49-51
55
60
10
%
%
Frequency Transition time
STROBE high to CLK
out
3
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Note 2
50
ps
ps
t
Deviation from mean,
Note 2
120
ja
VCO Frequency
Divider 1 Input
VCO
100
730
540
MHz
MHz
F
Output divider 1 = 2
(5 pF load)
Output divider 1 = 2
(15 pF load)
400
720
600
570
730
540
400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Output divider 1 = 3
(5 pF load)
Output divider 1 = 3
(15 pF load)
Output divider 1 = 38
~ 1029
All other Output
Divider 1 values
Divider 2 and 3 Inputs
Output divider 2, 3 = 2
(5 pF load)
Output divider 2, 3 = 2
(15 pF load)
Output divider 2, 3=12
440
500
MHz
MHz
Output divider 2, 3 =
16, 24, 28 and 32
All other Output
730
MHz
Divider 2 & 3 values
Note 1: Measured with 15 pF load.
Note 2: Jitter performance will change depending on configuration settings.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
11
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
16
Millimeters
Inches*
Symbol
Min Max
Min
Max
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
--
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
6.40 BASIC
4.30 4.50
0.65 Basic
0.002
0.032
0.007
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
E1
E
INDEX
AREA
C
D
E
E1
e
L
1
2
D
0.45
0.75
0.018
0.030
α
0°
8°
0°
8°
aaa
--
0.10
--
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
307G-03
Marking
307G-03
Shipping packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
307G-03T
307G-03
Tape and Reel
Tubes
307G-03LF
307G-03LFT
307GI-03
307G03LF
307G03LF
307GI-03
307GI-03
307GI03L
307GI03L
Tape and Reel
Tubes
307GI-03T
Tape and Reel
Tubes
307GI-03LF
307GI-03LFT
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE
12
ICS307-03
REV H 071708
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
ICS307GI-03LFT
Clock Generator, 270MHz, PDSO16, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
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