ICS280PGT [IDT]
Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16;
| 型号： | ICS280PGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总10页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER ICS280
Description
Features
The ICS280 field programmable spread spectrum clock
synthesizer generates up to four high-quality,
high-frequency clock outputs including multiple reference
clocks from a low-frequency crystal input. It is designed to
replace crystals, crystal oscillators and stand alone spread
spectrum devices in most electronic systems.
• Packaged as 16-pin TSSOP
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Configurable Spread Spectrum Modulation
• Input crystal frequency of 5 to 27 MHz
• Input clock frequency of 3 to 166 MHz
• Up to four reference outputs
TM
Using IDT’s VersaClock software to configure PLLs and
outputs, the ICS280 contains a One-Time Programmable
(OTP) ROM for field programmability. Programming
features include input/output frequencies, spread spectrum
amount and eight selectable configuration registers.
• Operating voltages of 3.3 V
• Controllable output drive levels
• Advanced, low-power CMOS process
• Available in RoHS compliant packaging
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
The ICS280 is also available in factory programmed custom
versions for high-volume applications.
Block Diagram
3
VDD
PLL1 with
Spread
Spectrum
3
S2:S0
OTP
ROM
CLK1
CLK2
CLK3
CLK4
with PLL
Values
Divide
Logic
and
Output
Enable
Control
PLL2
PLL3
Crystal or
Clock Input
X1/ICLK
X2
Crystal
Oscillator
3
GND
External capacitors
are required with a crystal input.
PDTS
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 1
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Pin Assignment
S2
GND
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
PDTS
GND
CLK4
CLK3
VDD
X2
S1
VDD
CLK1
CLK2
GND
X1/ICLK
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
7
GND
S0
Power
Input
Connect to ground.
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
S1
Input
VDD
CLK1
CLK2
GND
Power
Output Output clock 1. Weak internal pull-down when tri-state.
Output Output clock 2. Weak internal pull-down when tri-state.
Power
XI
Connect to ground.
8
X1/ICLK
X2
Crystal input. Connect this pin to a crystal or external input clock.
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect to +3.3 V.
9
XO
10
11
12
13
VDD
Power
CLK3
CLK4
GND
Output Output clock 3. Weak internal pull-down when tri-state.
Output Output clock 4. Weak internal pull-down when tri-state.
Power
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
14
PDTS
Input
Connect to +3.3 V.
15
16
VDD
S2
Power
Input
Select pin 2. Internal pull-up resistor.
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The ICS280 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
External Components
The ICS280 requires a minimum number of external
components for proper operation.
Each output frequency can be represented as:
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
M
N
----
OutputFreq = REFFreq ⋅
Output Drive Control
Decoupling Capacitors
The ICS270 has two output drive settings. Low drive should
be selected when outputs are less than 100 MHz. High drive
should be selected when outputs are greater than 100 MHz.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
As with any high-performance mixed-signal IC, the ICS280
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The value (in pF) of these crystal caps should equal (C -6
The ICS280 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electromagnetic interference (EMI). The
modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
L
pF)*2. In this equation, C = crystal load capacitance in pF.
L
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
ICS280 Configuration Capabilities
The architecture of the ICS280 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 3
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applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
The ICS280 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between 0.125% to 2.0%. For down spread,
the frequency can be modulated between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS280. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature (ICS280PG/PGLF)
Ambient Operating Temperature (ICS280PGI/PGILF)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
+85
° C
+3.135
+3.3
+3.465
4
V
ms
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 4
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Operating Voltage
VDD
3.135
3.465
V
Config. Dependent - See
VersaClock Estimates
mA
TM
Four 33.3333 MHz outs,
VDD=3.3V;
PDTS = 1, no load, Note 1
22
mA
Operating Supply Current
Input High Voltage
IDD
PDTS = 0, no load
S2:S0
500
µA
V
Input High Voltage
V
VDD/2+1
VDD-0.5
VDD/2+1
IH
Input Low Voltage
V
S2:S0
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -8 mA (Low Drive);
= -12 mA (High Drive)
V
V
OH
OH
OH
V
I
I
= 8 mA (Low Drive);
= 12 mA (High Drive)
0.4
OL
OL
OL
I
Low Drive
High Drive
40
70
OS
mA
Nom. Output Impedance
Internal Pull-up Resistor
Z
20
Ω
O
R
S2:S0, PDTS
CLK outputs
190
120
kΩ
kΩ
PUS
Internal Pull-down
Resistor
R
PD
Input Capacitance
C
Inputs
4
pF
IN
Note 1: Example with 25 MHz crystal input, four unloaded 33.3 MHz outputs.
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 5
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Fundamental crystal
Clock Input
Min. Typ. Max. Units
Input Frequency
F
5
3
27
MHz
MHz
MHz
ns
IN
166
200
Output Frequency
0.314
Output Rise/Fall Time
t
t
80% to 20%, high drive,
Note 1
1.0
2.0
OF
Output Rise/Fall Time
80% to 20%, low drive,
Note 1
ns
OF
Duty Cycle
Note 2
40
49-51
TBD
4
60
%
Output Frequency Synthesis Error
Configuration Dependent
ppm
ms
PLL lock-time from
power-up
10
2
Power-up Time
PDTS goes high until
stable CLK output,
Spread Spectrum Off
0.2
4
ms
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
7
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration Dependent
50
ps
ps
t
Deviation from Mean.
+200
ja
Configuration Dependent
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
78
70
68
37
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 6
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Marking Diagrams
Marking Diagrams (Pb free)
16
9
16
9
280PGL
######
YYWW
280PG
######
YYWW
1
8
9
1
8
9
16
16
280PGIL
######
YYWW
280PGI
######
YYWW
1
8
1
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes RoHS compliant package.
5. Bottom marking: country of origin.
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 7
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Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Inches
Max
Symbol
Min
Max
1.20
0.15
1.05
0.30
0.20
5.10
Min
—
A
A1
A2
b
—
.047
0.006
0.041
0.012
E1
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E
INDEX
AREA
C
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
1 2
6.40 BASIC
4.30 4.50
0.65 Basic
E1
e
D
L
0.45
0.75
.018
.030
α
0°
8°
0°
8°
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 8
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Ordering Information
Part / Order Number
280PG*
Marking
Shipping Packaging
Tubes
Package
Temperature
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
0 to +70°C
-40 to +85°C
0 to +70°C
-40 to +85°C
0 to +70°C
-40 to +85°C
0 to +70°C
-40 to +85°C
0 to +70°C
-40 to +85°C
0 to +70°C
-40 to +85°C
See page 7
280PGI*
Tubes
280PGLF
Tubes
280PGILF
Tubes
280G-XX*
280G-XX
280GIXX
280GXXL
280GIXXL
280G-XX
280GIXX
280GXXL
280GIXXL
Tubes
280GI-XX*
Tubes
280G-XXLF
280GI-XXLF
280G-XXT*
280GI-XXT*
280G-XXLFT
280GI-XXLFT
Tubes
Tubes
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
*NOTE: EOL for non-green parts to occur on ±/13/10 per PDN U-09-01
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The 280G-XX, 280G-XXLF, 280GI-XX, and 280GI-XXLF are factory programmed versions of the 280PG, 280PGLF, 280PGI, and
280PGILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on
file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing
representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
TM
VersaClock
is a trademark of IDT, Inc. All rights reserved.
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 9
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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