ICS252MI-XXT [IDT]
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER; 现场可编程双路输出SS VersaClock合成
| 型号： | ICS252MI-XXT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER |
| 文件： | 总11页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
ICS252
Description
Features
The ICS252 is a low cost, dual-output, field programmable
clock synthesizer. The ICS252 can generate two output
frequencies from 314 kHz to 200 MHz using up to two
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
• 8-pin SOIC package
• Two addressable registers
• Input crystal frequency of 5 to 27 MHz
• Clock input frequency of 3 to 150 MHz
• Output clock frequencies up to 200 MHz
• Configurable Spread Spectrum Modulation
™
Using IDT’s VersaClock software to configure the PLL and
output, the ICS252 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include 4 selectable configuration registers.
• Operating voltage of 3.3 V
• Replaces multiple crystals and oscillators
• Controllable output drive levels
The device employs Phase-Locked Loop (PLL) techniques
to run from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
• Advanced, low-power CMOS process
• Available in RoHS 5 (green) or RoHS 6 (green and lead
free) compliant package
The device also has a power-down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS252 is also available in factory programmed custom
versions for high-volume applications.
Block Diagram
VDD
OTP
SEL
PLL1
PLL2
Divide
Logic
and
Output
Enable
Control
ROM
with
CLK1
CLK2
PLL
Values
X1
Crystal
Oscillator
Crystal
X2
GND
External capacitors
are required.
PDTS
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Pin Assignment
Output Clock Selection Table
SEL CLK1 (MHz) CLK2 (MHz)
Spread
Percentage
User
Configurable
User
S E L
V D D
1
2
3
4
8
7
6
5
P D T S
G N D
0
1
User
Configurable
User
User
Configurable
User
X 1 / I C L K
X 2
C L K 2
C L K 1
Configurable
Configurable
Configurable
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Pin Description
Type
Input
Power
XI
1
2
3
4
5
6
7
SEL
VDD
Select pin for frequency selection on CLK1 and CLK2. Internal pull-up resistor.
Connect to +3.3 V.
X1/ICLK
X2
Connect this pin to a crystal or external clock input.
Connect this pin to a crystal, or float for clock input.
XO
CLK1
CLK2
GND
Output Clock1 output. Weak internal pull-down, low when power down.
Output Clock2 output. Weak internal pull-down, low when power down.
Power
Connect this to ground.
Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up
resistor. The pin must be tied either directly or through the external resistor to
VDD ro GND. External resistor value must be less than 15kOhm.
8
PDTS
Input
External Components
The ICS252 requires a minimum number of external
components for proper operation.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance
of the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS252
must be isolated from system power supply noise to perform
optimally.
The value (in pF) of these crystal caps should equal (C -6
L
pF)*2. In this equation, C = crystal load capacitance in pF.
L
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
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noise, the following guidelines should be observed.
be selected when outputs are less than 100 MHz. High drive
should be selected when outputs are greater than 100 MHz.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS252. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Spread Spectrum Modulation
The ICS252 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electro-magnetic interference (EMI).
The modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
ICS252 Configuration Capabilities
The architecture of the ICS252 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS252 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented
as:
The ICS252 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between +/- 0.125% to +/-2.0%. For down
spread, the frequency can be modulated between -0.25% to
-4.0%.
REFFreq
OutputDivide
M
----
--------------------------------------
OutputFreq =
⋅
N
Output Drive Control
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
The ICS252 has two output drive settings. Low drive should
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common VCO frequency can be identified.
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS252. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
-0.5
-0.5
-0.5
-65
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
VDD+ 0.5
VDD+ 0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
° C
° C
° C
Max 10 seconds
260
125
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature (ICS252M)
Ambient Operating Temperature (ICS252MI)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
+85
°C
+3.135
+3.3
+3.465
4
V
ms
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DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
V
Operating Voltage
VDD
3.135
3.3
3.465
Configuration Dependent
- See VersaClock
mA
TM
Two 33.3333 MHz output,
PDTS = 1, no load
Note 1
16
mA
Operating Supply Current
Input High Voltage
IDD
PDTS = 0
SEL
500
µA
V
Input High Voltage
V
VDD/2+1
VDD-0.5
VDD/2+1
IH
Input Low Voltage
V
SEL
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -8 mA (Low Drive);
= -12 mA (High Drive) VDD-0.4
V
V
OH
OH
OH
V
I
I
= 8 mA (Low Drive);
= 12 mA (High Drive)
0.4
OL
OL
OL
I
±70
20
mA
OS
Nominal Output
Impedance
Z
Ω
O
Internal Pull-up Resistor
R
SEL
120
120
kΩ
kΩ
PUP
Internal Pull-down
Resistor
R
Clock outputs CLK1 and
CLK2
PD
Input Capacitance
C
inputs
4
pF
IN
Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V.
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Fundamental Crystal
Input Clock
Min.
5
Typ. Max. Units
Input Frequency
F
27
MHz
MHz
MHz
ns
IN
2
150
200
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
0.314
t
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
1
1
OR
t
ns
OF
40
49-51
4
60
10
%
Power-up Time
PLL lock time from
power-up
ms
PDTS goes high until
stable CLK output,
Spread Spectrum Off
.6
4
2
7
ms
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration Dependent
50
ps
ps
t
Deviation from Mean.
+200
ja
Configuration Dependent
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
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Marking Diagram
Marking Diagram (Pb free)
8
5
8
5
252PML
252PM
######
YYWW
######
YYWW
1
4
1
8
4
8
5
5
252PMIL
######
YYWW
252PMI
######
YYWW
1
4
1
4
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temperature range (if applicable).
4. “L” denotes RoHS compliant package.
5. Bottom marking: country of origin.
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
.0532
.0040
.013
.0688
.0098
.020
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
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Ordering Information
Part / Order Number
ICS252PM
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
-40 to +85° C
0 to +70° C
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
See Page 7 Above
ICS252PMI
ICS252PMLF
ICS252PMILF
ICS252M-XX
ICS252MI-XX
ICS252M-XXLF
ICS252MI-XXLF
ICS252M-XXT
ICS252MI-XXT
ICS252M-XXLFT
ICS252MI-XXLFT
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
252M-XX
252MIXX
252MXXL
252MIXXL
252M-XX
252MIXX
252MXXL
252MIXXL
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
-40 to +85° C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS252M-XX, ICS252M-XXLF, ICS252MI-XX, and ICS252MI-XXLF are factory programmed versions of the ICS252PM,
ICS252PMLF, ICS252PMI, and ICS252PMILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and
a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact
your local IDT sales and marketing representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
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Revision History
Rev. Originator
Date
Description of Change
A
B
C
R.Willner
R.Willner
R.Willner
04/08/05 Preliminary release.
01/16/06 Corrected Block Diagram. Released from Prelim to Final.
06/13/06 Added "-XX" part ordering information and specific note pertaining to custom
configurations of device.
D
E
08/10/07 Removed “Inernal pull-up resistor” info from PDTS pin description and added extrenal
pull-up resistor statement/information.
08/20/07 Changed S1 pin name to “SEL”; removed references to PDTS pin; changed pull-up
resistor value from 190 to 120 kOhms.
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-4522
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
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Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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