ICS2305 [IDT]
3.3 VOLT ZERO DELAY LOW SKEW BUFFER; 3.3 VOLT零延迟低偏移缓冲器
| 型号： | ICS2305 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT ZERO DELAY LOW SKEW BUFFER |
| 文件： | 总9页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
3.3 VOLT ZERO DELAY LOW SKEW BUFFER
ICS2305
Description
Features
The ICS2305 is a low phase noise, high-speed PLL
based, low-skew zero delay buffer. Based on IDT’s
proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides four low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly from
the input (for testing), and can be set to tri-state mode
or to stop at a low level. The PLL feedback is on-chip
and is obtained from the CLKOUT pad.
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Four low skew (<250 ps) outputs
• Device-to-device skew <700 ps
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• 5 V tolerant CLKIN
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V
The ICS2305 is available in two different versions. The
ICS2305-1 is the base part. The ICS2305-1H is a high
drive version with faster rise and fall times.
• Industrial temperature range available
• Packaged in 8-pin SOIC
• Available in Pb (lead ) free package
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD
PLL
CLKOUT
CLK1
CLKIN
CLK2
CLK3
CLK4
GND
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Pin Assignment
CLKIN
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
( 150mil ) SOIC
8 pin
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number
Name
CLKIN
CLK2
CLK1
GND
1
2
3
4
5
6
7
8
Input
Clock input (5 V tolerant).
Output Buffered Clock output 2.
Power
Power
Buffered Clock output 1
Connect to ground.
CLK3
VDD
Output Buffered Clock output 3
Power
Power supply. Connect to 3.3 V.
CLK4
CLKOUT
Output Buffered Clock output 4.
Output Buffered output. Internall feedback on this pin.
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External Components
The ICS2305 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 mF should be connected between VDD and GND on pins 4 and 5, and VDD and GND
on pins 13 and 12, as close to the device as possible. A series termination resistor of 33Ω may be used to
each clock output pin to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS2305. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
CLKIN and FBIN inputs
7 V
-0.5 V to VDD+0.5 V
-0.5 V to 5.5 V
2000 V
Electrostatic Discharge (HBM)
Ambient Operating Temperature (Commercial)
Ambient Operating Temperature (Industrial)
Storage Temperature
0 to +70° C
-40 to +85° C
-65 to +150° C
150°C
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
° C
Ambient Operating Temperature (Industrial)
Ambient Operating Temperature (Commercial)
Power Supply Voltage (measured in respect to GND)
-40
0
+70
° C
+3.0
+3.6
V
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DC Electrical Characteristics
ICS2305M-XX, VDD = 3.3 V ±±0%, Ambient Temperature -40 to +85° C(Industrial), (0-70°C Commercial)
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input Low Current
Input High Current
Output High Voltage
Output Low Voltage
Operating Supply Current
Symbol
Conditions
Min.
3.0
2
Typ.
Max. Units
VDD
3.6
V
V
V
IH
V
I
0.8
50
V
IL
VIN = 0V
VIN = VDD
µA
µA
V
IL
I
100
IH
V
I
I
= -12 mA
= 12 mA
2.4
OH
OH
OL
V
0.4
32
12
V
OL
IDD
No Load
mA
µA
Power Down Supply
Current
CLKIN = 0, Note 1
Short Circuit Current
Input Capacitance
I
Each output
CLKIN
50
5
mA
pF
OS
C
IN
Note 1: When there is no clock signal present at CLKIN, the ICS2305 will enter power down mode. The
PLL is stopped and the outputs are tri-state.
AC Electrical Characteristics
ICS2305M-±, VDD=3.3 V ±±0%, Ambient temperature -40 to +85°C(Industrial), (0-70° C Commercial)
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Output Clock Frequency
Output Clock Frequency
Output Rise Time
f
10 pF load
10
10
133
100
2.5
2.5
60
MHz
MHz
ns
IN
30 pF load
t
0.8 to 2.0 V, outputs loaded
2.0 to 0.8 V, outputs loaded
OR
Output Fall Time
t
ns
OF
DC
Output Clock Duty Cycle
t
measured at 1.4V, Fout=66.67
MHz
40
45
50
50
%
Output Clock Duty Cycle
Device to Device Skew
Output to Output Skew
Input to Output Skew
Cycle to Cycle Jitter
t
measured at 1.4V, Fout=50 MHz
rising edges at VDD/2
55
%
ps
ps
ps
ps
DC
700
250
350
200
rising edges at VDD/2
rising edges at VDD/2
measured at 66.67M, outputs
loaded
PLL Lock Time
Note 2
1.0
ms
Note 2: With VDD at a steady rate and valid input at CLKIN.
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ICS2305M-±H, VDD=3.3 V ±±0%, Ambient temperature -40 to +85° C(Industrial), (0-70°C Commercial),
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Output Clock Frequency
Output Clock Frequency
Output Rise Time
f
10 pF load
10
10
133
100
1.5
1.5
60
MHz
MHz
ns
IN
30 pF load
t
0.8 to 2.0 V, outputs loaded
2.0 to 0.8 V, outputs loaded
OR
Output Fall Time
t
ns
OF
Output Clock Duty Cycle
t
measured at 1.4V, Fout=66.67
MHz
40
45
50
50
%
DC
Output Clock Duty Cycle
Device to Device Skew
Output to Output Skew
Input to Output Skew
Cycle to Cycle Jitter
t
measured at 1.4V, Fout=50 MHz
rising edges at VDD/2
55
%
ps
ps
ps
ps
DC
700
250
350
200
rising edges at VDD/2
rising edges at VDD/2
measured at 66.67M, outputs
loaded
PLL Lock Time
Note 3
1.0
ms
Note 3: With VDD at a steady rate and valid input at CLKIN
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
120
115
105
58
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
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Package Outline and Package Dimensions (8-pin SOIC, ±50 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Inches
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.±0 (.004)
C
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Ordering Information
Part / Order Number
2305MI-1*
Marking
2305MI-1
2305MI-1
2305MI1H
2305MI1H
2305MI1L
2305MI1L
2305I1HL
2305I1HL
2305M-1
Shipping Packaging
Tubes
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
2305MI-1T*
Tape and Reel
Tubes
2305MI-1H*
2305MI-1HT*
2305MI-1LF
2305MI-1LFT
2305MI-1HLF
2305MI-1HLFT
2305M-1*
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
2305M-1T*
2305M-1
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
2305M-1H*
2305M-1H
2305M-1H
2305M1LF
2305M1LF
2305M1HL
2305M1HL
2305M-1HT*
2305M-1LF
2305M-1LFT
2305M-1HLF
2305M-1HLFT
Tape and Reel
*NOTE: EOL for non-green parts to occur on 5/±3/±0 per PDN U-09-0±
“LF” denotes Pb (lead free) package.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied.
This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the
right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
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Revision History
Rev. Originator
Date
Description of Change
A
B
P. Griffith
P. Griffith
12/01/04 New device/datasheet; Preliminary.
12/27/04 Made corrections to IDD, IDDP, input capacitance, duty cycle and jitter specs/test
conditions. Removed reference to table 2 in output clock frequency test conditions.
Removed abslolute and cycle-to-cycle jitter specs for 15 pF load. Added duty cycle spec
for Fout=50 MHz. Release from Preliminary to Final.
C
P. Griffith
J. Sarma
1/25/05 Made corrections to test conditions of output rise time, fall-time, duty cycle and
cycle-to-cycle jitter.
D
E
2/25/05 Added LF packing info.
08/17/09 Added EOL note per PDN U-09-01.
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