FXO-PC735RFC-159.375 [IDT]
LVPECL Output Clock Oscillator, 159.375MHz Nom, ROHS COMPLIANT PACKAGE-6;
| 型号： | FXO-PC735RFC-159.375 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LVPECL Output Clock Oscillator, 159.375MHz Nom, ROHS COMPLIANT PACKAGE-6 机械 PC 石英晶振 振荡器 |
| 文件： | 总2页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
for FIBRE CHANNEL Model: FXO-PC735RFC-159.375
LVPECL 7 x 5mm 3.3V 50ppm XO Freq: 159.375MHz
Features
Low Jitter
Low Cost
Tri-State Enable / Disable Feature
Industry Standard Package
Gold over Nickel Termination Finish
V
DD
Enable / Disable
FOX
OUTPUT
XPRESSO
ASICs
GND
Electrical Characteristics
Maximum Value
(unless otherwise noted)
Parameters
Symbol
Condition
Frequency
FO
159.375 MHz
50 ppm
Frequency Stability 1
Temperature Range
TO
TSTG
Standard operating
Storage
-40°C to +85°C
-55°C to +125°C
Supply Voltage
VDD
IDD
Standard
Standard Load
Standard
3.3V ± 5%
120 mA
Input Current
Output Load
Differential
TS
50 ohms into VDD -2.0VDC
10 mS
Start-Up Time
Output Enable / Disable Time
100 nS
Moisture Sensitivity Level
Termination Finish
MSL
1
Au
Note 1 – Stability is inclusive of 25°C tolerance, operating temperature range, input voltage change, load change, aging, shock and vibration.
Output Wave Characteristics
Maximum Value
(unless otherwise noted)
1.35V ~ 1.65V
Parameters
Output LOW Voltage
Symbol
VOL
Condition
Standard Load
Output HIGH Voltage
Output Symmetry
VOH
Standard Load
2.055V ~ 2.405V
45% ~ 55%
@ 50% Vp-p Level
Output Enable (PIN # 1) Voltage
VIH
≥70% VDD
Output Disable (PIN # 1) Voltage
Cycle Rise Time
VIL
TR
TF
≤30% VDD
400 pS
400 pS
20% ~ 80% Vp-p
80% ~ 20% Vp-p
Cycle Fall Time
DWG- 100750 | Rev. 07/13/2010
DWG-
| Rev. 07/13/2010
Page 1 of 2
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE
for FIBRE CHANNEL Model: FXO-PC735RFC-159.375
LVPECL 7 x 5mm 3.3V 50ppm XO Freq: 159.375MHz
Dimensional Drawing & Pad Layout
Phase Jitter & Time Interval Error (TIE) (Typical Measurements)
Phase Jitter
(12kHz to 20MHz)
T I E
Frequency
Units
(Sigma of Jitter Distribution)
159.375 MHz
0.86
3.5
pS RMS
Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V.
TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Random & Deterministic Jitter Composition (Typical Measurements)
Total Jitter (Tj)
Random (Rj) Deterministic (Dj)
Frequency
(14 x Rj) + Dj
(pS RMS)
(pS P-P)
159.375 MHz
1.29
9.3
27.7 pS
Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Pin Functional Description
Pin #
Name
Type
Logic
Function
Enable / Disable Control of Output (0 = Disabled)
No Connection – Leave Open
E / D 1
1
2
2
NC
3
GND
Output
Output 2
Ground
Output
Output
Power
Electrical Ground for VDD
4
LVPECL Oscillator Output
5
Complementary LVPECL Output
Power Supply Source Voltage
3
6
VDD
1
NOTES:
Includes pull-up resistor to VDD to provide output when the pin (1) is No Connect. (Also see note 2)
An optional pin # 2 Enable / disable is available.
2
3
Installation should include a 0.01µF bypass capacitor placed between VDD
(Pin 6) and GND (Pin 3) to minimize power supply line noise.
DWG-
| Rev. 07/13/2010
Page 2 of 2
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE
相关型号：
FXO-PC735RFREQ
CRYSTAL OSCILLATOR, CLOCK, 0.75MHz - 1350MHz, LVPECL OUTPUT, ROHS COMPLIANT, CERAMIC PACKAGE-6
FOX
©2020 ICPDF网 联系我们和版权申明