F1451EVBK [IDT]
TX Digital VGA 700 MHz to 1100 MHz;
| 型号： | F1451EVBK |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TX Digital VGA 700 MHz to 1100 MHz |
| 文件： | 总28页 (文件大小：7174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T
TX Digital VGA
700 MHz to 1100 MHz
F1451
Datasheet
Description
Features
The F1451 is a High Gain / High Linearity 700 MHz to 1100 MHz
TX Digital Variable Gain Amplifier used in transmitter applications.
.
.
.
.
.
.
Broadband 700 MHz to 1100 MHz
32 dB max gain
3.6 dB NF @ max gain (900 MHz)
29.5 dB total gain control range, 0.5 dB step
< 2 dB overshoot between gain transitions
Maintains flat +23 dBm OP1dB for more than 13 dB gain
adjustment range
The F1451 TX DVGA provides 32 dB maximum gain with
+41.5 dBm OIP3 and 3.6 dB noise figure. Up to 29.5 dB gain
control is achieved using the combination of a digital step
attenuator (DSA) and a KLIN RF Digital Gain Amplifier. This
device uses a single 5 V supply and 185 mA of ICC.
TM
.
Maintains flat +41 dBm OIP3 for more than 15 dB gain
adjustment range
SPI interface for DSA control
Single 5 V supply voltage
ICC = 185 mA
This device is packaged in a 6 mm x 6 mm, 28-pin QFN with 50 Ω
single-ended RF input and RF output impedances for ease of
integration into the signal-path.
.
.
.
.
Competitive Advantage
Up to +105 °C TCASE operating temperature
In typical Base Stations, RF VGAs are used in the TX traffic paths
to drive the transmit power amplifier. The F1451 TX DVGA offers
very high reliability due to its construction from a monolithic silicon
die in a QFN package. The F1451 is configured to provide an
optimum balance of noise and linearity performance consisting of
a KLINTM RF amplifier, digital step attenuator (DSA) and a PA driver
amplifier. The KLINTM amplifier maintains the OIP3 and output P1dB
performance over an extended attenuation range when compared
to competitive devices.
. 50 Ω input and output impedance
.
.
.
Standby mode for power savings
Pin compatible 2100 MHz and 2700 MHz versions
6 mm x 6 mm, 28-pin QFN package
Block Diagram
Figure 1. Block Diagram
Typical Applications
K
LIN
Constant
.
.
.
.
.
Multi-mode, Multi-carrier Transmitters
WiMAX and LTE Base Stations
UMTS/WCDMA 3G Base Stations
PHS/PAS Base Stations
High LinearityTM
RF IN
RF OUT
Public Safety Infrastructure
SPI &
Decoder
3
/STBY
Digital CTL
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Pin Assignments
Figure 2. Pin Assignments for 6 mm x 6 mm x 0.9 mm QFN Package – Top View
21
20
19
18
17
16
15
1
GND
CSb
2
NC
DATA
F1451
3
NC
CLK
4
NC
RSET
Exposed Pad
(GND)
5
GND
RFOUT
GND
GND
6
RFIN
7
GND
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Description
Chip Select Input: 1.8 V or 3.3 V logic compatible.
1
2
CSb
DATA
CLK
Data Input: 1.8 V or 3.3 V logic compatible.
3
Clock Input: 1.8 V or 3.3 V logic compatible.
4 [a]
RSET
Connect 2.0 kΩ external resistor to GND to set amplifier bias.
5, 7, 15, 17,
21, 23, 27
GND
RFIN
Pins internally tied to exposed paddle. Connect to ground on PCB.
6
RF input internally matched to 50 Ω. Must use external DC block.
8, 9, 10, 11,
12, 13, 18,
19, 20, 22,
24, 25, 26
No internal connection. These pins can be left unconnected, voltage applied, or connected to ground
(recommended).
NC
Standby pin. Device will be placed in standby mode when pin 14 is set to a logic low or when pin 14 is
left floating (pulled low via internal high impedance to GND). In standby mode, SPI circuitry is still active.
With a logic high applied to pin 14 the part is set to full operation mode.
14
/STBY
16
28
RFOUT
VCC
RF output internally matched to 50 Ω. Must use external DC block.
5 V Power Supply. Connect to Vcc and use bypass capacitors as close to the pin as possible.
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple
ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple vias
are also required to achieve the noted RF performance.
— EP
a. External resistor on pin 4 used to optimize the overall device for DC current and linearity performance across the entire
frequency band.
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. Functional operation of the device at these or any other
conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Vcc to GND
VCC
VCntrl
IRSET
VRFIN
VRFOUT
Pmax_in
Pdiss
Tj
-0.5
-0.3
5.5
VCC
V
V
DATA, CSb, CLK, /STBY
RSET
+1.5
mA
V
RFIN externally applied DC voltage
RFOUT externally applied DC voltage
RF Input Power (RFIN) applied for 24 hours max. [a]
Continuous Power Dissipation
Junction Temperature
+1.4
+3.6
VCC - 0.15
VCC + 0.15
+12
V
dBm
W
1.75
150
°C
°C
°C
Storage Temperature Range
Lead Temperature (soldering, 10s)
Tst
-65
150
260
ElectroStatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
2000
(Class 2)
V
V
ElectroStatic Discharge – CDM
(JEDEC 22-C101F)
1000
(Class C3)
a. Exposure to these maximum RF levels can result in significantly higher Icc current draw due to
overdriving the amplifier stages.
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Power Supply Voltage
VCC
4.75
-40
5.25
+105
1100
1200
V
Operating Temperature Range
TCASE
Exposed Paddle
°C
High Linearity Bandwidth
Extended band for DPD
700
600
RF Frequency Range [a]
FRF
MHz
dBm
Maximum Operating Average RF
Output Power
14
ZS = ZL = 50
RFIN Port Impedance
ZRFI
Single Ended
Single Ended
50
50
RFOUT Port Impedance
ZRFO
a. Device linearity is optimized over the range from 700 MHz to 1100 MHz. Gain flatness is optimized from 600 MHz to
1200 MHz to account for systems with extended DPD bandwidth requirements.
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Electrical Characteristics - General
See Typical Application Circuit. Unless otherwise stated, specifications apply when operated as a TX VGA, VCC = +5.0 V, FRF = 806 MHz,
TCASE = +25 °C, /STBY = High, ZS = ZL = 50 , maximum gain setting. Evaluation Kit trace and connector losses are de-embedded.
Table 4. Electrical Characteristics
Parameter
Logic Input High Threshold
Logic Input Low Threshold
Symbol
VIH
Condition
JEDEC 1.8V or 3.3V logic
JEDEC 1.8V or 3.3V logic
SPI
Minimum
Typical
Maximum
Units
1.1 [a]
-0.3
-1
VCC
0.8
+1
V
V
VIL
IIH, IIL
ISTBY
ICC
Logic Current
µA
/STBY
-10
+10
215
2
DC Current
185
1
mA
mA
Standby Current
ICC_STBY
/STBY = Low
50% /STBY control to within
0.2 dB of the on state final
gain value
Standby Switching Time
TSTBY
250
ns
Gain Step
GSTEP
Least Significant Bit
Any state to state transition
FRF = 0.700 GHz
0.5
2
dB
dB
Maximum Attenuator Glitching
ATTNG
-0.09
-0.08
-0.09
-0.10
-0.10
+0.12
+0.12
+0.14
+0.15
+0.15
FRF = 0.806 GHz
0.10
Maximum Step Error (DNL)
[over voltage, temperature and
attenuation states]
ERRORSTEP FRF = 0.900 GHz
FRF = 1.000 GHz
dB
FRF = 1.100 GHz
Over attenuation range
referenced to max gain state
Maximum Absolute Error (INL)
ERRORABS
GST
1.2
dB
ns
Gain Settling Time [c]
SPI [d]
50% of CSb to 10% / 90% RF
200
Serial Clock Speed
CSb to CLK Setup Time
CLK to Data Hold Time
CSb Trigger to CLK Setup Time
FCLOCK
TLS
MHz
ns
25
5
5
5
TH
ns
TLC
ns
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. Excludes SPI write time.
d. SPI 3 wire bus (refer to serial Control Mode Timing diagram).
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Electrical Characteristics - RF
See Typical Application Circuit. Unless otherwise stated, specifications apply when operated as a TX VGA, VCC = +5.0 V, FRF = 806 MHz,
TCASE = +25 °C, /STBY = High, ZS = ZL = 50 , maximum gain setting. Evaluation Kit trace and connector losses are de-embedded
Table 5. Electrical Characteristics
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
RF Input Return Loss
RF Output Return Loss
Gain - Max Gain Setting
Gain - Min Gain Setting
Gain Flatness [c]
RLRFIN
RLRFOUT
GMAX
20
15
dB
dB
dB
dB
dB
30.6 [a]
0.0
33.6
3.0
32.1
1.5
GMIN
Max attenuation
GFLAT
FRF = 700 MHz to 1100 MHz
0 dB attenuation
0.7
3.6
10 dB attenuation
6.0
Noise Figure
NF
dB
20 dB attenuation
11.6
20.6
29.5 dB attenuation
0 dB attenuation
Pout = +7 dBm / tone
5 MHz tone separation
41.5
41.3
40.7
37.8
29.8
6 dB attenuation
Pin = -21 dBm / tone
5 MHz tone separation
10 dB attenuation
Pin = -21 dBm / tone
5 MHz tone separation
Output Third Order Intercept Point
OIP3
dBm
37
20 dB attenuation
Pin = -21 dBm / tone
5 MHz tone separation
29.5 dB attenuation
Pin = -21 dBm / tone
5 MHz tone separation
0 dB attenuation
23.5
23
0 dB attenuation,
TCASE = +105 °C
Output 1dB Compression Point
OP1dB
dBm
6 dB attenuation
23.5
21.8
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. Includes a positive slope feature over the noted RF range to compensate for typical system roll-off.
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Thermal Characteristics
Table 6. Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance
θJA
40
°C/W
Junction to Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC
4
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 1
Typical Operating Conditions (TOC)
Unless otherwise stated the typical operating graphs were measured under the following conditions:
.
.
.
.
.
.
.
.
.
.
.
.
Vcc = 5.0 V
ZL = ZS = 50 Ohms Single Ended
FRF = 806 MHz
TCASE = +25 °C
/STBY = High
5 MHz Tone Spacing
Gain setting = Maximum Gain
Output Power = +7 dBm / tone for OIP3
All temperatures are referenced to the exposed paddle
ACLR measurements used with a Basic LTE FDD Downlink 20 MHz TM1.2 Test signal
EVM measurements used with a Basic LTE FDD Downlink 20 MHz TM3.1 Test signal
Note TN1: Atten ≤ 4 dB Fixed Pout = +7.0 dBm per waveform or per tone, Atten > 4 dB Fixed Pin = -21 dBm per waveform or per tone
.
Note TN2: Atten ≤ 7 dB Fixed Pout = +10.5 dBm per waveform or per tone, Atten > 7 dB Fixed Pin = -14.5 dBm per waveform or per
tone
.
Evaluation Kit traces and connector losses are de-embedded
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Typical Performance Characteristics
Figure 3. Maximum Gain vs. Frequency over
Temp and Voltage [Attn = 0.0 dB]
Figure 4. Reverse Isolation vs. Frequency over
Temp and Voltage [Attn = 0.0 dB]
35
34
33
32
31
30
29
28
27
-30
-35
-40
-45
-50
-55
-60
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-65
-70
26
25
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.0
6.0
Frequency (GHz)
Frequency (GHz)
Figure 5. Input Return Loss vs. Frequency over
Temp and Voltage [Attn = 0.0 dB]
Figure 6. Output Return Loss vs. Frequency
over Temp and Voltage [Attn = 0.0 dB]
0
0
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-5
-10
-15
-20
-25
-30
-5
-10
-15
-20
-25
-30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Frequency (GHz)
Frequency (GHz)
Figure 7. Stability vs. Frequency over
Temperature and Voltage [Attn = 0.0 dB]
Figure 8. EvKit Insertion Loss vs. Frequency
over Temperature
10
9
8
7
6
5
4
3
2
1
0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-0.7
-40 C
-0.8
+25 C
+105 C
-0.9
Through Line has no series capacitors
-1.0
0
1
2
3
4
5
6
7
0.0
1.0
2.0
3.0
4.0
5.0
Frequency (GHz)
Frequency (GHz)
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Typical Performance Characteristics
Figure 9. Gain vs. Frequency [+25 °C, All
Figure 10. Gain vs. Attenuation over
Temperature and Voltage [806 MHz]
States]
35
30
25
20
15
10
5
35
30
25
20
15
10
5
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
0
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
Figure 11. Worse Case Attenuator Absolute
Accuracy vs. Freq [All parameters]
Figure 12. Attenuator Absolute Accuracy vs.
Atten over Temp and Voltage [806 MHz]
3.0
2.5
2.0
1.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Min
Max
1.0
0.5
0.0
-0.5
-1.0
StatisticallyBased of 29 Devices
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
For all Temperatures, Voltages,
and AttenuationStates.
Standard Deviation is included.
-1.5
-0.2
-0.4
-2.0
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
Figure 13. Worse Case Step Accuracy vs. Freq
[All parameters]
Figure 14. Step Accuracy vs. Attenuation over
Temperature and Voltage [806 MHz]
0.4
0.4
Min
0.3
0.3
Max
0.2
0.1
0.2
0.1
0.0
0.0
-0.1
-0.1
-0.2
-0.2
StatisticallyBased of 29 Devices
For all Temperatures, Voltages,
and AttenuationStates.
Standard Deviation is included.
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-0.3
-0.3
-0.4
-0.4
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
© 2016 Integrated Device Technology, Inc.
10
November 29, 2016
F1451 Datasheet
Typical Performance Characteristics
Figure 15. Input Return Loss vs. Frequency
Figure 16. Input Return Loss vs. Attenuation
over Temperature and Voltage [806 MHz]
[+25 °C, All states]
0
-5
0
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.0
2.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
Figure 17. Output Return Loss vs. Frequency
Figure 18. Output Return Loss vs. Attenuation
over Temperature and Voltage [806 MHz]
[+25 °C, All states]
0
-5
0
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
Figure 19. Reverse Isolation vs. Frequency
Figure 20. Reverse Isolation vs. Attenuation
over Temperature and Voltage [806 MHz]
[+25 °C, All states]
-30
-35
-40
-45
-50
-55
-60
-65
-70
-30
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-35
-40
-45
-50
-55
-60
-65
-70
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Typical Performance Characteristics
Figure 21. Output IP3 vs. Attn over Temp and
Voltage [700 MHz] (Test Note TN1)
Figure 22. Output IP3 vs. Attn over Temp and
Voltage [700 MHz] (Test Note TN2)
48
46
44
42
40
38
36
34
32
30
28
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
26
24
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Attenation Setting (dB)
Attenation Setting (dB)
Figure 23. Output IP3 vs. Attn over Temp and
Voltage [900 MHz] (Test Note TN1)
Figure 24. Output IP3 vs. Attn over Temp and
Voltage [900 MHz] (Test Note TN2)
48
46
44
42
40
38
36
34
32
30
28
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
26
24
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Attenation Setting (dB)
Attenation Setting (dB)
Figure 25. Output IP3 vs. Attn over Temp and
Voltage [1100 MHz] (Test Note TN1)
Figure 26. Output IP3 vs. Attn over Temp and
Voltage [1100 MHz] (Test Note TN2)
48
46
44
42
40
38
36
34
32
30
28
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
26
24
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Attenation Setting (dB)
Attenation Setting (dB)
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F1451 Datasheet
Typical Performance Characteristics
Figure 27. Output IP3 vs. Frequency over
Temperature and Voltage [Attn = 0.0 dB]
Figure 28. Output P1dB vs. Attenuation over
Temperature and Voltage [700 MHz]
48
46
44
42
40
38
36
34
32
30
28
25
20
15
10
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
26
24
5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuator Setting (dB)
Figure 29. Output P1dB vs. Frequency over
Temp and Voltage [Attn = 0.0 dB]
Figure 30. Output P1dB vs. Attenuation over
Temp and Voltage [900 MHz]
25
24
23
22
21
20
19
18
17
25
20
15
10
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
16
15
5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuator Setting (dB)
Figure 31. Output P1dB vs. Attenuation over
Temp and Voltage [1100 MHz]
25
20
15
10
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Attenuator Setting (dB)
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F1451 Datasheet
Typical Performance Characteristics
Figure 32. Gain Compression vs. Pout over
Temperature and Voltage [700 MHz]
Figure 33. Phase Compression vs. Pout over
Temperature and Voltage [700 MHz]
0.5
5
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
0
-5
0.0
-0.5
-1.0
-1.5
-2.0
-10
-15
-20
-25
12 13 14 15 16 17 18 19 20 21 22 23 24 25
12 13 14 15 16 17 18 19 20 21 22 23 24 25
Output Power (dBm)
Output Power (dBm)
Figure 34. Gain Compression vs. Pout over
Temperature and Voltage [900 MHz]
Figure 35. Phase Compression vs. Pout over
Temperature and Voltage [900 MHz]
0.5
5
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
0
-5
0.0
-0.5
-1.0
-1.5
-2.0
-10
-15
-20
-25
12 13 14 15 16 17 18 19 20 21 22 23 24 25
12 13 14 15 16 17 18 19 20 21 22 23 24 25
Output Power (dBm)
Output Power (dBm)
Figure 36. Gain Compression vs. Pout over
Temperature and Voltage [1100 MHz]
Figure 37. Phase Compression vs. Pout over
Temperature and Voltage [1100 MHz]
0.5
5
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
0
-5
0.0
-0.5
-1.0
-1.5
-2.0
-10
-15
-20
-25
12 13 14 15 16 17 18 19 20 21 22 23 24 25
12 13 14 15 16 17 18 19 20 21 22 23 24 25
Output Power (dBm)
Output Power (dBm)
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F1451 Datasheet
Typical Performance Characteristics
Figure 38. Noise Figure vs. Frequency over
Temperature and Voltage [Attn = 0.0 dB]
Figure 39. Noise Figure vs. Attenuation over
Temperature and Voltage [700 MHz]
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
25
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
20
15
10
5
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
0.5
0.0
0
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Frequency (GHz)
Attenuation Setting (dB)
Figure 40. Noise Figure vs. Attenuation over
Temperature and Voltage [900 MHz]
Figure 41. Noise Figure vs. Attenuation over
Temperature and Voltage [1100 MHz]
25
25
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
-40 C / +4.75 V
+25 C / +4.75 V
+105 C / +4.75 V
-40 C / +5.00 V
+25 C / +5.00 V
+105 C / +5.00 V
-40 C / +5.25 V
+25 C / +5.25 V
+105 C / +5.25 V
20
15
10
5
20
15
10
5
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Attenuation Setting (dB)
Attenuation Setting (dB)
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Typical Performance Characteristics
Figure 42. Switching Speed 0.0 dB to 29.5 dB
Figure 43. Switching Speed 29.5 dB to 0.0 dB
1.2
1.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
1.2
1.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
RF
Trigger
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
RF
Trigger
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Time (us)
Time (us)
Figure 44. Switching Speed Standby Mode to
Full Operation Mode
Figure 45. Switching Speed Full Operation
Mode to Standby Mode
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.2
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
RF
RF
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
Trigger
Trigger
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
Time (us)
Time (us)
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Typical Performance Characteristics
Figure 46. ACLR vs. Attenuation [700 MHz]
Figure 47. EVM vs. Attenuation [700 MHz]
-50
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
ACLR_low (Note TN1)
ACLR_high (Note TN1)
System Floor
ACLR_low (Note TN2)
ACLR_high (Note TN2)
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
EVM_rms (Note TN1)
EVM_rms (Note TN2)
system EVM
0
2
4
6
8
10
12
14
16
16
16
0
5
10
15
20
20
20
Attenuation Setting (dB)
Attenuation Setting (dB)
Figure 48. ACLR vs. Attenuation [900 MHz]
Figure 49. EVM vs. Attenuation [900 MHz]
-50
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
ACLR_low (Note TN1)
ACLR_high (Note TN1)
System Floor
ACLR_low (Note TN2)
ACLR_high (Note TN2)
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
0.10
EVM_rms (Note TN1)
EVM_rms (Note TN2)
system EVM
0.05
0.00
0
2
4
6
8
10
12
14
0
5
10
15
Attenuation Setting (dB)
Attenuation Setting (dB)
Figure 50. ACLR vs. Attenuation [1100 MHz]
Figure 51. EVM vs. Attenuation [1100 MHz]
-50
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
ACLR_low (Note TN1)
ACLR_high (Note TN1)
System Floor
ACLR_low (Note TN2)
ACLR_high (Note TN2)
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
0.10
EVM_rms (Note TN1)
EVM_rms (Note TN2)
0.05
system EVM
0.00
0
5
10
15
0
2
4
6
8
10
12
14
Attenuation Setting (dB)
Attenuation Setting (dB)
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Serial Port Interface
Serial data is formatted as a 6-bit word clocking data in MSB first.
Table 7. Attenuation Word Truth Table
Control Bit
Attenuator
Setting [a]
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
1
1
0
0
1
0
1
1
1
1
1
0
1
0
1
0
0.0 dB
0.5 dB
1.0 dB
2.0 dB
4.0 dB
8.0 dB
16.0 dB
29.5 dB
29.5 dB
29.5 dB
29.5 dB
29.5 dB
a. The attenuation setting is designed to operate from 0 dB (111111) to
29.5 dB (000100).
Figure 52. Serial Register Timing Diagram
CLK (pin 3)
DATA (pin 2)
D5
D0
Attenuation
CSb (pin 1)
Clock in MSB first
Increasing time
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Figure 53. SPI Timing Diagram
TH
TP
TLC
TS
TCH
TCL
CLK
DATA
TLS
CSb
TL
TL
Table 8. SPI Timing Diagram Values for Figure 53
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
CLK Frequency
CLK High Duration Time
CLK Low Duration Time
DATA to CLK Setup Time
CLK Period [a]
FC
TCH
TCL
TS
25
MHz
ns
20
20
5
ns
ns
TP
40
5
ns
CLK to DATA Hold Time
CSb to CLK Setup Time
CSb Trigger Pulse Width
CSb Trigger to CLK Setup Time [b]
a. (TCH + TCL) ≥ 1/FC
TH
ns
TLS
TL
5
ns
10
5
ns
TLC
ns
b. Once all desired DATA is clocked in, TLC represents the time a CSb high needs to occur before any
subsequent CLK signals.
Table 9. Standby Truth Table
/STBY (pin 14)
Condition
0 V
Vcc
Amplifier OFF with SPI powered ON
Full operation
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Application Information
The F1451 has been optimized for use in high performance RF applications from 700 MHz to 1100 MHz but in general has a much wider band
which is shown in the Typical Performance Characteristics.
Power Up Attenuation Setting
When the part is initially powered up, the default VGA setting is the 29.5 dB [000000] attenuation state.
Chip Select (CSb)
When CSb is set to logic high, the CLK input is disabled. When CSb is set to logic low, the CLK input is enabled and the DATA word can be
programmed into the shift registers. The programmed word is then latched into the F1451 on the CSb rising edge (refer to Figure 53). The
operation of the SPI bus in independent of the /STBY pin setting (see Standby Mode section below).
Standby Mode (/STBY)
The F1451 has a power down feature for power savings which is on Pin 14. For normal operation pin 14 must be set to a logic high. When a
logic low is applied to pin 14 the amplifier is placed in standby mode. The Standby mode is a high isolation state. The level of this isolation is
not specified and is dependent on the device and attenuation state. In Standby mode the SPI bus is operational and the device attenuation
setting can be programmed. Therefore, the device will present the desired attenuation when it is enabled.
Power Supplies
A common VCC power supply should be used for all power supply pins. To minimize noise and fast transients de-coupling capacitors to all
supply pins. Supply noise can degrade noise figure and fast transients can trigger ESD clamps causing them to fail. Supply voltage change or
transients should have a slew rate smaller than 1 V / 20 µs. In addition, all control pins should remain at 0 V (± 0.3 V) while the supply voltage
ramps or while it returns to zero.
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to SPI and control pins 1, 2, 3 and 14 as shown below. Note the recommended
resistor and capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity. For multiple devices driven
by a single control line, the component values will need to be adjusted accordingly so as not to load down the control line.
Figure 54. Control Pin Interface for Signal Integrity
1 k
CSb
2 pF
21
20
19
18
17
16
15
1
2
3
4
5
6
7
1 k
2 pF
1 k
2 pF
DATA
CLK
F1451
Exposed Pad
(GND)
1 k
2 pF
/STBY
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Evaluation Kit Picture
Figure 55. Top View
Figure 56. Bottom View
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Evaluation Kit / Applications Circuit
Figure 57. Electrical Schematic
VCC3
R4
C4
C3
GND1
VCC
GND4
U1
C6
C5
R6
R5
J7
R8 C7
R9
1
2
3
4
5
6
7
21
20
19
18
17
16
15
CSb
CLK
CSb
GND
NC
8
6
4
2
7
5
3
1
DATA
CLK
DATA
R10
R7
NC
GND
R1
F1451
B5
RSET
GND
RFIN
GND
NC
GND
J1
J2
C1
C2
RFIN
RFOUT
RFOUT
GND
C13
C14
C15
C16
VCC1
VCC2
VCC
R2
R3
VCC
B1
B2
B3
B4
R11 R12
R13 R14
C8
C9
J3
VCC
C10
C11
VCC
VCC
C12
R16
GND3
J4
GND2
R15
J5
J6
Not All Components are used. Please
check the Bill of Material (BOM) table.
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Table 10. Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C1, C2
2
1
1
3
1
1
4
4
1
1
1
2
1
1
47 pF ±5%, 50V, C0G Ceramic Capacitor (0402)
100 nF ±10%, 16V, X7R Ceramic Capacitor (0402)
1000 pF ±5%, 50V, C0G Ceramic Capacitor (0402)
2 pF ±0.1pF, 50V, C0G Ceramic Capacitor (0402)
10 uF ±20%, 16V, X6S Ceramic Capacitor (0603)
2.0 kΩ ±1%, 1/10W, Resistor (0402)
GRM1555C1H470J
GRM155R71C104K
GRM1555C1H102J
GRM1555C1H2R0B
GRM188C81C106M
ERJ-2RKF2001X
ERJ-2GE0R00X
ERJ-2RKF1001X
961102-6404-AR
961103-6404-AR
67997-108HLF
MURATA
MURATA
MURATA
MURATA
MURATA
PANASONIC
PANASONIC
PANASONIC
3M
C3
C4
C5, C6, C7
C12
R1
R4 - R7
0 Ω Resistor (0402)
R8 - R10, R16
1 kΩ ±1%, 1/10W, Resistor (0402)
J4
J6
CONN HEADER VERT SGL 2 X 1 POS GOLD
CONN HEADER VERT SGL 3 X 1 POS GOLD
CONN HEADER VERT DBL 4 X 2 POS GOLD
Edge Launch SMA (0.375 inch pitch ground, tab)
Edge Launch SMA (0.250 inch pitch ground, round)
VGA AMP
3M
J7
FCI
J1, J2
J3
142-0701-851
Emerson Johnson
Emerson Johnson
IDT
142-0711-821
U1
F1451NKGK
C8 - C11, C13 - C16,
R2, R3, R11 - R15, J5
DNP
1
Printed Circuit Board
F145X EVKIT REV 02
© 2016 Integrated Device Technology, Inc.
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F1451 Datasheet
Evaluation Kit Operation
Standby
Connector J6 allows the F1451 to be put into the standby mode. Connecting J6 pin 2 (the center pin) to Vcc the amplifier will be placed in
normal operating mode. To put the F1451 into standby mode for very low power consumption ground J6 pin 2 (the center pin). If J6 pin 2 (the
center pin) is left open, then the F1451 will default to the standby mode.
Figure 58. Image of J6 connector for Standby mode control
Serial Programming Pins
Connector J7 pins 1, 2, 4, 6, 8 are ground. Pin 3 is DATA, pin 5 is Clock (CLK), pin 7 is Chip Select (CSB).
Figure 59. Image of J7 connector for SPI
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Package Drawings
Figure 60. Package Outline Drawing NKG28 PSC-4606
TOP VIEW
BOTTOM VIEW
SIDE VIEW
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Recommended Land Pattern
Figure 61. Recommended Land Pattern
© 2016 Integrated Device Technology, Inc.
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November 29, 2016
F1451 Datasheet
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F1451NKGK
F1451NKGK8
F1451EVBK
F1451EVSK
6 x 6 x 0.9 mm QFN
6 x 6 x 0.9 mm QFN
1
1
Tray
-40° to +105°C
-40° to +105°C
Tape and Reel
Evaluation Board
Evaluation Board with Controller
Marking Diagram
1. Line 1, 2 and 3 are the part number.
2. Line 4 “ZB” is Assembly Stepping.
3. Line 4 “yyww = “1635” is two digit for the year and week that the part was assembled.
4. Line 4 “L” denotes Assembly Site.
IDT
F1451
NKGK
5. Line 5 “XU65013PY” is the Assembly Lot number.
ZB1635L
XU65013PY
© 2016 Integrated Device Technology, Inc.
27
November 29, 2016
F1451 Datasheet
Revision History
Revision
Revision Date
Description of Change
O
2016-November -29 Initial Release
Corporate Headquarters
Sales
Tech Support
www.IDT.com/go/support
6024 Silver Creek Valley Road
San Jose, CA 95138
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Per formance specifications and
operating parameters of the described products are determined in an independent state and are not guara nteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of
the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved
© 2016 Integrated Device Technology, Inc.
28
November 29, 2016
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