CV110JPVG8 [IDT]
Clock Generator, PDSO56;
| 型号： | CV110JPVG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO56 光电二极管 |
| 文件： | 总16页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
IDTCV110J
CLOCK FOR P4 PROCESSOR
DESCRIPTION:
FEATURES:
IDTCV110Jisa56pinclockdevice.TheCPUoutputbufferisdesignedto
support up to 400MHz processor. This chip has three PLLs inside for CPU/
SRC/PCI,SATA,and48MHz/DOT96IOclocks. OnededicatedPLLforSerial
ATA clock provides high accuracy frequency. This device also implements
Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential
outputs,whichcanprovidemorerobustsystemperformance.
• One high precision PLL for CPU, SSC, and N programming
• One high precision PLL for SRC/PCI/SATA, SSC, and N
programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, down spread 0.5%
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
StaticPLLfrequencydivideerrorcanbeaslowas36ppm,worsecase114
ppm,providinghighaccuracyoutputclock. EachCPU/SRC/PCI,SATAclock
has its own Spread Spectrum selection, which allows for isolated changes
insteadofaffecting otherclockgroups.
• Allows for CPU frequency to change to a higher frequency for
maximum system computing power
• Available in SSOP package
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 6*0.7V current –mode differential SRC CLK pair, one dedicated
forSATA
• One CPU_ITP/SRC selectable CLK pair
• 9*PCI, 3 free running, 33.3MHz
• 1*96MHz,1*48MHz
KEYSPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm
• 1*REF
FUNCTIONALBLOCKDIAGRAM
PLL1
SSC
N Programmable
CPU CLK
CPU[1:0]
Output Buffers
Stop Logic
X1
CPU_ITP/SRC7
XTAL
Osc Amp
IREF
REF
X2
ITP_EN
SDATA
SM Bus
Controller
SCLK
SRC CLK
Output Buffer
Stop Logic
SRC[6:1]
PLL2
SSC
N Programmable
PCI[5:0], PCIF[2:0]
IREF
VTT_PWRGD#/PD
Control
Logic
48MHz
DOT96
FSA.B.C
48MHz/96MHz
Output BUffer
PLL3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-6507/12
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
VDD_PCI
VSS_PCI
PCI3
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2
VDDIN
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
2
PCI1
TSTG
Storage Temperature
–65
0
+150
+70
+115
°C
°C
°C
V
3
PCI0
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
PCI4
4
FSC/TEST_SEL
REF
PCI5
5
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
6
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCIF2
VDD48
SCL
USB48
VSS_CPU
CPU0
VSS48
DOT96
CPU0#
DOT96#
FSB/TEST_MODE
VTT_PWRGD#/PD
FSA
VDD_CPU
CPU1
CPU1#
IREF
SRC1
VSSA
SRC1#
VDDA
VDD_SRC
SRC2
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
VDD_SRC
SRC2#
SRC3
SRC6
SRC3#
SRC6#
SRC5
SRC4
SRC4#
SRC5#
VSS_SRC
VDD_SRC
SSOP
TOP VIEW
FREQUENCYSELECTIONTABLE
FSC, B, A
101
CPU
100
SRC[7:1]
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
DOT
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
100
48
96
011
166
100
48
96
010
200
100
48
96
000
266
100
48
96
100
333
100
48
96
110
400
100
48
96
111
Reserve
100
48
96
2
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin Number
Name
VDD_PCI
VSS_PCI
PCI3
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/O
Description
1
2
3.3V
GND
3
PCI clock
PCI clock
PCI clock
GND
4
PCI4
5
PCI5
6
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
7
3.3V
8
PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
9
OUT
OUT
PWR
OUT
GND
OUT
OUT
IN
PCI clock, free running
10
11
12
13
14
15
16
17
PCIF2
PCI clock, free running
VDD48
3.3V
USB48
48MHz clock
VSS48
GND
DOT96
96MHz0.7currentmodedifferentialclockoutput
96MHz0.7currentmodedifferentialclockoutput
CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0.
DOT96#
FSB/TEST_MODE
VTT_PWRGD#/PD
IN
Level-sensitivestrobeusedtolatchtheFSA, FSB, FSC/TEST_SEL, andPCIF0/ITP_ENinputs. After
VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
FSA
SRC1
IN
CPUfrequencyselection
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
GND
OUT
OUT
OUT
PWR
Differentialserialreferenceclock
SRC1#
Differentialserialreferenceclock
VDD_SRC
SRC2
3.3V
Differentialserialreferenceclock
SRC2#
Differentialserialreferenceclock
SRC3
Differentialserialreferenceclock
SRC3#
Differentialserialreferenceclock
SRC4
Differentialserialreferenceclock
SRC4#
Differentialserialreferenceclock
VDD_SRC
VSS_SRC
SRC5#
3.3V
GND
Differentialserialreferenceclock
SRC5
Differentialserialreferenceclock
SRC6#
Differentialserialreferenceclock
SRC6
Differentialserialreferenceclock
VDD_SRC
CPU2_ITP#/SRC7#
CPU2_ITP/SRC7
VDDA
3.3V
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
3.3V
VSSA
GND
IREF
Referencecurrentfordifferentialoutputbuffer
Host0.7currentmodedifferentialclockoutput
Host0.7currentmodedifferentialclockoutput
3.3V
CPU1#
CPU1
VDD_CPU
3
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONT.)
Pin Number
Name
CPU0#
CPU0
Type
OUT
OUT
GND
IN
Description
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Host0.7currentmodedifferentialclockoutput
Host0.7currentmodedifferentialclockoutput
VSS_CPU
SCL
GND
SM Bus clock
SDA
I/O
SM Bus data
VDD_REF
XTAL_OUT
XTAL_IN
VSS_REF
REF
PWR
OUT
IN
3.3V
XTALoutput
XTALinput
GND
OUT
IN
GND
14.318MHzreferenceclockoutput
FSC/TEST_SEL
PCI0
CPUfrequencyselection. Selectstestmodeifpulledtoabove2VwhenVTT_PWRGD#isassertedLOW.
OUT
OUT
OUT
PCI clock
PCI clock
PCI clock
PCI1
PCI2
INDEXBLOCKWRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
11-18
19
29-36
37
20
21-28
29
D3h
38-45
46
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Byte count, N (block read back of N
bytes), power on is 8
38
39-46
47
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Setting bit[11:18] = starting address. After reading back the first data byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
4
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
CONTROLREGISTERS
N PROGRAMMING PROCEDURE
•
•
Use Index byte write.
For N programming, the user only needs to access Byte17, Byte 25, and Byte8.
1.
2.
3.
Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17.
Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f.
Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly.
•
•
Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled
It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much
thesystemcansustainforeachsteppingchange;theestimateisabout5. IftheNchangestoomuchinonestep, thesystemwilllikelyhang.
Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming.
•
MostoftheBytes,fromByte8-Byte31,areusedtoadjustoutputwaveformsandSSCmodulationprofiles.Thepoweronsettingwillbechangedaccording
toeachpoweronfrequencyselection.Toavoidmistakes,don’twriteonthosebyte(becarefulaboutBlockWrite). ItissuggestedtousetheIndexByte
writetoaccessbytes.
SSCMAGNITUDECONTROL, SMC
FREQUENCYSELECTIONTABLE
SMC[2:0]
FS_C, B, A
101
CPU
100
000
001
010
011
100
101
110
111
-0.25
-0.5
001
133
011
166
-0.75
-1
010
200
±0.125
±0.25
±0.375
±0.5
000
266
100
333
110
400
111
RESERVE
RESOLUTION
CPU (MHz)
100
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N =
150
200
125
150
200
125
150
133
166
200
266
333
400
5
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
Reserved
SRC1, SRC1#
SRC2, SRC2#
SRC3, SRC3#
SRC4, SRC4#
SRC5, SRC5#
SRC6, SRC6#
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
CPU2, CPU2#/
SRC7, SRC7#
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
CPU[2:0], SRC[7:1],
PCI[5:0], PCIF[2:0]
SpreadSpectrummodeenable
Spreadoff
Spreadon
RW
0
1
2
3
4
5
6
7
CPU0, CPU0#
CPU1, CPU1#
Reserve
OutputEnable
OutputEnable
Tristate
Tristate
Enable
Enable
RW
RW
1
1
0
1
1
1
1
REF
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
RW
RW
RW
RW
USB48
DOT96
PCIF0
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
PCIF1
PCIF2
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
Reserved
1
2
3
4
5
6
7
SRC1
SRC2
SRC3
SRC4
SRC5
SRC6
SRC7
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Allowcontrolledbysoftware
Freerunning,not
Stoppedwith
PCI_STOP
PCI_STOP, byte 6, bit 3, assertion
affected by PCI_STOP
6
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
Reserved
Reserved
Reserved
PCIF0
RW
RW
RW
RW
RW
RW
RW
1
1
1
0
0
0
0
0
PCIF1
Allowcontrolledbysoftware
PCI_STOP, byte 6, bit 3, assertion
DOT96 power down drive mode
Notstopped
by PCI_STOP
Stoppedwith
PCI_STOP
Tristate
PCIF2
DOT96
Driven in power down
Reserved
BYTE 5
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPU0, CPU0#
CPU1, CPU1#
CPU2, CPU2#
SRC[7:1], SRC[7:1]#
Reserved
CPU0 PWRDWN drive mode
CPU1 PWRDWN drive mode
CPU2 PWRDWN drive mode
SRC PWRDWN drive mode
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Reserved
Reserved
SRC[7:1], SRC[7:1]#
SRC PCI_STOP drive mode
Driven in PCI_STOP
Tristatewhenstopped
RW
BYTE 6
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
CPU[2:0]
CPU[2:0]
CPU[2:0]
PCI, SRC
FSA latched value on power up
FSB latched value on power up
FSC latched value on power up
R
R
R
SoftwarePCI_STOPcontrolfor
PCI and SRC CLK
Stop all PCI, PCIF, and
SRC which can be stopped
by PCI_STOP#
SoftwareSTOP
Disabled
RW
1
4
5
6
REF
REFdrivestrength
1x drive
2x drive
1
0
0
Reserved
Testclockmodeentrycontrol
Normaloperation
Testmode,controlled
RW
by Byte 6, Bit 7
REF/N
7
CPU, SRC, PCI
PCIF, REF,
Only valid when Byte 6, Bit 7
is HIGH
Hi-Z
0
USB48, DOT96
7
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 7
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
VendorID
VendorID
VendorID
VendorID
Revision ID
Revision ID
Revision ID
Revision ID
R
R
R
R
R
R
R
R
1
0
1
0
0
0
0
0
BYTE 8
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
One cycle read
Disable
Disable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
1
NProgrammingenable
Reserved
USB48
USB48Strengthcontrol
USB PLL power down
SRC PLL power down
CPU PLL power down
1x
2x
Normal
Normal
Normal
Disable
Power down
Power down
Power down
Enable
SRC, PLL2, SSC enable Only valid when Byte1 bit0 is 1
BYTE 9
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC SMC0
SRC SMC1
SRC SMC2
Reserved
SRC/PCI SSC control
see SMC table
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
1
0
0
CPU SMC0
CPU SMC1
CPU SMC2
CPU PLL SSC control
see SMC table
Must be 0
Must be 0
0
(Must be 0)
BYTE17
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPU_N0, LSB
CPU_N1
CPU CLK = N* Resolution
seeResolutiontable
RW
RW
RW
RW
RW
RW
RW
RW
CPU_N2
CPU_N3
CPU_N4
CPU_N5
CPU_N6
CPU_N7, MSB
8
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
BYTE25
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC_N0, LSB
SRC_N1
SRC f = N*SRC Resolution
Resolution=0.666667
100MHz N= 150
RW
RW
RW
RW
RW
RW
RW
RW
SRC_N2
SRC_N3
SRC_N4
SRC_N5
SRC_N6
SRC_N7, MSB
BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
9
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
Min.
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
2
VSS - 0.3
0.7
VSS - 0.3
–5
VDD + 0.3
VIL
Input LOW Voltage
—
0.8
V
VIH_FS
VIL_FS
IIL
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input LeakageCurrent
For FSA.B.C test_mode
For FSA.B.C test_mode
0< VIN < VDD, no internal pull-up or pull-down
Full active, CL = full load
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
—
VDD + 0.3
V
—
0.35
+5
400
70
12
—
7
V
—
mA
mA
mA
IDD3.3OP
IDD3.3PD
Operating Supply Current
Powerdown Current
—
—
—
—
—
—
FI
Input Frequency(1)
Pin Inductance(2)
—
14.31818
—
MHz
nH
LPIN
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Output pin capacitance
X1 and X2 pins
—
—
6
pF
—
—
5
Clock Stabilization(2,3)
Modulation Frequency(2)
TDRIVE_PD(2)
From VDD power-up or de-assertion of PD to first clock
Triangular modulation
—
—
1.8
33
300
5
ms
KHz
us
30
—
CPU output enable after PD de-assertion
Fall time of PD
—
—
TFALL_PD(2)
—
—
ns
TRISE_PD(3)
Rise time of PD
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
10
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
Max.
—
Unit
Ω
Current Source Output Impedance(2) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
Voltage HIGH(2)
Voltage LOW(2)
IOH = -1mA
IOL = 1mA
—
—
V
—
—
0.4
V
VHIGH
VLOW
VOVS
Statistical measurement on single-ended signal using
oscilloscope math function
660
–150
—
—
850
150
1150
—
mV
—
Max Voltage(2)
Measurement on single-ended signal using absolute value
—
mV
VUDS
Min Voltage(2)
–300
250
—
—
VCROSS(ABS) Crossing Voltage (abs)(2)
—
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Long Accuracy(2,3)
Variation of crossing over all edges
—
See TPERIOD Min. - Max. values
400MHz nominal/spread
–300
—
—
—
—
300
2.4993
2.9991
3.7489
2.5008
3.0009
3.7511
333.33MHz nominal/spread
266.66MHz nominal/spread
TPERIOD
Average Period(3)
200MHz nominal/spread
4.9985
—
5.0015
ns
166.66MHz nominal/spread
133.33MHz nominal/spread
100MHz nominal/spread
5.9982
7.4978
9.997
—
—
—
6.0018
7.5023
10.003
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
—
—
—
200MHz nominal/spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
166.66MHz nominal/spread
ns
133.33MHz nominal/spread
100MHz nominal/spread
7.4128
9.912
—
—
—
—
96MHz nominal
10.1635
175
175
—
—
—
—
—
—
—
—
—
—
700
700
125
125
55
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
ps
ps
ps
ps
%
Fall Time(2)
d-tR
Rise Time Variation(2)
Fall Time Variation(2)
Duty Cycle(2)
d-tF
—
dT3
Measurement from differential waveform
VT = 50%
45
tSK3
Skew(2)
—
100
85
ps
ps
tJCYC-CYC
NOTES:
Jitter, Cycle to Cycle(2)
Measurement from differential waveform
—
1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
11
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
30.009
30.1598
—
Unit
ppm
ns
ppm
LongAccuracy(1,2)
ClockPeriod(2)
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
Duty Cycle(1)
Skew(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
0.5
0.5
45
2
2
ns
dT1
55
%
tSK1
VT = 1.5V
—
500
250
ps
tJCYC-CYC
Jitter(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
Min.
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
300
20.834
—
Unit
ppm
ns
ppm
LongAccuracy(1,2)
ClockPeriod(2)
—
20.8257
2.4
—
TPERIOD
VOH
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
2
V/ns
V/ns
ns
Fallingedgerate
1
2
tR1
tF1
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
1
2
1
2
ns
dT1
Duty Cycle(1)
45
55
%
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
12
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
300
69.855
—
Unit
ppm
ns
ppm
LongAccuracy(1)
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
Clock Period
69.827
2.4
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current(1)
OutputLOWCurrent(1)
RiseTime(1)
V
VOL
IOL = 1mA
0.4
-33
38
V
IOH
VOH at Min. = 1V, VOH at Max. = 3.135V
VOL at Min. = 1.95V, VOL at Max. = 0.4V
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VT = 1.5V
-33
30
mA
mA
ns
IOL
tR1
1
2
tF1
FallTime(1)
1
2
ns
tSK1
Skew(1)
—
500
55
ps
dT1
Duty Cycle(1)
VT = 1.5V
45
%
tJCYC-CYC
Jitter(1)
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
PCISTOPFUNCTIONALITY
If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit.
PCI_STOP
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
DOT96
DOT96#
REF
(Byte 6 bit 3)
1
0
Normal
Normal
Normal
Normal
Normal
Normal
Low
33MHz
Low
48MHz
48MHz
Normal
Normal
Normal
Normal
14.318MHz
14.318MHz
IREF * 6 or float
13
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PD, POWER DOWN
PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhighallclockswillbedrivenlowbefore
turningofftheVCO.InPDde-assertionallclockswillstartwithoutglitches.
PD
0
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
DOT96#
Normal
Float
REF
14.318MHz
Low
1
IREF * 2 or float
IREF * 2 or float
IREF * 2 or float
PDASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
14
IDTCV110J
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PDDE-ASSERTION
Thetimefromthede-assertionofPDoruntilpowersupplyrampstogetstableclockswillbelessthan1.8ms.IfthedrivemodecontrolbitforPDtristateis
programmedto‘1’thestoppeddifferentialpairmustfirstbedrivenhightoaminimumof200mVinlessthan300µsofPDdeassertion.
tSTABLE <1.8mS
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PD
<300µS, <200mV
15
IDTCV110J
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDTCV XXX
Device Type
XX
X
Package
Grade
Commercial Temperature Range
Blank
(0°C to +70°C)
PV
PVG
Small Shrink Outline Package
SSOP - Green
Programmable FlexPC Clock for P4 Processor
110J
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800-345-7015 or 408-727-6116
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logichelp@idt.com
(408) 654-6459
16
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