AV9170-04CN8-LF [IDT]
Clock Generator, 100MHz, CMOS, PDIP8, 0.300 INCH, PLASTIC, DIP-8;
| 型号： | AV9170-04CN8-LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 100MHz, CMOS, PDIP8, 0.300 INCH, PLASTIC, DIP-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总11页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AV9170
Integrated
Circuit
Systems, Inc.
AV9170-05 is only available through America II distributor
Clock Synchronizer and Multiplier
General Description
Features
The AV9170 generates an output clock ꢀhich is
synchronized to a given continuous input clock ꢀith zero
delay ( 1ns at 5V VDD). Using ICS’s proprietary phase-
locked loop (PLL) ana-log CMOS technology, the AV9170
is useful for regenerating clocks in high speed systems
ꢀhere skeꢀ is a major concern. By the use of the tꢀo
select pins, multiples or divisions of the input clock can
be generated ꢀith zero delay (see Tables 2 and 3). The
standard versions produce tꢀo outputs, ꢀhere CLK2 is
alꢀays a divide by tꢀo version of CLK1.
•
•
•
On-chip Phase-Locked Loop for clocks
synchronization
Synchronizes frequencies up to 107MHz
(output) @ 5.0V
1ns skeꢀ (maꢁ) betꢀeen input ꢂ output clocks @
5.0V
•
•
Can recover poor duty cycle clocks
CLK1 to CLK2 skeꢀ controlled to ꢀithin 1ns @
5.0V
•
•
•
•
•
3.0 - 5.5V supply range
The AV9170 is also useful to recover poor duty cycle
clocks. A 50 MHz signal ꢀith a 20/80% duty cycle, for
eꢁample, can be regenerated to the 48/52% typical of the
part.
Loꢀ poꢀer CMOS technology
Small 8-pin DIP or SOIC package
On chip loop filter
AV9170-01, -04 for output clocks 20-107 MHz @
5.0V, 20 - 66.7 MHz @ 3.3V
AV9170-02, -05 for output clocks 5-26.75 MHz @
5.0V, 5 - 16.7 MHz @ 3.3V
The AV9170 alloꢀs the user to control the PLL feedback,
making it possible, ꢀith an additional 74F240 octal buffer
(or other such device that offers controlled skeꢀ outputs),
to synchronize up to 8 output clocks ꢀith zero delay
compared to the input (see Figure 1). Application notes for
the AV9170 are available. Please consult ICS.
•
Block Diagram
0237G—07/18/05
AV9170
AV9170-05 is only available through America II distributor
Pin Configuration
8-Pin DIP or SOIC
Pin Descriptions
PIN
NUMBER
PIN NAME
TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
FBIN
IN
Input
Input
—
Input
Input
Output
—
FEEDBACK INPUT
INPUT for reference clock
GROUND
FREQUENCY SELECT 0
FREQUENCY SELECT 1
CLOCK output 1 (See Tables 1, 2, 3, 4, 5 for values)
Poꢀer Supply
GND
FS0
FS1
CLK1
VDD
CLK
Output
CLOCK output 2 (See Tables 1, 2, 3, 4, 5 for values)
0237G—07/18/05
2
AV9170
AV9170-05 is only available through America II distributor
Using the AV9170
The AV9170 has the folloꢀing characteristics:
Eliminate High Speed
Clock Routing Problems
The AV9170 makes it possible to route loꢀer speed
clocks over long distances on the PC board and to place
an AV9170 neꢁt to the device requiring a higher speed
clock.The multiplied output can then be used to produce
a phase locked, higher speed output clock.
1. Rising edges at IN and FBIN are lined up. Falling
edges are not synchronized.
2. The relationship betꢀeen the frequencies at FBIN
and IN ꢀith CLK1 feedback is shoꢀn in Table 1
beloꢀ.
Compensate for Propagation Delays
Including an AV9170 in a timing loop alloꢀs the use of
PALs, gate arrays, etc., ꢀith loose timing specifications.
The AV9170 compensates for the delay through the PAL
and synchronizes the output to the input reference clock.
Functionality (Table 1:)
FS1
FS0
fFBIN (-01, -02) fFBIN (-04, -05)
2 • fIN
4 • fIN
fIN
3 • fIN
5 • fIN
6 • fIN
10 • fIN
0
0
1
1
0
1
0
1
Operating Frequency Range
The AV9170 is offered in versions optimized for operation
in tꢀo frequency ranges.The -01 and -04 cover high
frequencies, 20 to 100 MHz.*The -02 and -05 operate
from 5 to 25 MHz.* The AV9170 can be supplied ꢀith
custom multiplication factors and operating ranges.
Consult ICS for details.
8 • fIN
3. The frequency of CLK2 is half the CLK1 frequency.
4. The CLK1 frequency ranges are:
VDD=5V
VDD=3.3V
< 66.7
3.3V VDD Operation
AV9170-01, -04 20 < fCLK1
AV9170-02, -05 5 < fCLK1
<
107MHz*
26.75MHz*
The AV9170 does operate at both 5.0V and 3.3V system
conditions. Please note the Electrical Characteristic
specifica-tions at 3.3V include a limited output frequency
(66.6 MHz maꢁ.) and a ꢀider skeꢀ of FBIN to CLK1. For
3.3V 5% (3.15V min.), this skeꢀ is -5.0 to 0 ns. At
3.3V 10% (3.0V min.), the skeꢀ is ꢀidened to -8ns to
0 ns and should be accounted for in system design.
<
< 16.7
The AV9170 ꢀill only operate correctly ꢀithin these
frequency ranges.
Figure 1:
Application of
*At 3.3V, the maꢁimum CLK1 frequency is 66.7 MHz for -
01, -04 and 16.7 MHz for -02, -05.
AV9170 for Multiple Outputs
0237G—07/18/05
3
AV9170
AV9170-05 is only available through America II distributor
Using CLK2 Feedback
Using CLK1 Feedback
Connecting CLK2 to FBIN as shoꢀn in Figure 2 ꢀill cause With CLK1 connected to FBIN as shoꢀn in Figure 3, the
all of the rising edges to be aligned (Figure 4).
input and CLK1 output ꢀill be aligned on the rising edge,
but CLK2 can be either rising or falling (Figure 5). Consult
ICS if the CLK1 frequency is desired to be higher than 107
MHz.
Figure 2:
Figure 3:
For CLK2 frequencies 10 - 53.5 MHz* (-01)
For CLK2 frequencies 2.5 - 13.37 MHz (-02)
For CLK1 frequencies 20 - 107 MHz† (-01)
For CLK1 frequencies 5 - 26.75 MHz (-02)
*Maximum33.3MHz @3.3V(-01),8.33MHz @ 3.3V(-02)
†Maximum66.7MHz @ 3.3V(-01),16.7MHz @ 3.3V(-02)
Table 2:
Table 3:
FunctionalityTable for AV9170-01, -
02 with CLK2 Feedback
FunctionalityTable for AV9170-01, -
02 with CLK1 Feedback
FS1
FS0
CLK1
INꢁ4
CLK2
INꢁ2
INꢁ4
IN
FS1
FS0
CLK1
INꢁ2
INꢁ4
IN
CLK2
IN
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
INꢁ8
INꢁ2
IN÷2
INꢁ4
INꢁ2
INꢁ16
INꢁ8
INꢁ8
Figure 4:
Input and Output ClockWaveforms
with CLK2 Connected to FBIN
Figure 5:
Input and Output ClockWaveforms
with CLK1 Connected to FBIN
0237G—07/18/05
4
AV9170
AV9170-05 is only available through America II distributor
Using CLK1 Feedback
Using CLK2 Feedback
Connecting CLK2 to FBIN as shoꢀn in Figure 6 ꢀill cause With CLK1 connected to FBIN as shoꢀn in Figure 7, the
all of the rising edges to be aligned (Figure 8).
input and CLK1 output ꢀill be aligned on the rising edge,
but CLK2 can be either rising or falling (Figure 9).
Figure 6:
Figure 7:
For CLK2 frequencies 10 - 53 MHz* (-04)
For CLK2 frequencies 2.5 - 13.37 MHz (-05)
For CLK1 frequencies 20 - 107 MHz† (-04)
For CLK1 frequencies 5 - 26.75 MHz (-05)
*Maximum33.3MHz @3.3V(-04),8.33MHz @3.3V(-05)
†Maximum66.7MHz @ 3.3V(-04),16.7MHz @ 3.3V(-05)
Table 4:
Table 5:
FunctionalityTable for AV9170-04, -
05 with CLK2 Feedback
FunctionalityTable for AV9170-04, -
05 with CLK1 Feedback
FS1
FS0
CLK1
INꢁ6
CLK2
INꢁ3
FS1
FS0
CLK1
INꢁ3
CLK2
INꢁ1.5
INꢁ2.5
INꢁ3
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
INꢁ10
INꢁ12
INꢁ20
INꢁ5
INꢁ5
INꢁ6
INꢁ6
INꢁ10
INꢁ10
INꢁ5
Figure 8:
Input and Output ClockWaveforms
with CLK2 Connected to FBIN
Figure 9:
Input and Output ClockWaveforms
with CLK1 Connected to FBIN
0237G—07/18/05
5
AV9170
AV9170-05 is only available through America II distributor
Absolute Maximum Ratings
VDD (referenced to GND) . . . . . . . . . . . . 7.0V
Operating Temperature under Bias . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Voltage on I/O pins referenced to GND . GND –0.5V to VDD +0.5V
Poꢀer Dissipation . . . . . . . . . . . . . . . . . . 0.5 ꢀatts
Stresses above those listed under Absolute Maꢁimum Ratings above may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Eꢁposure to absolute maꢁimum rating conditions for
eꢁtended periods may affect product reliability.
Electrical Characteristics at 5V
VDD = +5V 5%, TA = 0°C to 70°C, unless otherꢀise stated
DC / CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Loꢀ Voltage
Input High Voltage
Input Loꢀ Current
Input High Current
Output Loꢀ Voltage
VIL
VIH
IIL
IIH
*VOL
VDD = 5V
VDD = 5V
VIN = 0V
VIN = VDD
IOL = 8mA
—
2.0
–1.5
—
—
—
–5
—
—
0.8
—
—
5
V
V
µA
µA
V
—
0.4
IOH = -1mA,
VDD = 5.0V
Output High Voltage
*VOH1
VDD -.4V
—
—
V
IOH = -4mA,
VDD = 5.0V
IOH = -8mA,
Unloaded, 100 MHZ
(-01, -04)
Output High Voltage
Output High Voltage
Supply Current
*VOH2
*VOH3
IDD1
VDD -.8V
—
—
30
—
—
50
V
V
2.4
—
mA
Unloaded, 25 MHZ
(-02, -05)
Supply Current
IDD2
—
13
20
mA
*Parameter guaranteed by design and characterization.Not 100% tested in production.
Notes:
1. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application.
2. All AC Specifications are measured ꢀith a 50Ω transmission line, load terminated ꢀith 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skeꢀ measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal.
0237G—07/18/05
6
AV9170
AV9170-05 is only available through America II distributor
Electrical Characteristics at 5V
VDD = +5V 5%, TA = 0°C to 70°C, unless otherꢀise stated
A/C CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Clock Rise Time
Input Clock Fall Time
ICLKr*
ICLKf*
tr1*
tr2*
tf1*
—
—
—
—
—
—
40
45
—
—
—
0.6
1.2
0.4
10
10
2
3
2
ns
ns
ns
ns
ns
ns
%
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Output Duty Cycle, AV9170-01
Output Duty Cycle, AV9170-02
Jitter, 1 sigma
15pF load.
15pF load.
15pF load.
15pF load.
15pF load. Note 2, 3
15pF load. Note 2, 3
tf2*
0.9
2
dt1*
dt2*
T1s*
48/52
49/51
125
60
55
300
%
ps
For CLK1 > 10 MHz
(-01, -04)
Jitter, absolute
Jitter, absolute
Tabs1*
Tabs2*
–500
—
—
—
500
2
ps
%
For CLK1 > 2.5 MHz
(-02, -05)
For CLK1 < 10 MHz
(-01, -04)
For CLK1 < 2.5 MHz
(-02, -05)
Input Frequency
Input Frequency
Output Frequency CLK1
Output Frequency CLK1
fi1
fi2
fo1
fo2
Note 1, AV9170-01, -04
AV9170-02, -05
AV9170-01, -04
8
2
20
5
—
—
—
—
107
26.75
107
MHz
MHz
MHz
MHz
AV9170-02, -05
26.75
Note 2, 4; 15pF load
FBIN to IN skeꢀ
Tskeꢀ1*
Tskeꢀ2*
–1
–0.3
1
ns
Input rise time < 5ns
Note 2, 4; 15pF load
Input rise time < 10ns
Tskeꢀ3* Note 2, 4
FBIN to IN skeꢀ
–2
–1
–0.3
0.4
2
1
ns
ns
CLK1 to CLK2 skeꢀ
*Parameter guaranteed by design and characterization.Not 100% tested in production.
Notes:
1. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application.
2. All AC Specifications are measured ꢀith a 50Ω transmission line, load terminated ꢀith 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skeꢀ measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal.
0237G—07/18/05
7
AV9170
AV9170-05 is only available through America II distributor
Electrical Characteristics at 3.3V
VDD = +3.3V 5%, TA = 0°C to 70°C, unless otherꢀise stated
DC / CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Loꢀ Voltage
Input High Voltage
Input Loꢀ Current
Input High Current
Output Loꢀ Voltage
VIL
VIH
IIL
IIH
*VOL
VDD = 3.3V
VDD = 3.3V
VIN = 0V
VIN = VDD
IOL = 6mA
—
0.7 VDD
–7
—
—
–4
—
—
0.2 VDD
V
V
µA
µA
V
—
—
5
—
—
0.4
IOH = -1mA,
VDD = 3.3V
Output High Voltage
*VOH1
VDD -.4V
—
—
V
IOH = -3mA,
VDD = 3.3V
IOH = -6mA,
Unloaded, 66.7 MHZ
(-01, -04)
Output High Voltage
Output High Voltage
Supply Current
*VOH2
*VOH3
IDD1
VDD -.8V
—
—
17
—
—
30
V
V
2.4
—
mA
Unloaded, 16.7 MHZ
(-02, -05)
Supply Current
IDD2
—
7
15
mA
*Parameter guaranteed by design and characterization.Not 100% tested in production.
Notes:
1. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application.
2. All AC Specifications are measured ꢀith a 50Ω transmission line, load terminated ꢀith 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skeꢀ measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal.
0237G—07/18/05
8
AV9170
AV9170-05 is only available through America II distributor
Electrical Characteristics at 3.3V
VDD = +3.3V 5%, TA = 0°C to 70°C, unless otherꢀise stated
A/C CHARACTERISTICS
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Clock Rise Time
Input Clock Fall Time
ICLKr*
ICLKf*
tr1*
tr2*
tf1*
—
—
—
—
—
—
40
45
—
—
—
10
10
2
4
2
ns
ns
ns
ns
ns
ns
%
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Output Duty Cycle, AV9170-01, -04
Output Duty Cycle, AV9170-02, -05
Jitter, 1 sigma
15pF load.
15pF load.
15pF load.
15pF load.
15pF load. Note 2, 3
15pF load. Note 2, 3
1.1
1.8
0.8
1.2
52
tf2*
3
dt1*
dt2*
T1s*
60
55
300
51
150
%
ps
For CLK1 > 10 MHz
(-01, -04)
Jitter, absolute
Jitter, absolute
Tabs1*
Tabs2*
–500
–2
—
—
500
2
ps
%
For CLK1 > 2.5 MHz
(-02, -05)
For CLK1 < 10 MHz
(-01, -04)
For CLK1 < 2.5 MHz
(-02, -05)
Input Frequency
Input Frequency
Output Frequency CLK1
Output Frequency CLK1
fi1
fi2
fo1
fo2
AV9170-01, -04
AV9170-02, -05
AV9170-01, -04
AV9170-02, -05
7
2
20
5
—
—
—
—
66.7
16.7
66.7
16.7
MHz
MHz
MHz
MHz
Note 2, 4; 15pF load
FBIN to IN skeꢀ
Tskeꢀ1*
Tskeꢀ2*
–8.0
–2.0
0
ns
3.0 £ VDD £ 3.7
Note 2, 4; 15pF load
3.0 £ VDD £ 3.7
Tskeꢀ3* Note 2, 4; 15pF load
FBIN to IN skeꢀ
–5.0
–2.0
–2.0
–0.9
0
0
ns
ns
CLK1 to CLK2 skeꢀ
*Parameter guaranteed by design and characterization.Not 100% tested in production.
Notes:
1. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application.
2. All AC Specifications are measured ꢀith a 50Ω transmission line, load terminated ꢀith 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skeꢀ measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal.
0237G—07/18/05
9
AV9170
AV9170-05 is only available through America II distributor
General Layout Precautions:
1) Use a ground plane on the top
layer of the PCB in all areas not
used by traces.
2) Make all poꢀer traces and vias
as ꢀide as possible to loꢀer
inductance.
Notes:
1) All clock outputs should have
series terminating resistor. Not
shoꢀn in all places to improve
readibility of diagram.
Connections toVDD:
0237G—07/18/05
10
AV9170
AV9170-05 is only available through America II distributor
8-Pin DIP PACKAGE
8-Pin SOIC PACKAGE
Ordering Information
AV9170-xxCN08 (8 Lead Plastic DIP [300 mils])
AV9170-xxCS08 (8 Lead SOIC [150 mils])
Eꢁample:
ICS XXXX - PPP M X#W
Lead Count & Package Width
Lead Count = 1, 2 or 3 digits
W = 0.3" SOIC or 0.6" DIP; None = Standard Width
Package Type
N = DIP (Plastic)
S = SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS = Standard Device; AV = ICS (West Coast)
For the SOIC package, the AV9170-01 is marked AV70-1 and the AV9170-02 is marked AV70-2.
0237G—07/18/05
11
相关型号：
AV9170-05CN08LF
Clock Generator, 26.75MHz, CMOS, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
IDT
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