AV9154A-27CN16LF [IDT]
Processor Specific Clock Generator, 80.18MHz, CMOS, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16;
| 型号： | AV9154A-27CN16LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 80.18MHz, CMOS, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总10页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
AV9154A
Low-Cost 16-Pin Frequency Generator
General Description
The AV9154A is a 0.8mm version of the industry leading AV9154.
Like the AV9154, the AV9154A is a low-cost frequency generator
designedforgeneralpurposePCanddiskdrive applications. However,
because the AV9154A uses 0.8mm technology and the latest phase-
locked loop architecture, it offers performance advantages that
enable the device to be sold into Pentium™ systems.
Features
.
•
•
•
•
•
•
•
Compatible with 386, 486 and Pentium CPUs
45/55 Duty cycle
Runs up to 66 MHz at 3.3V
Single pin can slow clock to 8 MHz (on -42 and -43)
Single pin can stop the CPU clock glitch-free (on -43)
Very low jitter, ±250ps for Pentium frequencies
1X and 2X CPU clocks skew controlled to ±250ps (-42
only)
TheAV9154A guarantees a 45/55 duty cycle over all frequencies. In
addition, a worst case jitter of ±250ps is specified at Pentium
frequencies.
•
•
•
•
Smooth transitions between all CPU frequencies
Slow frequency ramp at power-on avoids CPU lock-up
16-pin PDIP or 150-mil skinny SOIC packages
0.8µm CMOS technology
The CPU clock offers the unique feature of smooth, glitch-free
transitions from one frequency to the next, making this the ideal
device to use when slowing the CPU speed. The AV9154A makes a
gradual transition between frequencies so that it obeys the Intel
cycle-to-cycle timing specifications for 486 and Pentium systems.
Applications
Computer motherboards: The AV9154A-ST replaces crystals
and oscillators, saving board space, component cost, part
count and inventory costs. It produces a switchable CPU clock
anduptofourfixedclockstodrivefloppydisk, communications,
super I/O, Bus, and/or keyboard devices. The small package
and 3.3V operation is perfect for handheld computers.
TheAV9154A-42 andAV9154A-43 devicesoffer featuresspecifically
for green PCs. The AV9154A-42 and -43 have a single pin that,
when pulled low, will smoothly slow the 2XCPU clock to 8 MHz.
This is ideal for dynamic DX microprocessors. The AV9154A-43
not only has the slow clock feature, but also offers a glitch-free stop
clock for static SX microprocessors. The STOPCLK# pin, when
pulled low, enables the 2XCPU clock to go low only after completing
its last full cycle. The clock continues to run internally, and will be
output again on the first full cycle immediately following stop clock
disable.
The simultaneous 2X and 1X CPU clocks offer controlled skew to
within 500ps of each other (-42 only).
ICS has been shipping motherboard frequency generators since
April 1990, and is the leader in the area of multiple output clocks on
a single chip. Consult ICS for all your clock generation needs.
Block Diagram
Pentium is a trademark of Intel Corporation
9154 Rev B 04/17/97
AV9154A
Pin Configuration
16-Pin PDIP or SOIC
AV9154A-27
16-Pin PDIP or SOIC
AV9154A-42
16-Pin PDIP or SOIC
AV9154A-43
Description of new pin:
Description of new pis:
SLOWCLK#forces2XCPUCLK
output to ramp smoothly to
8MHz and CPUCLK output to 4
MHz when pulled low.
SLOWCLK#forces2XCPUCLK
output to ramp smoothly to
8MHz when pulled low.
STOPCLK# provides gilitch-
free stop of the 2XCPUCLK
output when pulled low. When
raised
back
high,
the
2XCPUCLK output clock
resumes full speed operation
(no clock frequency ramp up
since the internal VCO is not
stopped).
16-Pin PDIP or SOIC
9154-04
16-Pin PDIP or SOIC
9154-10
16-Pin PDIP or SOIC
9154-26
2
AV9154A
Stop Clock Feature
The ICS9154A-43 incorporates a unique stop clock
feature compatible with static logic processors. When
the stop clock pin goes low, the 2XCPUCLK will go
low after the next occurring falling edge. When
STOPCLK again goes high, 2XCPUCLK resumes on
the next rising edge of the internal clock. This feature
enables fast, glitch-free starts and stops of the
2XCPUCLK and is guaranteed that the CPU does not
receive any short period clocks.
3
AV9154A
Pin Descriptions
Frequencies based upon 14.318 MHz input)
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Digital power (3.3 or 5V).
Digital power (3.3 or 5V).
Digital ground.
-4
-10
-26
-27
-42
-43
4
13
5
4
13
5
4
13
5
4
13
5
4
13
5
4
13
5
12
8
VDD
VDD
GND
GDD
AGND
P
P
P
P
P
12
8
12
8
12
8
12
8
12
8
Digital ground.
Analog ground.
Frequency select 0 for CPU clock
(has internal pull-up).*
Frequency select 1 for CPU clock
(has internal pull-up).*
1
16
15
1
16
15
1
1
FS0
FS1
I
I
16
16
16
16
Frequency select 2 for CPU clock
(has internal pull-up).*
Tristates outputs when low (has internal pull-up).*
Slows 2XCPU clock to 8 MHz (active low)
(has internal pull-up).
10
-
-
-
-
10
9
10
9
9
-
10
-
FS2
OE
I
I
I
-
-
-
15
15
SLOWCLK#
Stops 2XCPU clock glitch-free (active low)
(has internal pull-up).
-
-
-
-
-
9
STOPCLK#
I
3
2
11
3
2
10
3
2
11
3
2
11
3
2
10
3
2
11
X1
X2
I
O
O
Crystal In.
Crystal Out.
14.318 MHz reference clock output.
14.318 MHz
-
7
1
-
-
1.84 MHz
O
1.84 MHz (comm) clock output.
6
-
11
6
6
-
6
-
6
-
6
-
24 MHz
16 MHz
12 MHz
O
O
O
24 MHz (floppy disk) clock output.
16 MHz clock output.
-
-
7
7
-
-
12 MHz keyboard clock output.
7
1
-
-
7
7
8 MHz
O
8 MHz keyboard clock output.
CPU clock output.
14
15
9
14
-
14
15
-
-
14
-
11
14
-
-
14
-
CPUCLK
2XCPUCLK
PD#
O
O
I
2X CPU clock output.
-
Power-Down All (active low) (has internal pull-up).
Power-Down Fixed Clock
(1.84, 8, 16, 24) (active low).**
-
9
-
-
-
-
PDFCLK#
I
Note:
Internal Pull-up Resistors.
* -04 and -10 have no pull-ups or frequency select pins
** -10 has no pull-up or Pin 9 PDFCLK
4
AV9154A
Clock Tables
(using 14.318 MHz input, all frequencies in MHz)
-43
2XCPUCLK
-42
-27
FS0
FS2
FS1
2XCPUCLK
2XCPUCLK
CPUCLK
8
^
16
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75*
32
16
40
20
40
60
33.33
25
16.67
12.50
30
33.33
25
40
50
60
60
66.66
80*
52
20
10
20
66.66
50
33.33
25
66.66
50
Actual Frequencies
(using 14.318 MHz input, all frequencies in MHz)
-42
-43
2XCPUCLK
16.00
-27
2CPUCLK
FS2
FS1
FS0
2XCPUCLK
16.00
CPUCLK
8.00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75.17*
31.94
60.14
40.09
50.11
66.48
80.18*
51.90
40.09
20.05
16.71
12.55
30.07
10.03
33.24
25.06
40.09
33.41
33.41
25.06
25.06
60.14
60.14
20.05
20.05
66.48
66.48
50.11
50.11
Clock Table for AV9154A-26
(using 14.318 MHz input all frequencies in
MHz)
Clock Tables in MHz
for -04 and -10
(using 14.318 MHz input ,
all frequencies in MHz)
Fixed Clock Output
Actual Frequencies
(using 14.318 MHz input,
all freqencies in MHz)
FS(2:0)
2XCPU
(MHz)
CPUCLK
(MHz)
-04
-10
FS(3:0)
14.318
1.84
24.0
12.0
8.0
CPUCL-
K
0
1
2
3
4
5
6
7
100.23*
80.18*
66.48*
50.11
50.11
40.09
33.24
25.06
20.05
16.11
12.12
7.88
2XCPU
CPU
0
1
2
3
4
5
6
7
-
100*
80*
66.6
50
50*
40*
33.3
25
PDCPU
40
50
40.09
66.6
32.22
40
20
-
-
-
-
24.23
32
16
15.75
24
12
16
8
* These selections only operate at 5 V.
5
AV9154A
Absolute Maximum Ratings
VDD referenced to GND ........................................................................... 7.0 V
Voltage on I/O pins referenced to GND ..... GND - 0.5 V to VDD + 0.5 V
Operating Temperature under bias .............................................. 0 to +70 ºC
Power Dissipation ................................................................................... 0.5 W
Storage Temperature ............................................................... -40 to +150 ºC
Stresses above those listed underAbsolute Maximum Ratings may cause permanent damage to the device.These ratings are stess
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics at 3.3V
VDD = 3.3 V ± 10%, TA = 0 - 70 oC unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage1
Output Low Current1
Output High Current1
Supply Current
SYMBOL
VIL
TEST CONDITIONS
MIN
-
0.7 V
-
-5.0
-
0.85 VDD
TYP
-
-
2.5
MAX
0.2 VDD
UNITS
V
V
A
A
V
VIH
IIL
IIH
VOL
VOH
IOL
IOH
IDD
-
7.0
5.0
VIN = 0V (pull-up pin)
VIN = VDD
IOL = 6mA
-
0.05 VDD
0.94 VDD
24
0.1 VDD
IOH = -4mA
-
-
V
VOL = 0.2VDD
VOH = 0.7VDD
unloaded, 60 MHz
15.0
-
-
mA
mA
mA
-13
16
-8.0
34
O u t p u t F r e q u e n c y
Change over Supply
and Temperature1
FD
With respect to typical frequency
-
0.002
0.01
%
Short circuit current1
Input Capacitance1
Load Capacitance1
Pull-up Resistor1
ISC
CI
CL
Rpu
each output clock
except X1, X2
pins X1, X2
20
-
-
30
-
20
620
-
10
-
mA
pF
pF
at VDD - 0.5V
-
900
k ohm
Notes:
1. Parameter is guaranteed by design and characterization.
6
AV9154A
Electrical Characteristics at 3.3V
VDD = 3.3V ± 10%, TA = 0 - 70 oC unless otherwise stated
AC Characteristics
TEST CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Input Clock Rise Time1
Input Clock Fall Time1
t
-
-
-
-
20
20
ns
ns
ICr
tICf
Rise time, 20% to 80%
r
t
15pF load
-
2.2
3.5
ns
1
DD
V
Fall time, 80% to 20%
f
t
15pF load
15pF load
15pF load
-
1.2
2.5
ns
%
%
1
DD
V
1
DD
t
Duty cycle at 50% V
d
40/60
50/65
48/52
43/57
60/40
65/50
Duty cycle, reference
clocks1
t
d
Jitter, one sigma, 20-66
MHz clocks1
Jitter, one sigma, clocks
below 20 MHz1
Jitter, absolute, 20-66
MHz clocks1
Jitter, absolute, clocks
below 20 MHz1
Input Frequency1
j1s
t
10,000 cycles
10,000 cycles
10,000 cycles
10,000 cycles
-
-
100
1.0
-
200
2.0
ps
%
ps
tjls
jab
t
-350
350
jab
t
-
1.5
14.318
-
4.0
32
-
%
in
f
2
MHz
MHz
Maximum Output
Frequency1
out
f
70
Clock skew between CPU
and 2XCPU outputs1
Power-up Time1
sk
T
AV9154A-42
-
-
-
220
6
500
12
ps
tPO
t
off to 50 MHz
from 8 to 50 MHz
ms
ms
Frequency Transition
Time1
ft
t
4.5
10
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
7
AV9154A
Electrical Characteristics at 5.0V
VDD = +5 ± 10% V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
TEST CONDITIONS
PARAMETER
Input Low Voltage
SYMBOL
MIN
-
TYP
-
MAX
0.8
UNITS
V
IL
DD
=5 V
V
V
IH
DD
Input High Voltage
Input Low Current
Input High Current
V
V
=5 V
2.0
-
-
6
-
-
15
5
V
A
A
IL
IN
V =0 V (pull-up pin)
I
IH
IN
V
DD
= V
I
-5
OL
OL
Output Low Voltage
Output High Voltage1
V
I
= 10 mA
= -30 mA
-
0.15
3.7
0.4
-
V
V
OH
OH
I
V
2.4
Output Low Current1
Output High Current1
I
V
= 0.8 V
= 2.4 V
25
-
45
-
mA
mA
OL
OL
OH
OH
V
I
-53
-35
DD
Supply Current
I
unloaded, 66 MHz
-
-
25
50
mA
%
Output Frequency Change
over Supply and Temperature1
with respect to typical
frequency
D
F
0.002
0.01
Short circuit current1
Input Capacitance1
Load Capacitance1
Pull-up Resistor1
I
each output clock
except X1, X2
pins X1, X2
25
-
40
-
-
10
-
mA
pF
SC
I
C
L
C
-
20
400
pF
pu
R
DD
A + V -1 V
-
700
k ohm
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
8
AV9154A
Electrical Characteristics at 5.0V
VDD = +5 ±10% V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
TEST CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Input Clock Rise Time1
t
-
-
-
-
20
20
ns
ns
ICr
Input Clock Fall Time1
Output Rise time, 0.8 to
2.0V1
Rise time, 20% to 80% V1
Output Fall time, 2.0 to
0.8V1
ICf
t
r
t
15pF load
-
-
-
1.5
2.0
0.5
2
3
ns
ns
ns
r
t
15pF load
15pF load
f
t
1.5
Fall time, 80% to 20% V1
t
15pF load
-
2.0
3.0
ns
%
%
f
Duty cycle at 1.4V1
15pF load, V = 5V±5%
45/55
40/65
48/52
43/57
55/45
65/40
t
d
DD
Duty cycle, reference
clocks1
t
d
15 pF load
Jitter, one sigma, 20 MHz-
80 MHz clocks1
Jitter, one sigma, clocks
below 20 MHz1
Jitter, absolute, 20 MHz-
80 MHz clocks1
Jitter, absolute, clocks
below 20 MHz1
j1s
t
10,000 cycles
10,000 cycles
10,000 cycles
10,000 cycles
-
-
70
0.8
-
140
2.0
ps
%
ps
jls
t
jab
t
-250
250
jab
t
-
2
1.0
14.318
-
3.0
32
-
%
in
Input Frequency
f
MHz
MHz
Maximum Output
Frequency1
out
f
140
Clock skew between CPU
and 2XCPU outputs1
Power-up Time1
sk
T
AV9154A-42
-
-
-
140
8
400
15
ps
ms
ms
tPO
t
to 80 MHz
Frequency Transition
Time1
ft
t
from 8 to 66.66 MHz
6.5
12
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
9
AV9154A
0.260
0.325
0.765
0.130
0.015min
0.010
0.360
0 ~ 5º
0.060
0.018
0.130
0.100
16-Pin PDIP Package
0.063
0.031
0.238
0.390
0.015
0.154
0.008
0.050
0.024
0.006±0.004
0.016
0.025
16-Pin SOIC Package
Ordering Information
AV9154A-04CN16
AV9154A-10CN16
AV9154A-26CN16
AV9154A-27CN16
AV9154A-42CN16
AV9154A-43CN16
AV9154A-04CS16
AV9154A-10CS16
AV9154A-26CS16
AV9154A-27CS16
AV9154A-42CS16
AV9154A-43CS16
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1,2, or 3 digits
W=0.3" SOIC or 0.6" DIP; None=Standard Width
Package Type
N=DIP (Plastic),
S=SOIC
Pattern Number (2 or 3-digit number for parts with ROM-code patterns)
Device Type (consists of 3 or 4-digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock device
10
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