AV9154A-04CS16LF [IDT]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO16, 0.150 INCH, ROHS COMPLIANT, SKINNY, SOIC-16;
| 型号： | AV9154A-04CS16LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO16, 0.150 INCH, ROHS COMPLIANT, SKINNY, SOIC-16 光电二极管 |
| 文件： | 总11页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
AV9154A
Systems, Inc.
Low-Cost 16-Pin Frequency Generator
General Description
Features
The AV9154A is a 0.8mm version of the industry leading
AV9154. Like the AV9154, the AV9154A is a low-cost
frequency generator designed for general purpose PC and
disk drive applications. However, because the AV9154A
uses 0.8mm technology and the latest phase-locked loop
architecture, it offers performance advantages that enable
the device to be sold into Pentium™ systems.
•
•
•
•
•
•
•
Compatible with 386, 486 and Pentium CPUs
45/55 Duty cycle
Runs up to 66 MHz at 3.3V
Single pin can slow clock to 8 MHz (on -4± and -43)
Single pin can stop the CPU clock glitch-free (on -43)
Very low jitter, ±±50ps for Pentium frequencies
1X and ±X CPU clocks skew controlled to ±±50ps (-4±
only)
The AV9154A guarantees a 45/55 duty cycle over all
frequencies. In addition, a worst case jitter of ±±50ps is
specified at Pentium frequencies.
•
•
•
•
Smooth transitions between all CPU frequencies
Slow frequency ramp at power-on avoids CPU lock-up
16-pin PDIP or 150-mil skinny SOIC packages
0.8µm CMOS technology
The CPU clock offers the unique feature of smooth, glitch-
free transitions from one frequency to the next, making this
the ideal device to use when slowing the CPU speed. The
AV9154A makes a gradual transition between frequencies
so that it obeys the Intel cycle-to-cycle timing specifications
for 486 and Pentium systems.
Applications
Computer motherboards: The AV9154A-ST replaces crystals
and oscillators, saving board space, component cost, part
count and inventory costs. It produces a switchable CPU
clock and up to four fixed clocks to drive floppy disk,
communications, super I/O, Bus, and/or keyboard devices.
The small package and 3.3V operation is perfect for handheld
computers.
The AV9154A-4± and AV9154A-43 devices offer features
specifically for green PCs. The AV9154A-4± and -43 have a
single pin that, when pulled low, will smoothly slow the ±XCPU
clock to 8 MHz. This is ideal for dynamic DX microprocessors.
The AV9154A-43 not only has the slow clock feature, but
also offers a glitch-free stop clock for static SX
microprocessors. The STOPCLK# pin, when pulled low,
enables the ±XCPU clock to go low only after completing its
last full cycle. The clock continues to run internally, and will
be output again on the first full cycle immediately following
stop clock disable.
The simultaneous ±X and 1X CPU clocks offer controlled
skew to within 500ps of each other (-4± only).
ICS has been shipping motherboard frequency generators
since April 1990, and is the leader in the area of multiple
output clocks on a single chip. Consult ICS for all your clock
generation needs.
Block Diagram
0174C—04/06/06
Integrated
Circuit
AV9154A
Systems, Inc.
Pin Configuration
16-Pin PDIP or SOIC
AV9154A-42
16-Pin PDIP or SOIC
16-Pin PDIP or SOIC
AV9154A-27
AV9154A-43
Description of new pin:
Description of new pis:
SLOWCLK# forces ±XCPUCLK
output to ramp smoothly to 8MHz
and CPUCLK output to 4 MHz
when pulled low.
SLOWCLK# forces ±XCPUCLK
output to ramp smoothly to 8MHz
when pulled low. STOPCLK#
provides gilitch-free stop of the
±XCPUCLK output when pulled
low. When raised back high, the
±XCPUCLK
output
clock
resumes full speed operation (no
clock frequency ramp up since
the internal VCO is not stopped).
16-Pin PDIP or SOIC
AV9154A-04
16-Pin PDIP or SOIC
AV9154A-26
16-Pin PDIP or SOIC
AV9154A-10
0174C—04/06/06
2
Integrated
Circuit
AV9154A
Systems, Inc.
Stop Clock Feature
The ICS9154A-43 incorporates a unique stop clock feature compatible with static logic processors. When the stop clock pin
goes low, the ±XCPUCLK will go low after the next occurring falling edge. When STOPCLK again goes high, ±XCPUCLK
resumes on the next rising edge of the internal clock. This feature enables fast, glitch-free starts and stops of the ±XCPUCLK
and is guaranteed that the CPU does not receive any short period clocks.
±XCPUCLK
STOPCLK#
0174C—04/06/06
3
Integrated
Circuit
AV9154A
Systems, Inc.
Pin Descriptions
Frequencies based upon 14.318 MHz input)
PIN NAME
TYPE
DESCRIPTION
Digital power (3.3 or 5V).
Digital power (3.3 or 5V).
Digital ground.
PIN NUMBER
-4
4
-10
4
-±6
4
-±7
4
-4±
4
13
5
1±
8
-43
4
13
5
1±
8
VDD
VDD
GND
GDD
AGND
P
P
P
P
P
13
5
13
5
13
5
13
5
1±
8
1±
8
1±
8
1±
8
Digital ground.
Analog ground.
Frequency select 0 for CPU clock
(has internal pull-up).*
Frequency select 1 for CPU clock
(has internal pull-up).*
Frequency select ± for CPU clock
(has internal pull-up).*
Tristates outputs when low (has internal pull-up).*
Slows ±XCPU clock to 8 MHz (active low)
(has internal pull-up).
1
16
15
1
16
15
1
1
FS0
FS1
I
I
16
16
16
16
10
-
-
-
-
10
9
10
9
9
-
10
-
FS±
OE
I
I
I
-
-
-
15
15
SLOWCLK#
Stops ±XCPU clock glitch-free (active low)
(has internal pull-up).
-
-
-
-
-
9
STOPCLK#
I
3
±
11
-
6
-
-
7
14
15
9
3
±
10
7
11
6
-
1
14
-
3
±
11
3
±
11
1
6
-
7
-
-
3
±
10
-
6
-
-
7
11
14
-
3
±
11
-
6
-
-
7
-
X1
X±
I
Crystal In.
Crystal Out.
O
O
O
O
O
O
O
O
O
I
14.318 MHz
1.84 MHz
±4 MHz
16 MHz
1± MHz
8 MHz
CPUCLK
±XCPUCLK
PD#
14.318 MHz reference clock output.
1.84 MHz (comm) clock output.
±4 MHz (floppy disk) clock output.
16 MHz clock output.
1± MHz keyboard clock output.
8 MHz keyboard clock output.
CPU clock output.
±X CPU clock output.
Power-Down All (active low) (has internal pull-up).
Power-Down Fixed Clock
6
-
7
-
14
15
-
14
-
14
-
-
-
9
-
-
-
-
PDFCLK#
I
(1.84, 8, 16, ±4) (active low).*
Note:
Internal Pull-up Resistors.
* -04 and -10 have no pull-ups or frequency select pins
** -10 has no pull-up or Pin 9 PDFCLK
0174C—04/06/06
4
Integrated
Circuit
AV9154A
Systems, Inc.
Clock Tables
(using 14.318 MHz input, all frequencies in MHz)
-43
±XCPUCLK
-±7
±XCPUCLK
FS±
FS1
FS0
-4±
±XCPUCLK
CPUCLK
^
16
40
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75*
3±
16
40
8
±0
60
40
50
66.66
80*
5±
33.33
±5
60
±0
66.66
50
16.67
1±.5
30
10
33.33
±5
33.33
±5
60
±0
66.66
50
Actual Frequencies
(using 14.318 MHz input, all frequencies in MHz)
-±7
±XCPUCLK
75.17*
31.94
-4±
-43
±XCPUCLK
16.00
FS±
FS1
FS0
±XCPUCLK
16.00
CPUCLK
8.00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
40.09
33.41
±5.06
60.14
±0.05
66.48
50.11
±0.05
16.71
1±.55
30.07
10.03
33.±4
±5.06
40.09
33.41
±5.06
60.14
±0.05
66.48
50.11
60.14
40.09
50.11
66.48
80.18*
51.90
Fixed Cloxk Output
Actual Frequencies
(using 14.318 MHz input,
Clock Table for AV9154A-26
(using 14.318 MHz input,
Clock Tables in MHz
for -04 and -10
(using 14.318 MHz input,
all frequencies in MHz)
all frequencies in MHz)
all frequencies in MHz)
±XCPU
(MHz)
100.±3*
80.18*
66.48*
50.11
40.09
3±.±±
±4.±3
15.75
CPUCLK
(MHz)
50.11
40.09
33.±4
±5.06
±0.05
16.11
1±.1±
7.88
FS(±:0)
14.318
1.84
±4.0
1±.0
8.0
-04
-10
0
1
±
3
4
5
6
7
FS(3:0)
±XCPU
CPU
CPUCLK
0
1
±
3
4
5
6
7
-
100*
80*
66.6
50
50*
40*
33.3
±5
PDCPU
40
50
66.6
-
-
-
-
40
±0
3±
16
±4
1±
16
8
0174C—04/06/06
5
Integrated
Circuit
AV9154A
Systems, Inc.
Absolute Maximum Ratings
VDD referenced to GND .......................................................................... 7.0 V
Voltage on I/O pins referenced to GND . . . . . . . GND - 0.5 V to VDD + 0.5 V
Operating Temperature under bias . . . . . . . . . . 0 to +70 ºC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
Storage Temperature . . . . . . . . . . . . . . . . . . . . . -40 to +150 ºC
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stess specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics at 3.3 V
VDD = 3.3 V ± 10ꢀ, TA = 0 - 70 oC unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage1
Output Low Current1
Output High Current1
Supply Current
SYMBOL TEST CONDITIONS
MIN
-
0.7 V
-
-5
-
TYP
-
-
±.5
-
MAX
0.± VDD
UNITS
V
V
A
A
V
V
mA
mA
mA
VIL
VIH
-
7
5
IIL
IIH
VIN = 0V (pull-up pin)
VIN = VDD
VOL
IOL = 6mA
0.05 VDD 0.1 VDD
VOH IOH = -4mA
0.85 VDD 0.94 VDD
-
-
-8
34
IOL
IOH
IDD
VOL = 0.±VDD
VOH = 0.7VDD
unloaded, 60 MHz
15
-
-
±4
-13
16
Output Frequency Change over
Supply and Temperature1
Short circuit current1
Input Capacitance1
Load Capacitance1
Pull-up Resistor1
FD
With respect to typical frequency
-
0.00±
0.01
ꢀ
ISC
CI
CL
each output clock
except X1, X±
pins X1, X±
±0
-
-
30
-
±0
6±0
-
10
-
mA
pF
pF
Rpu
at VDD - 0.5V
-
900
k ohm
Notes:
1. Parameter is guaranteed by design and characterization.
0174C—04/06/06
6
Integrated
Circuit
AV9154A
Systems, Inc.
Electrical Characteristics at 3.3 V
VDD = 3.3 V ± 10ꢀ, TA = 0 - 70 oC unless otherwise stated
AC Characteristics
TEST CONDITIONS
PARAMETER
SYMBOL
MIN
-
TYP
-
MAX
±0
UNITS
ns
Input Clock Rise
Time1
t
ICr
Input Clock Fall
t
ICf
-
-
±0
3.5
ns
ns
ns
ꢀ
Time1
Rise time, ±0ꢀ to
t
r
15pF load
-
±.±
1
80ꢀ VDD
Fall time, 80ꢀ to
t
f
15pF load
15pF load
15pF load
10,000 cycles
-
1.±
±.5
1
±0ꢀ VDD
Duty cycle at 50ꢀ
d
d
t
t
40/60
50/65
-
48/5±
43/57
100
60/40
65/50
±00
1
V
DD
Duty cycle, reference
ꢀ
clocks1
Jitter, one sigma, ±0-
66 MHz clocks1
Jitter, one sigma,
clocks below ±0
MHz1
t
j1s
ps
t
jls
10,000 cycles
10,000 cycles
10,000 cycles
-
-350
-
1.0
-
±.0
350
4.0
ꢀ
ps
ꢀ
Jitter, absolute, ±0-66
t
t
jab
jab
MHz clocks1
Jitter, absolute,
clocks below ±0
MHz1
1.5
Input Frequency1
f
in
±
14.318
-
3±
-
MHz
MHz
Maximum Output
f
out
70
Frequency1
Clock skew between
CPU and ±XCPU
outputs1
T
sk
AV9154A-4±
-
±±0
500
ps
Power-up Time1
t
tPO
off to 50 MHz
-
-
6
1±
10
ms
ms
Frequency Transition
Time1
t
ft
from 8 to 50 MHz
4.5
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
0174C—04/06/06
7
Integrated
Circuit
AV9154A
Systems, Inc.
Electrical Characteristics at 5.0 V
V
DD = +5 ± 10ꢀ V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
TEST CONDITIONS
PARAMETER
SYMBOL
MIN
-
TYP
-
MAX
0.8
UNITS
V
Input Low Voltage
V
IL
IH
IL
V
DD=5 V
Input High Voltage
Input Low Current
Input High Current
V
V
V
V
DD=5 V
±.0
-
-
6
-
-
V
A
A
I
IN=0 V (pull-up pin)
IN = VDD
15
5
I
IH
-5
Output Low Voltage
V
OL
I
OL = 10 mA
OH = -30 mA
-
0.15
0.4
V
Output High Voltage1
Output Low Current1
Output High Current1
V
OH
I
±.4
±5
-
3.7
45
-
-
V
I
OL
V
OL = 0.8 V
OH = ±.4 V
mA
mA
I
OH
DD
V
-53
-35
Supply Current
I
unloaded, 66 MHz
-
-
±5
50
mA
ꢀ
Output Frequency
Change over Supply
and Temperature1
with respect to
typical frequency
F
D
0.00±
0.01
Short circuit current1
Input Capacitance1
Load Capacitance1
Pull-up Resistor1
I
SC
each output clock
except X1, X±
pins X1, X±
±5
-
40
-
-
10
-
mA
pF
CI
C
L
-
±0
400
pF
R
pu
A + VDD -1 V
-
700
k ohm
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
0174C—04/06/06
8
Integrated
Circuit
AV9154A
Systems, Inc.
Electrical Characteristics at 5.0 V
VDD = +5 ±10ꢀ V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
-
TYP
-
MAX
±0
UNITS
Input Clock Rise
Time1
tICr
ns
ns
ns
ns
ns
ns
ꢀ
Input Clock Fall
t
ICf
-
-
±0
±
Time1
Output Rise time, 0.8
to ±.0V1
t
t
r
r
15pF load
15pF load
15pF load
15pF load
-
1.5
Rise time, ±0ꢀ to
-
±.0
3
80ꢀ V1
Output Fall time, ±.0
to 0.8V1
t
t
f
f
-
0.5
1.5
Fall time, 80ꢀ to
-
±.0
3.0
±0ꢀ V1
15pF load, VDD
5V±5ꢀ
=
Duty cycle at 1.4V1
d
t
t
45/55
40/65
-
48/5±
43/57
70
55/45
65/40
140
Duty cycle, reference
clocks1
d
15 pF load
ꢀ
Jitter, one sigma, ±0
MHz- 80 MHz clocks1
Jitter, one sigma,
clocks below ±0
MHz1
Jitter, absolute, ±0
MHz- 80 MHz clocks1
Jitter, absolute,
clocks below ±0
MHz1
tj1s
10,000 cycles
ps
t
jls
10,000 cycles
10,000 cycles
10,000 cycles
-
-±50
-
0.8
-
±.0
±50
3.0
ꢀ
ps
ꢀ
t
t
jab
jab
1.0
Input Frequency
f
in
±
14.318
-
3±
-
MHz
MHz
Maximum Output
fout
140
Frequency1
Clock skew between
CPU and ±XCPU
outputs1
Power-up Time1
T
sk
AV9154A-4±
to 80 MHz
-
140
400
ps
t
tPO
ft
-
-
8
15
1±
ms
ms
Frequency Transition
Time1
t
from 8 to 66.66 MHz
6.5
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
0174C—04/06/06
9
Integrated
Circuit
AV9154A
Systems, Inc.
0.±60
0.3±5
0.765
0.130
0.015min
0.010
0.360
0 ~ 5º
0.060
0.018
0.130
0.100
16-Pin PDIP Package
0.063
0.031
0.±38
0.390
0.015
0.154
0.008
0.050
0.0±4
0.006±0.004
0.016
0.0±5
16-Pin SOIC Package
Ordering Information
AV9154A-04CN16
AV9154A-10CN16
AV9154A-±6CN16
AV9154A-±7CN16
AV9154A-4±CN16
AV9154A-43CN16
AV9154A-04CS16
AV9154A-10CS16
AV9154A-±6CS16
AV9154A-±7CS16
AV9154A-4±CS16
AV9154A-43CS16
Example:
ICS XXXX PPP M X#W LF
Lead Free, RoHS Compliant (Optional)
Lead Count & Package Width
Lead Count=1, ± or 3 digits
W=0.3" SOIC or 0.6" DIP; None=Standard Width
Package Type
N = DIP (Plastic)
S = SOIC
Pattern Number (2 or 3 digit number for parts with ROM-code patterns)
Device Type
Prefix
0174C—04/06/06
ICS = Standard Device
10
Integrated
Circuit
AV9154A
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
10
C
4/6/±006 Added LF Ordering Information
0174C—04/06/06
11
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