9DBV0431AKILFT [IDT]
4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer (ZDB/FOB);
| 型号： | 9DBV0431AKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer (ZDB/FOB) PC |
| 文件： | 总16页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-output 1.8V PCIe Gen1-2-3
Zero-delay/Fanout Buffer (ZDB/FOB)
9DBV0431
DATASHEET
Description
Features/Benefits
The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
• LP-HCSL outputs save 8 resistors; minimal board space
and BOM cost
• 53mW typical power consumption in PLL mode; minimal
power consumption
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
Recommended Application
• Programmable Slew rate for each output; allows tuning for
various line lengths
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
• Programmable output amplitude; allows tuning for various
Output Features
• 4 - 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for 12k-20MHz
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 32-pin 5x5mm VFQFPN; minimal board
space
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Block Diagram
vOE(3:0)#
4
CLK_IN
DIF3
DIF2
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
vSADR
^vHIBW_BYPM_LOBW#
CONTROL
LOGIC
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
9DBV0431 REVISION E 04/28/16
1
©2016 Integrated Device Technology, Inc.
9DBV0431 DATASHEET
Pin Configuration
32 31 30 29 28 27 26 25
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
vOE2#
DIF2#
DIF2
24
23
22
21
20
19
18
FB_DNC# 3
9DBV0431
epad is Gnd
VDDR1.8 4
VDDA1.8
GNDA
DIF1#
DIF1
CLK_IN 5
CLK_IN# 6
GNDR
7
8
GNDDIG
17 vOE1#
9
10 11 12 13 14 15 16
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
+
Read/Write bit
SADR
Address
1101011
1101100
1101101
x
x
x
0
M
1
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SMBus
OEx bit
DIFx
CKPWRGD_PD#
CLK_IN
OEx# Pin
PLL
True O/P
Low
Comp. O/P
Low
0
1
1
1
X
X
0
X
X
0
Off
On1
On1
On1
Running
Running
Running
Low
Low
1
1
Running
Low
Running
Low
1
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
Power Connections
PLL Operating Mode
Pin Number
VDD
4
Byte1 [7:6] Byte1 [4:3]
Description
HiBW_BypM_LoBW#
MODE
PLL Lo BW
Bypass
Readback
Control
00
GND
7
0
M
1
00
01
11
Input receiver analog
Digital Power
DIF outputs
01
9
8
15,20,26,30
20
PLL Hi BW
11
16, 25
21
PLL Analog
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
CLK_IN
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
(MHz)
100.00
50.00
125.00
Reserved
10
11
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
2
REVISION E 04/28/16
9DBV0431 DATASHEET
Pin Descriptions
Pin# Pin Name
Type
Pin Description
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
1
2
3
4
^vHIBW_BYPM_LOB
FB_DNC
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
1.8V power for differential input clock (receiver). This VDD should be treated as an
Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
DNC
FB_DNC#
DNC
VDDR1.8
PWR
5
6
7
8
9
CLK_IN
CLK_IN#
GNDR
GNDDIG
VDDDIG1.8
IN
IN
GND
GND
PWR
IN
1.8V digital power (dirty power)
10 SCLK_3.3
11 SDATA_3.3
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
I/O
12 vOE0#
IN
13 DIF0
14 DIF0#
15 GND
OUT
OUT
GND
PWR
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for outputs, nominally 1.8V.
16 VDDO1.8
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
17 vOE1#
IN
18 DIF1
OUT
OUT
GND
PWR
OUT
OUT
Differential true clock output
Differential Complementary clock output
Ground pin for the PLL core.
1.8V power for the PLL core.
Differential true clock output
Differential Complementary clock output
19 DIF1#
20 GNDA
21 VDDA1.8
22 DIF2
23 DIF2#
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
24 vOE2#
IN
25 VDDO1.8
26 GND
27 DIF3
PWR
GND
OUT
OUT
Power supply for outputs, nominally 1.8V.
Ground pin.
Differential true clock output
Differential Complementary clock output
28 DIF3#
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin.
29 vOE3#
30 GND
IN
GND
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down Mode.
This pin has internal pull-up resistor.
31 ^CKPWRGD_PD#
IN
LATCHED
IN
32 ^SADR_tri
33 ePad
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
Connect epad to ground.
GND
REVISION E 04/28/16
3
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
Test Loads
Low-Power Differential Output Test Load
5 inches
Rs
Rs
Zo=100ohm
2pF
2pF
Alternate Differential Output Terminations
Rs
33
27
Zo
100
85
Units
Ohms
Driving LVDS
3.3 Volts
R7b
Driving LVDS
R7a
Cc
L4
Rs
Rs
Cc
R8a
R8b
LVDS CLK
Input
Driving LVDS inputs with the 9DBV0431
Value
Receiver has Receiver does not
Component
R7a, R7b
R8a, R8b
Cc
termination
10K ohm
5.6K ohm
0.1 uF
have termination Note
140 ohm
75 ohm
0.1 uF
Vcm
1.2 volts
1.2 volts
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
4
REVISION E 04/28/16
9DBV0431 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
-0.5
TYP
MAX
2.5
VDD+0.5V
Power supply voltage
Input Voltage
VDDxx
VIN
Applies to all VDD pins
V
V
1,2
1, 3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
3.6V
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1150
UNITS NOTES
Differential inputs
(single-ended measurement)
Differential inputs
Input High Voltage - DIF_IN
VIHDIF
600
800
mV
mV
mV
1
1
1
Input Low Voltage - DIF_IN
VILDIF
VCOM
V
SS - 300
300
0
300
(single-ended measurement)
Input Common Mode Voltage
- DIF_IN
Common Mode Input Voltage
725
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
VSWING
dv/dt
IIN
Peak to Peak value (VIHDIF - VILDIF), single-ended
Measured differentially
300
0.4
-5
1450
mV
V/ns
uA
1
1,2
1
VIN = VDD , VIN = GND
5
dtin
Measurement from differential wavefrom
Differential Measurement
45
0
55
%
1
Input Jitter - Cycle to Cycle
JDIFIn
150
ps
1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
REVISION E 04/28/16
5
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
VDD
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
UNITS NOTES
Supply voltage for core, analog and LVCMOS
1.8V Supply Voltage
V
1
outputs
TCOM
TIND
VIH
VIM
VIL
Commmercial range
0
-40
25
25
70
85
°C
°C
V
1
1
1
1
1
1
Ambient Operating
Temperature
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
0.75 VDD
0.4 VDD
-0.3
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
IIN
-5
uA
Input Current
V
IN = 0 V; Inputs with internal pull-up resistors
IINP
-200
200
uA
1
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
Fibyp
Fipll100
Fipll125
Fipll62
Lpin
1
50
200
140
175
65
7
MHz
MHz
MHz
MHz
nH
2
2
100MHz PLL mode
100
125
50
Input Frequency
125MHz PLL mode
62.5
25
2
50MHz PLL mode
2
Pin Inductance
Capacitance
1
CIN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
1.5
1.5
5
pF
1
CINDIF_IN
COUT
2.7
6
pF
1,6
1
pF
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
Clk Stabilization
TSTAB
fMODIN
tLATOE#
tDRVPD
0.6
1
33
3
ms
kHz
1,2
1
Input SS Modulation
Frequency
30
1
31.5
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
clocks
us
1,3
1,3
175
300
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
ns
ns
V
1,2
1,2
1,4
1,5
1
Trise
tR
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
5
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
0.8
3.6
0.4
2.1
V
V
@ VOL
4
mA
V
1
1.7
3.6
1000
300
1
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SMBus Operating Frequency fMAXSMB
Maximum SMBus operating frequency
400
kHz
1,7
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.25VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.7VDDSMB
6DIF_IN input
7The differential input clock must be running for the SMBus to be active
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
6
REVISION E 04/28/16
9DBV0431 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
SYMBOL
Trf
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
Scope averaging on 3.0V/ns setting
Scope averaging on 2.0V/ns setting
Slew rate matching, Scope averaging on
2
1.3
3.2
2.3
5.4
4
3.3
20
1, 2, 3
1, 2, 3
1, 2, 4
Slew rate matching
Voltage High
Trf
Δ
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
660
779
21
850
1,7
1,7
mV
Voltage Low
VLOW
-150
150
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
835
-42
1515
409
14
1150
1
1
mV
-300
300
250
mV
mV
mV
1,2,7
1,5,7
1, 6
Vcross_abs
Scope averaging off
Scope averaging off
550
140
-Vcross
Δ
1
Ω
Ω
Ω
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33 for Zo = 50 (100 differential
trace impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
∆
-
absolute) allowed. The intent is to limit Vcross induced modulation by setting Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
IDDROP
IDDOP
IDDROP
IDDOP
IDDRPD
IDDPD
VDDR, @100MHz
VDDA + VDD1.8, @100MHz
VDDR, @100MHz
4.2
27
6
33
3
mA
mA
mA
mA
mA
mA
1
1
Operating Supply Current
(PLL Mode)
2.2
1
Operating Supply Current
(PLL-Bypass Mode)
VDDA + VDD1.8, @100MHz
VDDR, CKPWRGD_PD# = 0
VDDA + VDD1.8, CKPWRGD_PD# = 0
20
25
0.3
1.2
1
0.014
0.95
1,2
1, 2
Powerdown Current
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped, and CKPWRGD_PD# pin low.
REVISION E 04/28/16
7
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
2
1
2.7
1.4
1.2
4
2
2
MHz
MHz
dB
1,5
1,5
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
Measured differentially, PLL Mode
45
-1
50.1
55
%
1
Duty Cycle Distortion
Skew, Input to Output
Skew, Output to Output
Jitter, Cycle to cycle
tDCD
Measured differentially, Bypass Mode @100MHz
-0.1
1
%
1,3
tpdBYP
tpdPLL
Bypass Mode, VT = 50%
PLL Mode VT = 50%
2550
0
3370
112
33
4200
200
50
ps
ps
ps
1
1,4
1,4
Commercial Operating Range, VT = 50%
tsk3
Industrial Operating Range, VT = 50%
PLL mode
33
13
0.1
55
50
1
ps
ps
ps
1,4
1,2
1,2
tjcyc-cyc
Additive Jitter in Bypass Mode
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Electrical Characteristics–Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
PCIe Gen 1
MIN
TYP
32
MAX
52
LIMIT
86
UNITS Notes
ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
ps
(rms)
ps
(rms)
0.8
2.4
1.4
2.6
0.6
3
3.1
1
1,2
tjphPCIeG2
1,2
Phase Jitter, PLL Mode
ps
tjphPCIeG3
tjphSGMII
0.5
1,2,4
(rms)
(PLL BW of 2-4MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
ps
(rms)
1.9
2.2
5.0
0.3
0.1
0.1
3
1,6
tjphPCIeG1
PCIe Gen 1
0.1
N/A
N/A
N/A
N/A
ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
ps
0.2
1,2,4
(rms)
tjphPCIeG2
ps
0.05
0.05
1,2,4
(rms)
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
Additive Phase Jitter,
Bypass Mode
ps
tjphPCIeG3
1,2,4
(rms)
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
fs
(rms)
tjphSGMIIM0
165
251
200
300
N/A
N/A
1,6
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
fs
(rms)
tjphSGMIIM1
1,6
1Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FGV0831 or equivalent
6 Driven by Rohde&Schwarz SMA100
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
8
REVISION E 04/28/16
9DBV0431 DATASHEET
Additive Phase Jitter Plot: 125M (12kHz to 20MHz)
REVISION E 04/28/16
9
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
written to Byte 8)
(H)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
starT bit
T
Slave Address
Slave Address
WRite
WR
WRite
WR
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus address is latched on SADR pin.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 10
REVISION E 04/28/16
9DBV0431 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Output Enable
Output Enable
Reserved
Output Enable
Reserved
Output Enable
Reserved
Type
0
1
Default
1
1
1
1
1
1
1
1
DIF OE3
DIF OE2
RW
RW
Low/Low
Low/Low
Enabled
Enabled
DIF OE1
DIF OE0
RW
RW
Low/Low
Low/Low
Enabled
Enabled
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Name
PLLMODERB1
PLLMODERB0
Control Function
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
Type
R
R
0
1
Default
Latch
Latch
See PLL Operating Mode Table
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
0
Bit 5
RW1
RW1
PLLMODE1
PLLMODE0
PLL Mode Control Bit 1
0
0
1
1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See PLL Operating Mode Table
PLL Mode Control Bit 0
Reserved
RW
Controls Output Amplitude
RW
AMPLITUDE 1
AMPLITUDE 0
00 = 0.6V
10= 0.8V
01 = 0.7V
11 = 0.9V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Slew Rate Selection
Slew Rate Selection
Reserved
Slew Rate Selection
Reserved
Slew Rate Selection
Reserved
Type
0
1
Default
1
1
1
1
1
1
1
1
SLEWRATESEL DIF3
SLEWRATESEL DIF2
RW
RW
2 V/ns
2 V/ns
3 V/ns
3 V/ns
SLEWRATESEL DIF1
SLEWRATESEL DIF0
RW
RW
2 V/ns
2 V/ns
3 V/ns
3 V/ns
SMBus Table: Frequency Select Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Type
0
1
Default
Reserved
Reserved
1
1
Enable SW selection of
frequency
SW frequency
change disabled
SW frequency
change enabled
FREQ_SEL_EN
RW
0
Bit 5
RW1
RW1
FSEL1
FSEL0
Freq. Select Bit 1
0
Bit 4
See Frequency Select Table
Freq. Select Bit 0
Reserved
Reserved
Adjust Slew Rate of FB
0
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
RW
2 V/ns
3 V/ns
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Byte 4 is Reserved and reads back 'hFF
REVISION E 04/28/16
11
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
0
0
0
0
1
Revision ID
A rev = 0000
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGV, 01 = DBV,
10 = DMV, 11= Reserved
0
1
0
0
0
1
0
0
Device Type
Device ID
000100 binary or 04 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 12
REVISION E 04/28/16
9DBV0431 DATASHEET
Marking Diagrams
ICS
BV0431AL
YYWW
COO
ICS
B0431AIL
YYWW
COO
LOT
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
TYP
VALUE
42
PARAMETER
SYMBOL
CONDITIONS
PKG
UNITS NOTES
C/W
C/W
Junction to Case
Junction to Base
°
°
°
°
°
°
1
1
1
1
1
1
θJC
θJb
θJA0
θJA1
θJA3
θJA5
2.4
39
33
28
27
C/W
C/W
C/W
C/W
Junction to Air, still air
Thermal Resistance
NLG32
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
1ePad soldered to board
REVISION E 04/28/16
13
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
9DBV0431 DATASHEET
Package Outline and Package Dimensions (NLG32)
(Ref)
ND & NE
Even
Seating Plane
(ND-1)x
(Ref)
e
A1
Index Area
(Typ)
If ND & NE
are Even
L
A3
e
2
N
1
2
N
Anvil
Singulation
1
2
(NE-1)x
(Ref)
e
-- or --
E2
E
E2
2
Sawn
Singulation
Top View
b
A
C
(Ref)
ND & NE
Odd
e
Thermal Base
D
D2
2
C
D2
0.08
Millimeters
Symbol
Min
0.80
0
Max
1.00
0.05
A
A1
A3
0.20 Reference
0.18 0.3
0.50 BASIC
5.00 x 5.00
b
e
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
N
3.00
3.30
3.30
0.50
3.00
0.30
32
8
ND
NE
8
Ordering Information
Part/Order Number Shipping Packaging
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
9DBV0431AKLF
9DBV0431AKLFT
9DBV0431AKILF
9DBV0431AKILFT
Trays
32-pin VFQFPN
32-pin VFQFPN
32-pin VFQFPN
32-pin VFQFPN
Tape and Reel
Trays
Tape and Reel
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 14
REVISION E 04/28/16
9DBV0431 DATASHEET
Revision History
Rev. Initiator Issue Date Description
Page #
1. Removed "Differential" from DS title and Recommended Application, corrected typo's in
Description.
2. Corrected spelling error in pullup/pulldown text under pinout
3. Updated all electrical tables and added "Industry Limit" column to "Phase Jitter
8/13/2012
Parameters".
1,2,5-
8,10,
12,13
A
RDW
4. Updated Byte3[0] to be consistent with Byte 2. Updated Byte6[7:6] definition.
5. Added thermal data to page 12.
6. Added NLG32 to "Package Outline and Package Dimensions" on page 13.
7. Move to final
1. "Input/Supply/Common Parameters" table modified as follows:
a. Updated Single-ended input logic thresholds to include missing mid-level on tri-level inputs. Adjusted logic
thresholds as follows:
i. Changed VIH min. from 0.65*VDD to 0.75*VDD
ii. Changed VIL max. from 0.35*VDD to 0.25*VDD
iii. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to 0.6*VDD.
iv. Clarified conditions for these specifications, accordingly.
b. Clarified the operating conditions and voltages of the SMBus to make it clear that the SMBus operates at
<3.3V by addition of footnotes 4 and 5 to "Input/Supply/Common Parameters" table.
2. Slight modifications of Slew Rates and typical values in the "DIF 0.7V Low Power Differential Outputs" table.
3. "Current Consumption" table modifed as follows:
a. Overall current consumption values lowered
b. VDDA is now grouped with VDD1.8 instead of VDDR
B
RDW
2/28/2013
5-8
c. Added separate current specs for PLL bypass mode.
d. Clarified that CKPWRDG_PD# is low for power down current.
4. "Output Duty Cycle, Jitter, Skew and PLL Characterisitics" table modifed as follows:
a. Bypass mode Input-to-Output skew changed from 3000 to 4500ps to 2550 to 4200ps. Typical value
reduced from 3500ps to 3370ps.
b. Separate Output-to-Output skew spec added for Industrial temp.
c. Additive cycle-to-cycle jitter spec reduced to 1ps max.
5. "Phase Jitter Parameters" modifed as follows:
a. Corrected typo in PLL Mode conditions for tjPHSGMII. Frequency integration range is 1.5MHz to 10MHz.
Bypass mode conditions were correct.
1. Updated front page text for consistency and updated block diagram resistor colors to
highlight internal resistors.
2. Updated max frequency of 100MHz PLL mode from 110MHz to 140MHz
C
RDW 11/26/2014 3. Updated max frequency of 125MHz PLL mode from 137.5MHz to 175MHz
4. Updated max frequency of 50MHz PLL mode from 55MHz to 65MHz
5. Updated Key Specifications with addtive phase jitter.
Various
6. Added additive phase jitter plot to specifications.
1. Updated block diagram with new format showing individual outputs instead of bussed
D
RDW
4/3/2015 outputs.
2. Updated pin out and pin descriptions to show ePad on package connected to ground.
1. Updated max frequency of 100MHz PLL mode to 140MHz
4/22/2016 2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
1-4
6
E
RDW
REVISION E 04/28/16
15
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)
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