9DBL0452BKILFT [IDT]
4-Output 3.3V PCIe Zero-delay Buffer;
| 型号： | 9DBL0452BKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 4-Output 3.3V PCIe Zero-delay Buffer PC |
| 文件： | 总19页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Output 3.3V PCIe Zero-delay
Buffer
9DBL0442 / 9DBL0452
DATASHEET
Description
Features/Benefits
The 9DBL0442 / 9DBL0452 devices are 3.3V members of
IDT's Full-Featured PCIe family. The 9DBL0442 / 9DBL0452
supports PCIe Gen1-4 Common Clocked (CC) and PCIe
Separate Reference Independent Spread (SRIS) systems. It
offers a choice of integrated output terminations providing
direct connection to 85 or 100 transmission lines. The
9DBL04P2 can be factory programmed with a user-defined
power up default SMBus configuration.
• Direct connection to 100 (xx42) or 85 (xx52)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 132mW typical power consumption in PLL mode;
eliminates thermal concerns
• SMBus-selectable features allows optimization to customer
requirements:
– control input polarity
– control input pull up/downs
– slew rate for each output
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Output Features
• 4 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
• 9DBL0442 default ZOUT = 100
• 9DBL0452 default ZOUT = 85
• 9DBL04P2 factory programmable defaults
• Easy AC-coupling to other logic families, see IDT
application note AN-891
• Customer defined SMBus power up default can be
programmed into P2 device; allows exact optimization to
customer requirements
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Key Specifications
• PCIe Gen1-2-3-4 CC compliant in ZDB mode
• PCIe Gen2 SRIS compliant in ZDB mode
• Supports PCIe Gen2-3 SRIS in fan-out mode
• DIF cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps
• Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device operation
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• 5 × 5 mm 32-VFQFPN package; minimal board space
• Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
9DBL0442 / 9DBL0452 FEBRUARY 22, 2017
1
©2017 Integrated Device Technology, Inc.
9DBL0442 / 9DBL0452 DATASHEET
Pin Configuration
32 31 30 29 28 27 26 25
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
vOE2#
DIF2#
DIF2
24
23
22
21
20
19
18
FB_DNC# 3
9DBL0442/52/P2
connect epad to
GND
VDDR3.3 4
VDDA3.3
NC
CLK_IN 5
CLK_IN# 6
vOE1#
DIF1#
NC
7
8
GNDDIG
17 DIF1
9 10 11 12 13 14 15 16
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased
to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
+
Read/Write bit
SADR
Address
1101011
1101100
1101101
x
x
x
0
M
1
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SMBus
OE bit
X
DIFx/DIFx#
CKPWRGD_PD#
CLK_IN
OEx# Pin
PLL
True O/P
Low1
Comp. O/P
Low1
0
1
1
1
X
X
0
Off
On3
On3
On3
Running
Running
Running
1
1
0
Running
Running
Disabled1
Disabled1
Disabled1
Disabled1
1
X
1. The output state is set by B11[1:0] (Low/Low default)
2. Input polarities defined as default values for xx42/xx52 devices.
3. If Bypass mode is selected, the PLL will be off, and outputs will be running.
Power Connections
PLL Operating Mode
Pin Number
Description
Byte1 [7:6] Byte1 [4:3]
VDD
4
GND
33
8
HiBW_BypM_LoBW#
MODE
PLL Lo BW
Bypass
Readback
Control
00
Input receiver analog
Digital Power
DIF outputs
0
M
1
00
01
11
11
15,25
21
01
33
PLL Hi BW
11
33
PLL Analog
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
Pin Descriptions
Pin# Pin Name
Type
Pin Description
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2
(Bypass mode) with internal pull up/pull down resistors. See PLL Operating Mode Table for
Details.
LATCHED
IN
1
^vHIBW_BYPM_LOB
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
2
3
4
FB_DNC
FB_DNC#
VDDR3.3
DNC
DNC
PWR
5
6
7
8
9
CLK_IN
CLK_IN#
NC
GNDDIG
SCLK_3.3
IN
IN
N/A
GND
IN
True Input for differential reference clock.
Complementary Input for differential reference clock.
No Connection.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
10 SDATA_3.3
11 VDDDIG3.3
I/O
PWR
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
Active low input for enabling output 0. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
12 vOE0#
IN
13 DIF0
14 DIF0#
15 VDDO3.3
16 NC
OUT
OUT
PWR
N/A
Differential true clock output
Differential Complementary clock output
Power supply for outputs,nominal 3.3V.
No Connection.
17 DIF1
18 DIF1#
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 1. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
19 vOE1#
IN
20 NC
N/A
PWR
OUT
OUT
No Connection.
3.3V power for the PLL core.
Differential true clock output
Differential Complementary clock output
21 VDDA3.3
22 DIF2
23 DIF2#
Active low input for enabling output 2. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
24 vOE2#
IN
25 VDDO3.3
26 NC
PWR
N/A
Power supply for outputs,nominal 3.3V.
No Connection.
27 DIF3
28 DIF3#
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 3. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
No Connection.
29 vOE3#
30 NC
IN
N/A
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal 120kohm pull-up resistor.
31 ^CKPWRGD_PD#
IN
LATCHED Tri-level latch to select SMBus Address. It has an internal 120kohm pull down resistor.
32 vSADR_tri
33 epad
IN
See SMBus Address Selection Table.
connect epad to ground.
GND
NOTE: DNC indicates Do Not Connect anything to this pin.
FEBRUARY 22, 2017
3
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0442 / 9DBL0452 DATASHEET
Test Loads
Terminations
Device
Low-Power Differential Output Test Load
Zo (Ω)
100
100
100
85
Rs (Ω)
None needed
7.5
Prog.
N/A
None needed
Prog.
9DBL0442
9DBL0452
9DBL04P2
9DBL0442
9DBL0452
9DBL04P2
5 inches
Rs
Rs
Zo=100ohm
85
85
2pF
2pF
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
Alternate Terminations
The 9DBL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
4
FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBL0442 / 9DBL0452. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
TYP
MAX
4.6
VDD+0.5
Supply Voltage
Input Voltage
VDDx
VIN
V
V
1,2
1,3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
Human Body Model
3.9
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
2500
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
900
UNITS NOTES
Input Crossover Voltage -
DIF_IN
VCROSS
Cross Over Voltage
150
mV
1
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
IIN
Differential value
Measured differentially
300
0.4
-5
mV
V/ns
uA
1
1,2
8
5
Input Leakage Current
Input Duty Cycle
VIN = VDD , VIN = GND
dtin
Measurement from differential wavefrom
Differential Measurement
45
0
55
125
%
1
1
Input Jitter - Cycle to Cycle
JDIFIn
ps
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics–SMBus Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
VDDSMB = 3.3V
VDDSMB = 3.3V
@ IPULLUP
0.8
3.6
0.4
V
V
2.1
SMBus Output Low Voltage VOLSMB
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
@ VOL
4
mA
V
2.7
3.6
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fSMB
SMBus operating frequency
500
kHz
2,3
1 Guaranteed by design and characterization, not 100% tested in production.
2. The device must be powered up for the SMBus to function.
3.
The differential input clock must be running for the SMBus to be active
FEBRUARY 22, 2017
5
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0442 / 9DBL0452 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
VDDx
CONDITIONS
Supply voltage for core and analog
Industrial range
MIN
3.135
-40
TYP
3.3
25
MAX
3.465
85
UNITS NOTES
Supply Voltage
Ambient Operating
Temperature
V
TAMB
°C
Input High Voltage
VIH
0.75 VDDx
VDDx + 0.3
V
Single-ended inputs, except SMBus
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
VIL
VIHtri
VIMtri
VILtri
IIN
-0.3
0.25 VDDx
VDD + 0.3
V
V
0.75 VDDx
Single-ended tri-level inputs ('_tri' suffix)
0.4 VDDx 0.5 VDDx 0.6 VDDx
V
-0.3
-5
0.25 VDDx
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IN = 0 V; Inputs with internal pull-up resistors
IN = VDD; Inputs with internal pull-down resistors
Bypass mode
uA
Input Current
V
IINP
-50
50
uA
V
1
200
140
65
175
7
MHz
MHz
MHz
MHz
nH
2
2
2
2
1
1
1
1
100MHz PLL mode
60
30
75
100.00
50.00
Input Frequency
FIN
50MHz PLL mode
125MHz PLL mode
125.00
Pin Inductance
Capacitance
Lpin
CIN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
1.5
1.5
5
pF
CINDIF_IN
COUT
2.7
6
pF
pF
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Clk Stabilization
TSTAB
1
ms
1,2
Input SS Modulation
Frequency PCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
fMODINPCIe
30
33
kHz
Input SS Modulation
Frequency non-PCIe
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
fMODIN
tLATOE#
tDRVPD
0
1
66
3
kHz
clocks
us
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
1,3
1,3
300
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
5
ns
ns
2
2
Trise
tR
Rise time of single-ended control inputs
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
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FEBRUARY 22, 2017
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Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
dV/dt
dV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching
2
1.2
2.8
1.9
7
4
3.1
20
1,2,3
1,2,3
1,2,4
Slew rate
Slew rate matching
Voltage High
dV/dt
Δ
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
660
768
-11
850
7
7
mV
Voltage Low
VLOW
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vmax
Vmin
Vcross_abs
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
811
-49
357
14
1150
7
7
1,5
1,6
mV
-300
250
550
140
mV
mV
Crossing Voltage (var)
-Vcross
Scope averaging off
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Δ
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDA
CONDITIONS
MIN
TYP
7
MAX
10
UNITS NOTES
VDDA, PLL Mode @100MHz
VDDDIG, PLL Mode @100MHz
mA
mA
mA
Operating Supply Current
IDDDIG
3.4
5
IDDO+R
VDDO+VDDR, PLL Mode, All outputs @100MHz
VDDA, CKPWRGD_PD# = 0
30.0
0.6
3.1
0.9
37
1.0
4.3
1.3
IDDRPD
IDDDIGPD
IDDAOPD
mA
mA
mA
1
1
1
Powerdown Current
VDDDIG, CKPWRGD_PD# = 0
VDDO+VDDR, CKPWRGD_PD# = 0
1 Input clock stopped.
FEBRUARY 22, 2017
7
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0442 / 9DBL0452 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
-3dB point in High BW Mode (100MHz)
-3dB point in Low BW Mode (100MHz)
Peak Pass band Gain (100MHz)
2
1
3.3
1.5
0.8
4
2
2
MHz
MHz
dB
1,5
1,5
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
Bypass Mode, VT = 50%
45
-1
50
0.0
3406
8
55
1
%
%
1
Duty Cycle Distortion
tDCD
1,3
1
tpdBYP
tpdPLL
tsk3
2500
-100
4500
100
ps
ps
Skew, Input to Output
PLL Mode VT = 50%
1,4
Skew, Output to Output
Jitter, Cycle to cycle
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
21
15
0.1
55
50
1
ps
ps
ps
1,4
1,2
1,2
tjcyc-cyc
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
23
MAX
32
UNITS Notes
ps (p-p) 1,2,3,5
LIMIT
86
tjphPCIeG1-CC
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
ps
0.6
1.7
0.8
3
1,2,5
(rms)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
tjphPCIeG2-CC
Phase Jitter,
PLL Mode
ps
2.1
3.1
1,2,5
(rms)
ps
0.48
0.48
0.01
1
tjphPCIeG3-CC
tjphPCIeG4-CC
tjphPCIeG1-CC
0.4
0.4
0.0
1,2,5
(rms)
ps
(rms)
0.5
1,2,5
ps
PCIe Gen 1
1,2,5
(p-p)
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
PCIe Gen 4
ps
0.0
0.0
0.01
0.01
1,2,4,5
(rms)
tjphPCIeG2-CC
Additive Phase Jitter,
n/a
ps
Bypass mode
1,2,4,5
(rms)
ps
tjphPCIeG3-CC
0.0
0.0
0.01
0.01
1,2,4,5
(rms)
ps
tjphPCIeG4-CC
1,2,4,5
(rms)
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.
5 Driven by 9FGL0841 or equivalent
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
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FEBRUARY 22, 2017
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Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate
Reference Independent Spread (SRIS) Architectures5
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
LIMIT
PARAMETER
SYMBOL
tjphPCIeG2-
CONDITIONS
MIN
TYP
1.2
MAX
1.5
UNITS Notes
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
ps
1,2
2
(rms)
SRIS
Phase Jitter, PLL Mode
tjphPCIeG3-
PCIe Gen 3
ps
0.5
n/a
0.0
0.0
1,2,6
(rms)
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
SRIS
tjphPCIeG2-
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
ps
0.01
1,2,4
(rms)
Additive Phase Jitter,
Bypass mode
SRIS
n/a
tjphPCIeG3-
PCIe Gen 3
ps
0.01
1,2,4,6
(rms)
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
SRIS
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where a is rms input jitter and c is rms total jitter.
5 As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4.
6 This device does not support PCIe Gen3 SRIS in PLL mode. It supports PCIe Gen3 SRIS in bypass mode.
Electrical Characteristics–Unfiltered Phase Jitter Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
tjph156M
CONDITIONS
MIN
TYP
159
MAX
LIMIT
N/A
UNITS Notes
156.25MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
fs
1,2,3
(rms)
Additive Phase Jitter,
Fanout Mode
tjph156M12k-
156.25MHz, 12kHz to 20MHz, -20dB/decade
rollover <12kHz, -40db/decade rolloff > 20MHz
fs
363
N/A
1,2,3
(rms)
20
1Guaranteed by design and characterization, not 100% tested in production.
2
Driven by Rohde&Schartz SMA100
3 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
FEBRUARY 22, 2017
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9DBL0442 / 9DBL0452 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
(H)
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
starT bit
Slave Address
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
T
Slave Address
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus Address is Latched on SADR pin.
Unless otherwise indicated, default values are for the
xx42 and xx52. P2 devices are fully factory
programmable.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
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FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Output Enable
Reserved
Output Enable
Output Enable
Reserved
Output Enable
Reserved
Type
0
1
Default
0
1
0
1
1
0
1
0
DIF OE3
RW
Pin Control
DIF OE2
DIF OE1
RW
RW
Pin Control
Pin Control
See B11[1:0]
DIF OE0
RW
Pin Control
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Name
PLLMODERB1
PLLMODERB0
Control Function
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
Type
R
R
0
1
Default
Latch
Latch
See PLL Operating Mode Table
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
0
Bit 5
RW1
RW1
PLLMODE1
PLLMODE0
PLL Mode Control Bit 1
0
0
1
1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See PLL Operating Mode Table
PLL Mode Control Bit 0
Reserved
RW
Controls Output Amplitude
RW
AMPLITUDE 1
AMPLITUDE 0
00 = 0.6V
10 = 0.75V
01= 0.68V
11 = 0.85V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Slew rate selection
Reserved
Slew rate selection
Slew rate selection
Reserved
Slew rate selection
Reserved
Type
0
1
Default
1
1
1
1
1
1
1
1
SLEWRATESEL DIF3
RW
Slow Setting
Fast Setting
SLEWRATESEL DIF2
SLEWRATESEL DIF1
RW
RW
Slow Setting
Slow Setting
Fast Setting
Fast Setting
SLEWRATESEL DIF0
RW
Slow Setting
Fast Setting
Note: See "Low-Power HCSL Outputs" table for slew rates.
SMBus Table: Slew Rate Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Reserved
Reserved
Enable SW selection of
frequency
Type
0
1
Default
1
1
SW frequency
change disabled
SW frequency
change enabled
FREQ_SEL_EN
RW
0
Bit 5
RW1
RW1
00 = 100M, 10 = 125M
01 = 50M, 11= Reserved
FSEL1
FSEL0
Freq. Select Bit 1
0
Bit 4
Freq. Select Bit 0
Reserved
Reserved
Adjust Slew Rate of FB
0
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
RW
Slow Setting
Fast Setting
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Byte 4 is Reserved
FEBRUARY 22, 2017
11
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0442 / 9DBL0452 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
1
0
0
0
1
Revision ID
B rev = 0000
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
0
1
0
0
0
1
0
0
Device Type
Device ID
000110binary or 04 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
Bytes 8 and 9 are Reserved
SMBus Table: PD_Restore
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
1
1
0
0
0
0
0
0
Power-Down (PD) Restore
Restore Default Config. In PD
Reserved
RW Clear Config in PD Keep Config in PD
Reserved
Reserved
Reserved
Reserved
Reserved
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FEBRUARY 22, 2017
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SMBus Table: Stop State and Impedance Control
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FB_imp[1]
FB_imp[0]
Control Function
FB Zout
Type
RW
RW
0
1
Default
00=33Ω DIF Zout 10=100Ω DIF Zout
01=85Ω DIF Zout
see Note
FB Zout
11 = Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
Reserved
STP[1]
STP[0]
True/Complement DIF Output
Disable State
RW
RW
00 = Low/Low
01 = HiZ/HiZ
10 = High/Low
11 = Low/High
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Impedance Control
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DIF1_imp[1]
DIF1_imp[0]
Control Function
Type
RW
RW
0
1
Default
00=33Ω DIF Zout 10=100Ω DIF Zout
01=85Ω DIF Zout 11 = Reserved
DIF3 Zout
Reserved
Reserved
see Note
DIF0_imp[1]
DIF1_imp[0]
RW
RW
00=33Ω DIF Zout 10=100Ω DIF Zout
01=85Ω DIF Zout
DIF1 Zout
11 = Reserved
Reserved
Reserved
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Impedance Control
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
DIF3_imp[1]
DIF3_imp[0]
DIF6 Zout
DIF6 Zout
RW
RW
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
11 = Reserved
see Note
Reserved
Reserved
DIF2_imp[1]
DIF2_imp[0]
DIF4 Zout
DIF4 Zout
RW
RW
00=33 DIF Zout 10=100 DIF Zout
01=85 DIF Zout
11 = Reserved
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Pull-up Pull-down Control
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
OE1_pu/pd[1]
OE1_pu/pd[0]
Control Function
Type
RW
RW
0
1
Default
OE3 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
0
1
0
1
0
1
0
1
Reserved
OE0_pu/pd[1]
OE0_pu/pd[0]
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
RW
RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
Reserved
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
FEBRUARY 22, 2017
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SMBus Table: Pull-up Pull-down Control
Byte 15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Reserved
OE6 Pull-up(PuP)/
Type
0
1
Default
0
1
0
1
0
1
0
1
OE3_pu/pd[1]
OE3_pu/pd[0]
RW
RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
Pull-down(Pdwn) control
Reserved
Reserved
OE2_pu/pd[1]
OE2_pu/pd[0]
OE4 Pull-up(PuP)/
Pull-down(Pdwn) control
RW
RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
SMBus Table: Pull-up Pull-down Control
Byte 16
Bit 7
Bit 6
Bit 5
Bit 4
Name
Control Function
Reserved
Type
0
1
Default
X
X
X
X
Reserved
Reserved
Reserved
HIBW_BYPM_LOBWpu/pd[1]
HIBW_BYPM_LOBWpu/pd[0]
HIBW_BYPM_LOBW
Pull-up(PuP)/
Pull-down(Pdwn) control
RW
RW
00=None
01=Pdwn
10=Pup
1
1
Bit 3
Bit 2
11 = Pup+Pdwn
CKPWRGD_PD_pu/pd[1]
CKPWRGD_PD_pu/pd[0]
CKPWRGD_PD Pull-up(PuP)/ RW
00=None
01=Pdwn
10=Pup
11 = Pup+Pdwn
1
0
Bit 1
Bit 0
Pull-down(Pdwn) control
RW
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
Bytes 17 is Reserved
SMBus Table: Polarity Control
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Sets OE6 polarity
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
OE3_polarity
RW Enabled when Low Enabled when High
OE2_polarity
OE1_polarity
Sets OE4 polarity
Sets OE3 polarity
Reserved
Sets OE1 polarity
Reserved
RW Enabled when Low Enabled when High
RW Enabled when Low Enabled when High
OE0_polarity
RW Enabled when Low Enabled when High
SMBus Table: Polarity Control
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Control Function
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Determines
CKPWRGD_PD polarity
Power Down when Power Down when
Low High
CKPWRGD_PD
RW
0
Bit 0
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FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
Marking Diagrams
ICS
L0442BIL
YYWW
COO
ICS
L0452BIL
YYWW
COO
ICS
4P2B000I
YYWW
COO
LOT
LOT
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. “YYWW” is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “I” denotes industrial temperature range device.
Thermal Characteristics
TYP
VALUE
42
PARAMETER
SYMBOL
CONDITIONS
PKG
UNITS NOTES
C/W
C/W
Junction to Case
Junction to Base
°
1
1
1
1
1
1
θJC
θJb
θJA0
θJA1
θJA3
θJA5
2.4
39
33
28
27
°
C/W
°
Junction to Air, still air
Thermal Resistance
NLG32
C/W
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
°
°
°
C/W
C/W
1ePad soldered to board
FEBRUARY 22, 2017
15
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9DBL0442 / 9DBL0452 DATASHEET
Package Outline and Dimensions (NLG32)
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
16
FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
Package Outline and Dimensions (NLG32), cont.
FEBRUARY 22, 2017
17
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9DBL0442 / 9DBL0452 DATASHEET
Ordering Information
Part / Order Number
9DBL0442BKILF
9DBL0442BKILFT
9DBL0452BKILF
Notes
Shipping Packaging
Trays
Package
Temperature
32-pin VFQFPN -40 to +85° C
32-pin VFQFPN -40 to +85° C
32-pin VFQFPN -40 to +85° C
32-pin VFQFPN -40 to +85° C
100Ω
Tape and Reel
Trays
Tape and Reel
85Ω
9DBL0452BKILFT
Factory configurable.
Contact IDT for
addtional information.
9DBL04P2BxxxKILF
9DBL04P2BxxxKILFT
Trays
32-pin VFQFPN -40 to +85° C
32-pin VFQFPN -40 to +85° C
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
“xxx” is a unique factory assigned number to identify a particular default configuration.
Revision History
Rev. Initiator Issue Date Description
Page #
1. Add PCIe G1-4 Common Clock and PCIe SRIS to electrical tables
2. Update Electrical Tables to final
3. Changed '1' value in Byte 0 to indicate "Pin Control"
4. Stylistic update to block diagram
A
RDW
5/31/2016
Various
5. Minor updates to SMBus registers 0 and 1 for Readability
6. Front page text update for family consistency.
7. Removed '000' code from ordering information, updated table.
8. Minor corrections to Byte 1 [1:0] and Byte 11 [1:0]
1. Electrical Table and SMBus Updates/Corrections
2. Release to final.
B
C
D
RDW
RDW
6/14/2016
Various
5
6/21/2016 1. Updated ESD from 2000V to 2500V
1. Corrected pin 32 to indicate an internal pull down resistor, not a pull up
resistor.
2/8/2017 Renamed datasheet to 9DBL0442 / 9DBL0452
RDW 11/11/2016
2, 3
E
F
RDW
RDW
Various
2/22/2017 Replaced POD drawing from P3 [3.10 EPAD] to P1 [3.15 EPAD] option. 16, 17
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
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FEBRUARY 22, 2017
Corporate Headquarters
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San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
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Fax: 408-284-2775
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
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