9DB801BFLF [IDT]
SSOP-48, Tube;
| 型号： | 9DB801BFLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SSOP-48, Tube 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总20页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9DB801
Systems, Inc.
Eight Output Differential Buffer for PCI Express (50-200MHz)
Recommended Application:
Pin Configurations
DB800 Version 2.0 Yellow Cover part with PCI Express
suppor with extended bypass mode frequency range.
SRC_DIV#
VDD
1
2
48 VDDA
47 GNDA
GND
3
4
5
6
7
8
9
10
11
12
13
46
IREF
Output Features:
SRC_IN
SRC_IN#
OE_0
45 LOCK
44 OE_7
43 OE_4
•
•
•
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
42
41
40
OE_3
DIF_7
DIF_7#
OE_INV
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1 14
OE_2 15
DIF_2
DIF_2#
GND
VDD
Key Specifications:
39 VDD
38
37
DIF_6
DIF_6#
•
•
•
•
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
50 - 200MHz operation
Extended frequency range in bypass mode:
Revision B: up tp 333.33 MHz
Revision C: up to 400 MHz
36 OE_6
35 OE_5
34
33
DIF_5
DIF_5#
16
17
18
19
20
21
22
23
24
32 GND
31 VDD
30
29
DIF_4
DIF_4#
Features/Benefits:
DIF_3
DIF_3#
28 HIGH_BW#
27 SRC_STOP#
26 PD#
•
•
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
BYPASS#/PLL
SCLK
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
25 GND
SDATA
OE_INV = 0
Supports polarity inversion to the output enables ,
SRC_STOP and PD.
SRC_DIV#
VDD
1
2
48 VDDA
47 GNDA
GND
3
4
5
6
7
8
9
10
11
12
13
46
IREF
Polarity Inversion Pin List Table
SRC_IN
SRC_IN#
OE0#
45 LOCK
44 OE7#
43 OE4#
OE_INV
Pins
6
0
OE_0
1
OE0#
OE3#
OE1#
OE2#
PD
42
41
40
OE3#
DIF_7
DIF_7#
OE_INV
7
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1# 14
OE2# 15
DIF_2
DIF_2#
GND
VDD
14
15
26
27
35
36
43
44
OE_1
39 VDD
OE_2
38
37
DIF_6
DIF_6#
PD#
SRC_STOP#
OE_5
SRC_STOP
OE5#
OE6#
OE4#
OE7#
36 OE6#
35 OE5#
OE_6
34
33
DIF_5
DIF_5#
OE_4
16
17
18
19
20
21
22
23
24
OE_7
32 GND
31 VDD
30
29
DIF_4
DIF_4#
DIF_3
DIF_3#
28 HIGH_BW#
27 SRC_STOP
26 PD
BYPASS#/PLL
SCLK
25 GND
SDATA
OE_INV = 1
48-pin SSOP & TSSOP
1015B—09/07/06
Integrated
Circuit
ICS9DB801
Systems, Inc.
Pin Desription for OE_INV = 0
PIN
PIN # PIN NAME
TYPE
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
SRC/2.
1
SRC_DIV#
IN
0 = SRC/2, 1= SRC
2
3
4
5
VDD
GND
SRC_IN
SRC_IN#
PWR
PWR
IN
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
IN
6
7
OE_0
OE_3
IN
IN
8
9
DIF_0
DIF_0#
OUT
OUT
PWR
PWR
OUT
OUT
10 GND
11 VDD
12 DIF_1
13 DIF_1#
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
14 OE_1
15 OE_2
IN
IN
16 DIF_2
17 DIF_2#
18 GND
19 VDD
20 DIF_3
21 DIF_3#
OUT
OUT
PWR
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
22 BYPASS#/PLL
IN
23 SCLK
24 SDATA
IN
I/O
1015B—09/07/06
2
Integrated
Circuit
ICS9DB801
Systems, Inc.
Pin Desription for OE_INV = 0
PIN
PIN # PIN NAME
TYPE
DESCRIPTION
25 GND
PWR
Ground pin.
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
26 PD#
IN
27 SRC_STOP#
28 HIGH_BW#
IN
IN
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
29 DIF_4#
30 DIF_4
31 VDD
32 GND
33 DIF_5#
34 DIF_5
OUT
OUT
PWR
PWR
OUT
OUT
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
35 OE_5
36 OE_6
IN
IN
37 DIF_6#
38 DIF_6
39 VDD
OUT
OUT
PWR
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
40 OE_INV
IN
41 DIF_7#
42 DIF_7
OUT
OUT
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
43 OE_4
44 OE_7
45 LOCK
IN
IN
OUT
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
46 IREF
IN
47 GNDA
48 VDDA
PWR
PWR
3.3V power for the PLL core.
1015B—09/07/06
3
Integrated
Circuit
ICS9DB801
Systems, Inc.
Pin Desription for OE_INV = 1
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
SRC/2.
1
SRC_DIV#
IN
0 = SRC/2, 1= SRC
2
3
4
5
VDD
GND
SRC_IN
SRC_IN#
PWR
PWR
IN
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
IN
6
7
OE0#
OE3#
IN
IN
8
9
DIF_0
DIF_0#
OUT
OUT
PWR
PWR
OUT
OUT
10 GND
11 VDD
12 DIF_1
13 DIF_1#
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
14 OE1#
15 OE2#
IN
IN
16 DIF_2
17 DIF_2#
18 GND
19 VDD
20 DIF_3
21 DIF_3#
OUT
OUT
PWR
PWR
OUT
OUT
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
22 BYPASS#/PLL
IN
23 SCLK
24 SDATA
IN
I/O
1015B—09/07/06
4
Integrated
Circuit
ICS9DB801
Systems, Inc.
Pin Desription for OE_INV = 1
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25 GND
PWR
Ground pin.
Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is stopped.
26 PD
IN
27 SRC_STOP
28 HIGH_BW#
IN
IN
Active high input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
29 DIF_4#
30 DIF_4
31 VDD
32 GND
33 DIF_5#
34 DIF_5
OUT
OUT
PWR
PWR
OUT
OUT
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
35 OE5#
36 OE6#
IN
IN
37 DIF_6#
38 DIF_6
39 VDD
OUT
OUT
PWR
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
40 OE_INV
IN
41 DIF_7#
42 DIF_7
OUT
OUT
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when
43 OE4#
44 OE7#
45 LOCK
IN
IN
OUT
lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
46 IREF
IN
47 GNDA
48 VDDA
PWR
PWR
3.3V power for the PLL core.
1015B—09/07/06
5
Integrated
Circuit
ICS9DB801
Systems, Inc.
General Description
The ICS9DB801 follows the Intel DB800 Differential Buffer Specification v2.0. This buffer provides eight PCI-Express SRC
clocks. The ICS9DB801 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the
ICS952601 or ICS954101. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps)
requirements.
Block Diagram
8
OE_(7:0)
SPREAD
COMPATIBLE
PLL
SRC_IN
SRC_IN#
M
U
X
8
STOP
LOGIC
DIF(7:0))
SRC_STOP#
HIGH_BW#
CONTROL
LOGIC
BYPASS#/PLL
PD#
IREF
SDATA
SCLK
LOCK
Note: Polarities shown for OE_INV = 0.
1015B—09/07/06
6
Integrated
Circuit
ICS9DB801
Systems, Inc.
Absolute Max
Symbol
VDD_A
VDD_In
VIL
Parameter
Min
Max
4.6
4.6
Units
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
V
V
V
GND-0.5
VIH
Input High Voltage
VDD+0.5V
V
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
°C
°C
°C
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
DD + 0.3
0.8
UNITS NOTES
VIH
VIL
IIH
V
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
2
GND - 0.3
-5
V
V
uA
5
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
-5
uA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
IDD3.3PLL
IDD3.3ByPass
175
160
50
200
175
70
4
200
mA
mA
mA
mA
MHz
Full Active, CL = Full load;
Operating Supply Current
all diff pairs driven
all differential pairs tri-stated
PLL Mode
IDD3.3PD
FiPLL
Powerdown Current
Input Frequency
Input Frequency
1
50
0
Bypass Mode (Revision B/REV
FiBypass
333.33
400
MHz
MHz
ID = 1H)
Bypass Mode (Revision C/REV
ID = 2H)
FiBypass
Input Frequency
Pin Inductance1
0
Lpin
CIN
COUT
7
4
4
nH
pF
pF
1
1
1
Logic Inputs
1.5
Input Capacitance1
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
2.4
0.7
3
1
3.4
1.4
MHz
MHz
1
1
PLL Bandwidth
BW
PLL Bandwidth when
PLL_BW=1
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
Clk Stabilization1,2
TSTAB
0.5
10
1
ms
1,2
Modulation Frequency
Tdrive_SRC_STOP#
fMOD
Triangular Modulation
DIF output enable after
SRC_Stop# de-assertion
DIF output enable after
PD# de-assertion
30
33
15
kHz
ns
1
1,3
Tdrive_PD#
Tfall
300
5
us
ns
ns
1,3
1
Fall time of PD# and
SRC_STOP#
Rise time of PD# and
SRC_STOP#
Trise
5
2
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3Time from deassertion until outputs are >200 mV
1015B—09/07/06
7
Integrated
Circuit
ICS9DB801
Systems, Inc.
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
850
UNITS NOTES
VO = Vx
3000
1
Ω
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1,3
1,3
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
1
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
tr
tf
d-tr
d-tf
see Tperiod min-max values
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
0
ppm
ps
ps
ps
ps
1,2
1
1
1
1
175
175
700
700
125
125
Measurement from differential
wavefrom
dt3
Duty Cycle
Skew
45
55
50
%
1
1
tsk3
VT = 50%
ps
PLL mode,
Measurement from differential
wavefrom
BYPASS mode as additive jitter
50
50
ps
ps
1
1
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
1015B—09/07/06
8
Integrated
Circuit
ICS9DB801
Systems, Inc.
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, Route as non -coupled 50 ohm trace.
Dimension or Value
Unit
inch
inch
inch
ohm
ohm
Figure
2, 3
2, 3
2, 3
2, 3
2, 3
0.5 max
0.2 max
0.2 max
33
L2 length, Route as non
-coupled 50 ohm trace.
-coupled 50 ohm trace.
L3 length, Route as non
Rs
Rt
49.9
Down Device Differential Routing
Dimension or Value
2 min to 16 max
Unit
inch
Figure
L4 length, Route as coupled
microstrip 100 ohm
2
2
differential trace.
L4 length, Route as coup
differential trace.
led stripline 100 ohm
1.8 min to 14.4 max
inch
Differential Routing to PCI Express Connector
Dimension or Value
0.25 to 14 max
Unit
inch
Figure
L4 length, Route as coupled
differential trace.
microstrip 100 ohm
3
3
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
0.225 min to 12.6
max
inch
L1
L2
L4
L4’
Rs
L1’
L2’
Rs
Rt
Rt
Fig.1
HSCL Output
Buffer
PCI Ex
REF_CLK
Test Load
L3’
L3
L1
L2
L4
Rs
Rs
L4’
L1’
L2’
Fig.2
Rt
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
L3’
L3
REF_CLK Input
L1
L2
L4
L4’
Rs
Rs
L1’
L2’
Rt
Rt
Fig.3
HSCL Output
Buffer
PCI Ex
Add In Board
REF_CLK Input
L3’
L3
1015B—09/07/06
9
Integrated
Circuit
ICS9DB801
Systems, Inc.
General SMBus serial interface information for the ICS9DB801
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
s t arT bi t
T
s t arT bi t
T
S l ave A ddres s DC
S l ave A ddres s DC
( H )
( H )
R
Ri t e
R
Ri t e
A CK
A CK
A CK
A CK
A CK
A CK
B egi nni ng B y t e
N
B egi nni ng B y t e
Dat a B y t e Cou nt
B egi nni ng B y t e N
N
RT
R D
R
e
p
e
a
t
s
t
a
r
T
S
l
a
v
e
A
d
d
r
e
s
s
D
D
(
H
)
R
e
a
D
A
C
K
Dat a B y t e Co un t
B egi nni n g B y t e N
A CK
A CK
B
y
t
e
N
- 1
s t o P b i t
A
C
K
P
B
y
t
e
N
-
1
N
P
Not ac k nowl edge
s t oP bi t
1015B—09/07/06
10
Integrated
Circuit
ICS9DB801
Systems, Inc.
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Pin #
Name
PD_Mode
Control Function
PD# drive mode
Type
RW
0
1
Hi-Z
Hi-Z
PWD
-
-
-
-
-
-
-
-
driven
driven
0
0
X
X
X
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STOP_Mode SRC_Stop# drive mode RW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLL_BW#
BYPASS#
SRC_DIV#
Reserved
Reserved
Reserved
RW
RW
RW
Select PLL BW
BYPASS#/PLL
SRC Divide by 2 Select RW
RW High BW Low BW
RW fan-out
ZDB
1x
x/2
SMBus Table: Output Control Register
Byte 1
Bit 7
Pin #
42,41
Name
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
0
1
PWD
RW Disable
RW Disable
RW Disable
RW Disable
RW Disable
RW Disable
RW Disable
RW Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
38,37
34,33
30,29
20,21
16,17
12,13
8,9
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Output Control Register
Byte 2
Bit 7
Pin #
42,41
Name
DIF_7
Control Function
Output Control
Type
0
1
PWD
0
RW Free-run Stoppable
38,37
34,33
Bit 6
Bit 5
DIF_6
DIF_5
Output Control
Output Control
RW Free-run Stoppable
0
0
RW Free-run Stoppable
30,29
20,21
Bit 4
Bit 3
DIF_4
DIF_3
Output Control
Output Control
RW Free-run Stoppable
RW Free-run Stoppable
0
0
16,17
Bit 2
DIF_2
Output Control
RW Free-run Stoppable
0
12,13
8,9
Bit 1
Bit 0
DIF_1
DIF_0
Output Control
Output Control
RW Free-run Stoppable
RW Free-run Stoppable
0
0
1015B—09/07/06
11
Integrated
Circuit
ICS9DB801
Systems, Inc.
SMBus Table: Output Control Register
Byte 3
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Vendor & Revision ID Register
Byte 4
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
PWD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
SMBus Table: DEVICE ID
Byte 5 Pin # Name
Bit 7
Control Function
Device ID 7 (MSB)
Type
R
R
0
1
PWD
1
0
-
-
Reserved
Reserved
Device ID 6
Bit 6
-
-
-
-
Device ID 5
Reserved
R
R
R
R
0
0
0
0
Bit 5
Device ID 4
Device ID 3
Device ID 2
Reserved
Reserved
Reserved
Bit 4
Bit 3
Bit 2
-
-
Device ID 1
Device ID 0
R
R
Reserved
Reserved
0
1
Bit 1
Bit 0
SMBus Table: Byte Count Register
Control
Function
Byte 6
Bit 7
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
configures how many
bytes will be read back.
1015B—09/07/06
12
Integrated
Circuit
ICS9DB801
Systems, Inc.
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
Tstable
<1mS
PWRDWN#
DIF
DIF#
Tdrive_PwrDwn#
<300uS, >200mV
1015B—09/07/06
13
Integrated
Circuit
ICS9DB801
Systems, Inc.
SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1015B—09/07/06
14
Integrated
Circuit
ICS9DB801
Systems, Inc.
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
1mS
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1015B—09/07/06
15
Integrated
Circuit
ICS9DB801
Systems, Inc.
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
- C -
VARIATIONS
D mm.
D (inch)
e
SEEAATTIINNGG
PLANE
N
b
MIN
15.75
MAX
16.00
MIN
.620
MAX
.10 (.004)
C
48
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9DB801yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
1015B—09/07/06
16
Integrated
Circuit
ICS9DB801
Systems, Inc.
c
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
In Millimeters
COMMON DIMENSIONS
N
In Inches
COMMON DIMENSIONS
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
SEE VARIATIONS
0.319 BASIC
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
c
D
INDEX
AREA
1
2
SEE VARIATIONS
8.10 BASIC
E
a
E1
e
L
6.00
0.50 BASIC
0.45
6.20
.236
.244
0.020 BASIC
.030
SEE VARIATIONS
D
0.75
.018
N
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
b
48
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9DB801yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
1015B—09/07/06
17
Integrated
Circuit
ICS9DB801
Systems, Inc.
Revision History
Rev. Issue Date Description
Page #
1. Updated Operating Supply Current Spec from Input/Supply/Common
Output Parameters table.
0.10
4/4/2005 2. Updated Ordering Information from "Lead Free" to "Annealed Lead Free".
7,16-17
1, 7
1. Updated Min/Max BW spec
2. Added 50-200MHz nomenclature to data sheet to indicate B rev limits
4/8/2005 3. Released
0.20
A
4/8/2005 Release to Final
1. Added Polarity Table.
2. Updated Electrical Characteristics.
3. Updated LF Ordering Information from "Annealed Lead Free" to "RoHS
9/7/2006 Compliant".
1, 7,
16-17
B
1015B—09/07/06
18
Se a rch En t i re Si t e
Co n t a ct I DT | I n ve st o rs | Pre ss
Do c u me n t Se a r c h | Pa c ka g e Se a r c h | Pa r a me t r ic Se a r c h | Cr o s s Re f e r e n c e Se a r c h | Gr e e n & Ro HS | Ca lc u la t o r s | Th e r ma l Da t a | Re lia b ilit y & Qu a lit y | Milit a r y
A d d t o m y I DT [ ?] Ho m e > Pro d u ct s > T i m i n g So l u t i o n s > PC-No t e b o o k-Se rve r Cl o cks > PCI e / HCSL Bu f f e rs a n d Ge n e ra t o rs > 9 DB8 0 1
9DB801 (PCIe /HCSL Buffe rs and Ge ne rators)
De s c r ipt ion
D
B
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f
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fo r PC I Exp r e s s ( 5 0 - 2 0 0 MH z)
M a r k e t Gr oup
PC C L OC K
Addit iona l Inf o
D
B8
0
0
Ve
r
s
i
o
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2
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Ye
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/T
S
S
O
P
Yo u m a y a l so l i ke . . .
Re la t e d Or de r a ble Pa r t s
2
1
Attr i b u te s
Volt a ge
9 D B8 0 1 BFL F
9 D B8 0 1 BFL FT
9 D B8 0 1 BGL F
9 D B8 0 1 BGL FT
9 D B8 0 1 C FL F
9 D B8 0 1 C GL F
3 .3 V ( PVG4 8 )
3 .3 V ( PVG4 8 )
3 .3 V ( PAG4 8 )
3 .3 V ( PAG4 8 )
3 .3 V ( PVG4 8 )
3 .3 V ( PAG4 8 )
Pa c k a ge
Spe e d
SSOP 4 8
N A
SSOP 4 8
N A
TSSOP 4 8
N A
TSSOP 4 8
SSOP 4 8
N A
TSSOP 4 8
N A
N A
C
Te m pe r a t ur e
St a t us
C
C
C
C
C
Ac ti ve
Ye s
Ac ti ve
N o
Ac ti ve
Ye s
Acti ve
N o
Ac ti ve
Ye s
Ac ti ve
Ye s
Sa m ple
M inim um Or de r
Qua nt it y
1 8 0
3 0
1 0 0 0
1 0 0 0
1 5 2
3 8
1 0 0 0
1 0 0 0
1 8 0
3 0
1 5 2
3 8
Fa c t or y Or de r
Inc r e m e nt
2
1
Re la t e d Doc um e nt s
Typ e
Ti tl e
Si ze
R e vi s i o n D a te
D a ta s h e e t
9 D B8 0 1 D a ta s h e e t
9 D B8 0 1 IBIS Mo d e l
PC N # : TB- 0 5 1 0 - 0 5 N e w Sh i p p i n g Tu b e fo r TSSOP/TVSOP/TSSOP Exp o s e d
2 0 1 KB 0 5 /2 1 /2 0 0 7
1 0 4 KB 0 3 /2 7 /2 0 0 6
2 0 2 KB 1 2 /1 3 /2 0 0 5
Mo d e l - IBIS
Pr o d u c t C h a n g e N o ti c e
Ho m e | Si t e M a p | Ab o u t I DT | Pre ss Ro o m | I n ve st o r Re l a t i o n s | T ra d e m a rk | Pri va cy Po l i cy | Ca re e rs | Re g i st e r | Co n t a ct Us
Use o f t h i s we b si t e si g n i f i e s yo u r a g re e m e n t t o t h e a cce p t a b l e u se a n d p ri va cy p o l i cy. Co p yri g h t 1 9 9 7 -2 0 0 7 I n t e g ra t e d De vi ce T e ch n o l o g y, I n c. Al l Ri g h t s Re se rve d .
N o d e : w w w .i d t.c o m
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