954226 [IDT]
Programmable Timing Control HubTM for Mobile P4TM Systems; 可编程定时控制HubTM移动P4TM系统
| 型号： | 954226 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Programmable Timing Control HubTM for Mobile P4TM Systems |
| 文件： | 总22页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Programmable Timing Control HubTM for Mobile P4TM
Systems
954226
Key Specifications:
Recommended Application:
CK410M Compatible Main Clock
•
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
PCI Express outputs cycle-cycle jitter < 125ps
SATA outputs cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 500ps
+/- 300ppm frequency accuracy on CPU, PCI Express
and SATA clocks
+/- 100ppm frequency accuracy on USB clocks
Output Features:
•
•
•
2 - 0.7V current-mode differential CPU pairs
4 - 0.7V current-mode differential PCI Express* pairs
1 - 0.7V current-mode differential CPU/PCI Express
selectable pair
•
Features/Benefits:
•
•
•
1 - 0.7V current-mode differential SATA pair
1 - 0.7V current-mode differential LCDCLK/PCI Express
selectable pair
Supports tight ppm accuracy clocks for Serial-ATA and
PCI Express
Supports programmable spread percentage and
frequency
•
•
•
•
•
•
4 - PCI (33MHz)
2 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
2 - REF, 14.318MHz
•
•
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, PCI Express pair
in PD for power management.
PEREQ# pins to support PCI Express and SATA power
management.
MLF Pin Configuration
TSSOP Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
56 PCICLK2/REQ_SEL**
55 PCI/SRC_STOP#
54 CPU_STOP#
53 REF1/FSLC/TEST_SEL
PCICLK5 5
52 REF0
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
**SELPCIEX_LCDCLK#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
45 GND
44 CPUCLKT0
43 CPUCLKC0
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
38 GNDA
37 VDDA
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VDDPCI
ITP_EN/PCICLK_F0
1
2
3
42 VDDREF
41 SDATA
40 SCLK
**SELPCIEX_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
VDD48
4
5
6
7
8
9
39 GND
VDD48 11
FSLA/USB_48MHz 12
38 CPUCLKT0
37 CPUCLKC0
36 VDDCPU
35 CPUCLKT1
34 CPUCLKC1
33 IREF
FSLA/USB_48MHz
GND
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
ICS 954226AKLF
DOTT_96MHz
DOTC_96MHz
FSLB/TEST_MODE 16
LCDCLK_SS/PCIEX0T 17
LCDCLK_SS/PCIEX0C 18
PCIEXT1 19
FSLB/TEST_MODE 10
LCDCLK_SS/PCIEXT0 11
LCDCLK_SS/PCIEXC0 12
PCIEXT1 13
32 GNDA
31 VDDA
PCIEXC1 20
VDDPCIEX 21
PCIEXT2 22
30 CPUCLKT2_ITP/PCIEXT6
29 CPUCLKC2_ITP/PCIEXC6
36 CPUCLKT2_ITP/PCIEXT6
35 CPUCLKC2_ITP/PCIEXC6
34 VDDPCIEX
PCIEXC1 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
PCIEXC2 23
PCIEXT3 24
PCIEXC3 25
SATACLKT 26
SATACLKC 27
VDDPCIEX 28
33 PEREQ1#*/PCIEXT5
32 PEREQ2#*/PCIEXC5
31 PCIEXT4
30 PCIEXC4
29 GND
56-TSSOP
56-MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Table 1: Frequency Selection Table
FSLC B6b2 FSLB B6b1 FSLA B6b0
CPU
MHz
PCIEX
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
Spread %
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66 100.00 33.33 14.318
133.33 100.00 33.33 14.318
200.00 100.00 33.33 14.318
166.66 100.00 33.33 14.318
333.33 100.00 33.33 14.318
100.00 100.00 33.33 14.318
400.00 100.00 33.33 14.318
200.00 100.00 33.33 14.318
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
1
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
TSSOP Pin Description
PIN #
PIN NAME
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
1
2
3
4
5
6
7
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
VDDPCI
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
8
9
ITP_EN/PCICLK_F0
I/O
I/O
IN
0 = PCIEX_6 pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
**SELPCIEX_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
10
11
12
VDD48
PWR
I/O
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
FSLA/USB_48MHz
13
14
15
GND
PWR
OUT
OUT
Ground pin.
DOTT_96MHz
DOTC_96MHz
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
16
FSLB/TEST_MODE
IN
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
17
18
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
OUT
OUT
19
20
21
22
23
24
25
26
27
28
PCIEXT1
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PCIEXC1
VDDPCIEX
PCIEXT2
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
2
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
TSSOP Pin Description (cont.)
PIN #
29
PIN NAME
TYPE
PWR
OUT
OUT
DESCRIPTION
GND
Ground pin.
30
PCIEXC4
PCIEXT4
Complement clock of differential PCI_Express pair.
31
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
32
PEREQ2#*/PCIEXC5
I/O
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
Power supply for PCI Express clocks, nominal 3.3V
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
33
34
35
PEREQ1#*/PCIEXT5
VDDPCIEX
I/O
PWR
OUT
CPUCLKC2_ITP/PCIEXC6
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
36
CPUCLKT2_ITP/PCIEXT6
OUT
37
38
VDDA
GNDA
PWR
PWR
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
39
40
IREF
OUT
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
CPUCLKC1
41
42
43
CPUCLKT1
VDDCPU
OUT
PWR
OUT
CPUCLKC0
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
PWR
IN
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
I/O
PWR
OUT
IN
X1
GND
REF0
PWR
OUT
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
53
REF1/FSLC/TEST_SEL
I/O
54
55
CPU_STOP#
IN
IN
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
PCI/SRC_STOP#
56
PCICLK2/REQ_SEL**
I/O
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
3
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
MLF Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
2
3
4
ITP_EN/PCICLK_F0
I/O
I/O
IN
0 = SRC pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
**SELPCIEX_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
5
6
7
VDD48
PWR
I/O
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
FSLA/USB_48MHz
GND
PWR
Ground pin.
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
8
9
DOTT_96MHz
OUT
OUT
IN
0 = PCIEX_6 pair
DOTC_96MHz
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
10
FSLB/TEST_MODE
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
11
12
LCDCLK_SS/PCIEXT0
LCDCLK_SS/PCIEXC0
OUT
OUT
13
14
15
16
17
18
19
20
21
22
23
24
25
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
GND
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin.
PCIEXC4
PCIEXT4
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
26
PEREQ2#*/PCIEXC5
I/O
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
27
28
PEREQ1#*/PCIEXT5
VDDPCIEX
I/O
PWR
Power supply for PCI Express clocks, nominal 3.3V
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
4
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
29
CPUCLKC2_ITP/PCIEXC6
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
30
CPUCLKT2_ITP/PCIEXT6
OUT
31
32
VDDA
GNDA
PWR
PWR
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
33
34
IREF
OUT
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
CPUCLKC1
35
36
37
CPUCLKT1
VDDCPU
OUT
PWR
OUT
CPUCLKC0
38
CPUCLKT0
OUT
39
40
41
42
43
44
45
46
GND
SCLK
SDATA
VDDREF
X2
PWR
IN
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
I/O
PWR
OUT
IN
X1
GND
REF0
PWR
OUT
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
47
REF1/FSLC/TEST_SEL
I/O
48
49
CPU_STOP#
IN
IN
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
PCI/SRC_STOP#
50
PCICLK2/REQ_SEL**
I/O
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
51
52
53
54
55
56
VDDPCI
GND
PWR
PWR
OUT
OUT
OUT
PWR
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCICLK3
PCICLK4
PCICLK5
GND
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
5
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
General Description
The ICS954226 is a CK410M compatible clock synthesizer. It provides a single-chip solution for mobile systems built with
Intel P4-M processors and Intel mobile chipsets. The device is driven with a 14.318MHz crystal and generates CPU outputs
up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI Express.
Block Diagram
REF(1:0)
USB_48MHz
X1
XTAL
OSC.
FIXED PLL
DIVIDER
X2
DOT_96MHz
PCICLK(5:2)
PCICLK_F(1:0)
PCIEX(5:1)
PROG.
SPREAD
MAIN PLL
PROG.
DIVIDERS
CPUCLK2/PCIEX6
CPUCLK(1:0)
LCDCLK_SS/PCIEX0
SATACLK
PCI/SRC_STOP#
CPU_STOP#
FSL(C:A)
ITP_EN
TEST_MODE
TEST_SEL
VTT_PWRGD#/PD
PEREQ#(2:1)
CONTROL
LOGIC
SDATA
SCLK
SELPCIEX_LCDCLK#
REQ_SEL
IREF
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
6
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Table2: LCDCLK Spread and Frequency Selection Table
Pin
Spread
Byte 6b7
Byte 6b6
Byte 6b5
Byte 6b4 Byte 6b3 17/18
%
MHz
96.00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.8 Down
96.00
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
96.00
96.00
96.00
96.00
96.00
96.00
3 Down
96.00
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
0.8 Down
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
96.00
96.00
96.00
96.00
96.00
96.00
96.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
3 Down
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
100.00
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
7
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
General SMBus serial interface information for the 954226
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
* By default, SMBADR = 0,
Byte N + X - 1
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 1.
N
P
Not acknowledge
stoP bit
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
8
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: Output Control Register
Control
Byte 0
Pin #
Name
Type
RW
0
1
PWD
Function
CPUCLK2_ITP/PCIEX6
Enable
-
-
Disable
Disable
Enable
Enable
Output Enable
1
1
Bit 7
Bit 6
PCIEX5 Enable
Output Enable
RW
-
-
-
-
-
-
PCIEX4 Enable
SATACLK Enable
PCIEX3 Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCIEX2 Enable
PCIEX1 Enable
LCDCLK/PCIEX0 Enable
SMBus Table: Spread and Output Control Register
Control
Function
Test Mode
Byte 1
Pin #
Name
Type
0
1
PWD
-
-
Test Clock Mode Entry
RW
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
0
Bit 7
Bit 6
Bit 5
Bit 4
DOT_96MHz Enable
USB_48MHz Enable
REF_0 Enable
Output Enable
Output Enable
Output Enable
RW
RW
RW
1
1
1
-
-
LCDCLK/PCIEX0 Spectrum
-
OFF
ON
Spread Control
RW
1
Bit 3
Mode
-
-
Disable
Disable
Enable
Enable
CPUCLK1
Output Enable
Output Enable
RW
RW
1
1
Bit 2
Bit 1
CPUCLK0
-
OFF
ON
Spread Spectrum Mode
Spread Control for PLL1
RW
0
Bit 0
SMBus Table: Output Control Register
Byte 2 Pin #
Control
Function
Name
Type
0
1
PWD
-
-
-
-
-
PCICLK5
PCICLK4
PCICLK3
Output Enable
Output Enable
Output Enable
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Hi-Z
Enable
Enable
Enable
Enable
REF/N
1
1
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PCICLK2
Output Enable
Test Mode Selection
Test Mode Selection
Stop all PCI, PCIEX and
SATA clocks
-
Enable
Disable
PCI_STOP
RW
1
Bit 2
-
-
PCI_F0 Enable
PCI_F1 Enable
Output Enable
RW
RW
Disable
Disable
Enable
Enable
1
1
Bit 1
Bit 0
Output Enable
SMBus Table: Output Control Register
Byte 3 Pin #
Control
Function
Name
Type
0
1
PWD
-
PCIEX6
RW
Free Running
Stoppable
0
Bit 7
-
-
-
-
-
-
-
PCIEX5
PCIEX4
SATACLK
PCIEX3
PCIEX2
PCIEX1
PCIEX0
RW
RW
RW
RW
RW
RW
RW
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCIEX clocks
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
9
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: Output Control Register
Control
Byte 4
Pin #
Name
Type
0
1
PWD
Function
Output Enable
Driven in PD
-
-
-
REF_1 Enable
96MHz
RW
RW
RW
Disable
Driven
1X
Enable
Hi-Z
2X
1
1
1
Bit 7
Bit 6
Bit 5
REF_0 STRENGTH
Strength Programming
Allow assertion of
-
-
-
PCI_F1
PCI_F0
RW
RW
RW
Free Running
Free Running
Free Running
Stoppable
Stoppable
Stoppable
0
0
1
Bit 4
Bit 3
Bit 2
PCI_STOP# or setting of
CPUCLK2_ITP
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
-
-
CPUCLK1
CPUCLK0
RW
RW
Free Running
Free Running
Stoppable
Stoppable
1
1
Bit 1
Bit 0
SMBus Table: Output Control Register
Byte 5 Pin #
Control
Name
Type
RW
0
1
PWD
Function
Driven in PCI_STOP#
-
-
PCI_STOP Drive Mode
CPUCLK2_ITP_STOP Drive
Mode
Driven
Driven
Hi-Z
Hi-Z
0
0
Bit 7
Bit 6
RW
CPUCLK1_STOP Drive
Mode
CPUCLK0_STOP Drive
Mode
-
Driven in CPU_STOP#
Driven
Driven
Driven
Driven
Driven
PCIEX
Hi-Z
Hi-Z
RW
RW
RW
RW
RW
RW
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
Hi-Z
PCIEX (6:0) Drive Mode
0
CPUCLK2_ITP_PD Drive
Mode
CPUCLK[1:0] PD Drive
Mode
Driven in Powerdown (PD)
PCIEX/CPU_ITP select
Hi-Z
0
Hi-Z
0
CPU_ITP
ITP_EN
latch
SMBus Table: Output Control Register
Byte 6 Pin #
Control
Function
Name
SS4
Type
RW
0
1
PWD
-
-
LCDCLK Spread Prog Bit 4
96Mhz
100Mhz
0
1
Bit 7
Bit 6
SS3
LCDCLK Spread Prog Bit 3
RW
-
-
SS2
SS1
LCDCLK Spread Prog Bit 2
LCDCLK Spread Prog Bit 1
RW
RW
0
0
Bit 5
Bit 4
See Table 2: LCDCLK Freq Sel
-
-
-
-
SS0
FSLC
FSLB
LCDCLK Spread Prog Bit 0
Freq Select Bit 2
RW
RW
RW
0
Bit 3
Bit 2
Bit 1
Bit 0
Latched
Latched
See Table 1: PLL1 Frequency Selection
Table
Freq Select Bit 1
FSLA
Freq Select Bit 0
RW
Latched
SMBus Table: Vendor & Revision ID Register
Control
Function
Byte 7
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
x
0
0
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
10
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: Byte Count Register
Control
Byte 8
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
Byte Count Programming
b(7:0)
SMBus Table: Watchdog Timer Register
Byte 9 Pin #
Control
Function
Name
Type
0
1
PWD
-
WDH_EN
Watchdog Hard Alarm Enable
RW
Disable
Enable
0
Bit 7
-
-
-
WDS_EN
WD Hard Status
WD Soft Status
Watchdog Soft Alarm Enable
WD Hard Alarm Status
WD Soft Alarm Status
RW
R
R
Disable
Normal
Normal
Enable
Alarm
Alarm
0
X
X
Bit 6
Bit 5
Bit 4
Watch Dog Time base
Control
-
WDTCtrl
RW
290ms Base
1160ms Base
0
Bit 3
-
-
-
WD2
WD1
WD0
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
RW
RW
RW
1
1
1
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
Bit 2
Bit 1
Bit 0
SMBus Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Byte 10
Bit 7
Pin #
Name
Type
0
1
PWD
-
-
-
M/N_EN
LCDCLK/PCIEX0 SEL
REQ_SEL
PLLM/N Programming Enable
SELPCIEX0/LCDCLK#
REQ_SEL
RW
RW
RW
Disable
LCDCLK
PCIEX5
Enable
PCIEX0
PEREQ
0
latch
latch
Bit 6
Bit 5
-
-
Driven
Hi-Z
LCDCLK/PCIEX0
Driven in PD
RW
RW
0
0
Bit 4
Bit 3
Latch
Inputs/Byte6[2:0]
B10b(2:0)
WD Safe Freq Source
WD Safe Freq Source
-
-
-
WD SFC
WD SFB
WD SFA
RW
RW
RW
0
0
0
Bit 2
Bit 1
Bit 0
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
SMBus Table: VCO Frequency Control Register
Control
Function
Byte 11
Pin #
Name
Type
0
1
PWD
-
-
N Div8
N Div 9
N Divider Prog bit 8
RW
RW
X
X
Bit 7
N Divider Prog bit 9
Bit 6
Bit 5
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
M Div5
RW
X
-
-
-
-
-
M Div4
M Div3
M Div2
M Div1
M Div0
RW
RW
RW
RW
RW
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Divider Programming bits
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
11
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: VCO Frequency Control Register
Control
Byte 12
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
-
-
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
N Divider Programming
b(8:0)
N Div0
RW
X
SMBus Table: Spread Spectrum Control Register
Control
Function
Byte 13
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(7:0)
SMBus Table: Spread Spectrum Control Register
Control
Function
Reserved
Byte 14
Bit 7
Pin #
Name
Reserved
SSP14
Type
R
0
1
PWD
-
-
-
-
0
RW
X
Bit 6
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
-
-
-
-
-
-
SSP13
SSP12
SSP11
SSP10
SSP9
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum
Programming b(14:8)
SSP8
SMBus Table: Output Divider Control Register
Control
Function
Byte 15
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
PCIEX Div3
PCIEX Div2
PCIEX Div1
PCIEX Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2
0001:/3
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
X
X
X
X
X
X
X
X
Bit 7
PCIEX Divider Ratio
Programming Bits
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0010:/5 0110:/10 1010:/20 1110:/40
0011:/15 0111:/30 1011:/60 1111:/120
0000:/2
0001:/3
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
CPUDivider Ratio
Programming Bits
0010:/5 0110:/10 1010:/20 1110:/40
0011:/15 0111:/30 1011:/60 1111:/120
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
12
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: PEREQ# Control Register
Control
Byte 16
Pin #
Name
Type
0
1
PWD
Function
-
-
Reserved
Reserved
RW
RW
-
-
0
0
Bit 7
Not Controlled
Controlled
PCIEX4 is controlled
Bit 6
Bit 5
PEREQ2# controls selected
outputs. Outputs controlled
by this pin will be Hi-Z when
PEREQ2# is high.
-
Not Controlled
Controlled
PCIEX3 is controlled
PCIEX1 is controlled
Reserved
RW
RW
RW
RW
0
0
0
0
-
-
Not Controlled
-
Controlled
-
Bit 4
Bit 3
Reserved
-
SATACLK is controlled
Not Controlled
Controlled
Bit 2
PEREQ1# controls selected
outputs. Outputs controlled
by this pin will be Hi-Z when
PEREQ1# is high.
-
-
PCIEX2 is controlled
PCIEX0 is controlled
RW
RW
Not Controlled
Not Controlled
Controlled
Controlled
0
0
Bit 1
Bit 0
SMBus Table: PLL 2 VCO Frequency Control Register
Control
Byte 17
Pin #
Name
Type
0
1
PWD
Function
-
-
N Div8
N Div9
N Divider Prog bit 8
N Divider Prog bit 9
RW
RW
X
X
Bit 7
Bit 6
Bit 5
The decimal representation of M and N
Divier in Byte 17 and 18 will configure the
VCO frequency. Default at power up =
Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
-
M Div5
RW
X
-
-
-
-
-
M Div4
M Div3
M Div2
M Div1
M Div0
RW
RW
RW
RW
RW
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Divider Programming bits
SMBus Table: PLL 2 VCO Frequency Control Register
Control
Byte 18
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
-
-
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N
Divier in Byte 17 and 18 will configure the
VCO frequency. Default at power up =
Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
N Divider Programming
b(8:0)
SMBus Table: PLL 2 Spread Spectrum Control Register
Control
Byte 19
Pin #
Name
Type
0
1
PWD
Function
-
SSP7
RW
X
Bit 7
-
-
-
-
SSP6
SSP5
SSP4
SSP3
RW
RW
RW
RW
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(7:0)
-
-
-
SSP2
SSP1
SSP0
RW
RW
RW
X
X
X
Bit 2
Bit 1
Bit 0
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
13
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: PLL2 Spread Spectrum Control Register
Control
Byte 20
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
-
-
-
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
Reserved
R
-
-
0
Bit 7
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(14:8)
SSP8
RW
X
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
14
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
4.6
UNITS
Notes
-
-
1
1
3.3V Core Supply Voltage VDDA
V
3.3V Logic Input Supply
VDD
4.6
V
Voltage
°C
°C
°C
-
-
-
1
1
1
Storage Temperature
Ambient Operating Temp Tambient
Junction Temperature Tj
Ts
-65
0
150
70
125
-
1
Input ESD protection HBM ESD prot
2000
V
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
V
Notes
1
VDD
0.3
0.8
5
+
Input High Voltage
VIH
3.3 V +/-5%
2
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
VIN = VDD
VSS - 0.3
-5
V
1
1
uA
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
-5
uA
1
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
0.7
uA
V
1
1
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
VIH_FSL
3.3 V +/-5%
3.3 V +/-5%
1.7
VIL_FSL
VSS - 0.3
0.35
V
1
Operating Supply Current IDD3.3OP
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
400
70
12
mA
mA
mA
1
1
1
2
Powerdown Current
IDD3.3PD
Input Frequency
Pin Inductance
Fi
14.31818
MHz
Lpin
7
5
6
5
nH
pF
pF
pF
1
1
1
1
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance
COUT
CINX
From VDD Power-Up or de-assertion of
PD# to 1st clock
Clk Stabilization
TSTAB
1.8
ms
1
Modulation Frequency
Tdrive_PD#
Triangular Modulation
CPU output enable after
PD# de-assertion
30
33
kHz
us
1
1
300
Tfall_Pd#
Trise_Pd#
SMBus Voltage
PD# fall time of
PD# rise time of
5
5
5.5
ns
ns
V
1
1
1
VDD
VOL
2.7
4
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
@ IPULLUP
0.4
V
1
IPULLUP
TRI2C
TFI2C
mA
1
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
ns
ns
1
1
Clock/Data Fall Time
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
15
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
1
Current Source Output
Impedance
Ω
Zo
VO = Vx
3000
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
Vuds
Vx(abs)
d-Vx
Statistical measurement on single
ended signal
Measurement on single ended signal
using absolute value.
660
-150
850
150
1150
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,3
1,3
1
1
1
1
1,2
2
2
2
2
2
2
2
2
2
2
2
-300
250
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
550
140
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
Variation of crossing over all edges
see Tperiod min-max values
400MHz nominal
ppm
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
Average period
Tperiod
2
2
2
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Rise/Fall Matching
tr
tf
d-tr
d-tf
trfm
700
700
125
125
20
175
%
Duty Cycle
Skew
dt3
tsk3
tsk4
Measurement from differential wavefrom
45
55
%
ps
ps
1
1
1
CPU(1:0), VT = 50%
CPU(1:0) to CPU2_ITP,
VT = 50%
100
150
Skew
Measurement from differential wavefrom
(CPU2_ITP)
Jitter, Cycle to cycle
Jitter, Cycle to cycle
tjcyc-cyc
tjcyc-cyc
125
85
ps
ps
1
1
Measurement from differential
wavefrom, (CPU(1:0))
Ω
Ω
Ω
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 , IREF = 475
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
Ω
Ω
IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
16
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Electrical Characteristics - SATA/PCIEX/LCDCLK_SS@100M 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Current Source Output
Impedance
Ω
Zo
VO = Vx
3000
1
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
Vuds
Vx(abs)
d-Vx
Statistical measurement on single
ended signal
Measurement on single ended signal
using absolute value.
660
-150
850
150
1150
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ns
ps
ps
1,3
1,3
1
1
1
1
1,2
2
2
1,2
1
-300
250
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
550
140
300
10.0030
10.0533
Variation of crossing over all edges
see Tperiod min-max values
100.00MHz nominal
ppm
-300
9.9970
9.9970
9.8720
175
Average period
Tperiod
100.00MHz spread
Absolute min period
Rise Time
Tabsmin
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
tr
tf
d-tr
d-tf
trfm
700
700
125
125
20
Fall Time
175
1
1
1
1
Rise Time Variation
Fall Time Variation
Rise/Fall Matching
ps
ps
%
Duty Cycle
Skew
dt3
Measurement from differential wavefrom
VT = 50%
45
55
%
ps
ps
1
1
1
tsk3
250
125
Jitter, Cycle to cycle
tjcyc-cyc Measurement from differential wavefrom
Ω
Ω
Ω
= 475
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9
I
ΒREF
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
Ω
Ω
.
IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50
Electrical Characteristics - DOT_96MHz/LCDCLK_SS@96M 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Current Source Output
Impedance
Ω
Zo
VO = Vx
3000
1
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
Statistical measurement on single
ended signal
Measurement on single ended signal
using absolute value.
660
-150
850
150
1150
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ps
ps
ps
1,3
1,3
1
1
1
1
1,2
2
1,2
1
1
Vuds
-300
250
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Average period
Vx(abs)
d-Vcross
ppm
550
140
100
Variation of crossing over all edges
see Tperiod min-max values
96.00MHz nominal
-100
10.4135
10.1635
175
Tperiod
10.4198
Absolute min period
Rise Time
Tabsmin
96.00MHz nominal
tr
tf
d-tr
d-tf
trfm
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
700
700
125
125
20
Fall Time
175
Rise Time Variation
Fall Time Variation
Rise/Fall Matching
1
1
1
ps
%
Duty Cycle
dt3
Measurement from differential wavefrom
45
55
%
1
1
Jitter, Cycle to cycle
tjcyc-cyc Measurement from differential wavefrom
250
ps
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; C =2pF, R =33.2Ω, R =49.9Ω I
= 475Ω
1Guaranteed by design and characterization, not 100% tested in production.
ΤREF
L
S
P
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
17
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS*
MIN
12
TYP
MAX
55
UNITS
Ω
Notes
Output Impedance
Output High Voltage
Output Low Voltage
RDSP
VO = VDD*(0.5)
1
1
1
1
1
1
1
VOH
IOH = -1 mA
2.4
V
VOL
IOL = 1 mA
0.55
-33
V
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
mA
mA
mA
mA
Output High Current
IOH
Output Low Current
Edge Rate
IOL
VOL @ MAX = 0.4 V
Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
38
4
tslewr/f
1
V/ns
1
Duty Cycle
Group Skew
dt1
45
55
%
ps
ps
1
1
1
tskew
VT = 1.5 V
VT = 1.5 V
500
250
Jitter, Cycle to cycle
tjcyc-cyc
Ω
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33 (unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - 48MHz
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS*
see Tperiod min-max values
48.00MHz output nominal
MIN
-100
20.8313
TYP
MAX
100
20.8354
UNITS
ppm
ns
Notes
1
Ω
Output Impedance
Output High Voltage
Output Low Voltage
RDSP
VOH
VOL
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
0.55
-33
1
1
1
1
1
1
1
2.4
V
V
V
OH @MIN = 1.0 V
OH@MAX = 3.135 V
VOL @ MIN = 1.95 V
OL @ MAX = 0.4 V
-33
30
mA
mA
mA
mA
Output High Current
IOH
V
Output Low Current
Edge Rate
IOL
V
38
2
48M Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
tslewr/f_48
1
V/ns
1
Duty Cycle
dt1
45
55
%
1
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
Ω
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
-300
69.8270
2.4
300
69.8550
ppm
ns
V
1,2
2
1
VOL
IOL = 1 mA
0.4
-23
V
1
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
@MAX = 0.4 V
Output High Current
Output Low Current
Edge Rate
IOH
IOL
-29
29
mA
mA
1
1
1
VOL
27
4
Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
tslewr/f
1
V/ns
Duty Cycle
Jitter
dt1
tjcyc-cyc
45
55
1000
%
ps
1
1
VT = 1.5 V
Ω
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 39
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
18
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Test Clarification Table
Comments
HW
SW
TEST
FSLC/TES FSLB/TES ENTRY REF/N or
T_SEL
T_MODE
BIT
HI-Z
HW PIN HW PIN
W1b7
W2b3
OUTPUT
NORMAL
HI-Z
REF/N
REF/N
0
1
1
1
X
0
0
1
0
X
X
X
X
0
1
0
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
1
0
1
X
1
1
0
REF/N
HI-Z
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up
through SMBus B1b7.
X
o If TEST is selected by B1b7, only B2b3 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
0
X
1
1
REF/N
· Power must be cycled to exit TEST.
W1b7: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
W2b3: 1= REF/N, Default = 0 (HI-Z)
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
19
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
c
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
L
0.45
0.75
.018
.030
A
N
SEE VARIATIONS
SEE VARIATIONS
A2
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- CC --
VARIATIONS
e
SEATING
PLANE
b
D mm.
D (inch)
N
MIN
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
13.90
Reference Doc.: JEDEC Publicat ion 95, M O-153
10-0039
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
20
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
(Ref.)
ND & N
Even
Seating Plane
(ND -1)x e
(Ref.)
A1
Index Area
L
A3
E2
N
N
(T yp.)
e
2
If ND & N
are Even
1
Anvil
Singulation
2
(N -1)x
e
OR
(Ref.)
E2
2
Sawn
Singulation
Top V iew
b
e
Thermal
Base
(Re f.)
D2
2
A
D
&
ND
Odd
N
D2
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
0. 08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
DIMENSIONS
SYMBOL
MIN.
0.8
0
MAX.
1.0
ICS 56L
VLLD-2 / -5 TOLERANCE
A
A1
A3
b
SYMBOL
0.05
N
ND
NE
56
14
14
56
14
14
0.25 Reference
0.18
0.3
e
0.50 BASIC
D x E BASIC
8.00 x 8.00 8.00 x 8.00
D2 MIN. / MAX. 2.75 / 6.80
E2 MIN. / MAX. 2.75 / 6.80
L MIN. / MAX. 0.30 / 0.50
4.35 / 4.65
5.05 / 5.35
0.30 / 0.50
Ordering Information
Part / Order Number Shipping Packaging
Package
56-pin TSSOP
56-pin TSSOP
56-pin MLF
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
954226AGLF
954226AGLFT
954226AKLF
954226AKLFT
Tubes
Tape and Reel
Tubes
Tape and Reel
56-pin MLF
“LF” to the suffix are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
21
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Revision History
Rev. Issue Date
Who
Description
Page #
0.1 3/29/2005
JC
Updated Ordering Information from "Lead Free" to "Annealed Lead Free"
18
0.2 7/14/2006
DC
Added MLF Pinout, Pin Description and Ordering Information.
1. Clean up Electrical Tables
1, 4, 5, 21
2. Corrected Test Clarification Table
3. Move to final
A
4/12/2010
RDW
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www.IDT.com
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Fax: 65-6-744-1764
England
Phone: 44-1372-363339
Fax: 44-1372-378851
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks
a
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
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22
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