954141CGLFT [IDT]
Clock Generator, PDSO56;
| 型号： | 954141CGLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO56 光电二极管 |
| 文件： | 总19页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
954141
Datasheet
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
Features/Benefits:
CK410 compliant clock
•
•
•
•
•
•
Programmable output frequencies
Programmable output skew.
Programmable spread percentage for EMI control.
Programmable watch dog safe frequency.
Output Features:
•
•
•
2 - 0.7V current-mode differential CPU pairs
6 - 0.7V current-mode differential SRC pair
Supports tight ppm accuracy clocks for Serial-ATA
1 - 0.7V current-mode differential CPU_ITP/SRC
selectable pair
Supports spread spectrum modulation, 0 to -0.5%
down spread, 0.25% center spread, and 0.3%
center spread
•
•
•
•
•
6 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
1 - REF, 14.318MHz
•
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Supports undriven differential CPU, SRC pair in PD#
for power management.
Key Specifications:
•
•
•
CPU/SRC outputs cycle-cycle jitter < 85ps
PCI outputs cycle-cycle jitter < 250ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
Pin Configuration
Bit2 Bit1 Bit0
FSLC FSLB FSLA MHz
CPU
SRC
MHz
SATA
MHz
PCI
MHz
33.33
Bit4 Bit3
1
56
PCICLK2
55 PCICLK1
54 PCICLK0
VDDPCI
GND 2
PCICLK3 3
266.66 100.00 100.00
133.33 100.00 100.00
200.00 100.00 100.00
166.66 100.00 100.00
333.33 100.00 100.00
100.00 100.00 100.00
400.00 100.00 100.00
200.00 100.00 100.00
266.66 133.33 133.33
133.33 133.33 133.33
200.00 133.33 133.33
166.66 125.00 125.00
333.33 125.00 125.00
100.00 133.33 133.33
400.00 133.33 133.33
200.00 133.33 133.33
269.33 101.00 101.00
134.66 101.00 101.00
202.00 101.00 101.00
168.33 101.00 101.00
274.66 103.00 103.00
137.33 103.00 103.00
206.00 103.00 103.00
171.66 103.00 103.00
279.99 105.00 105.00
140.00 105.00 105.00
210.00 105.00 105.00
174.99 105.00 105.00
287.99 108.00 108.00
144.00 108.00 108.00
216.00 108.00 108.00
179.99 108.00 108.00
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.67
33.67
33.67
33.67
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
36.00
36.00
36.00
36.00
4
5
6
7
8
9
53
52
51
50
49
48
PCICLK4
PCICLK5
FSLC
REFOUT
0
0
0
0
0
1
1
0
1
0
GND
VDDPCI
ITP_EN/PCICLK_F0
PCICLK_F1
GND
X1
X2
0
0
0
0
1
1
0
1
1
0
VDDREF
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCICLK_F2 10
VDD48 11
47 SDATA
46 SCLK
12
13
14
15
16
45
44
43
42
41
USB_48MHz
GND
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
DOTT_96MHz
DOTC_96MHz
FSLB
Vtt_PwrGd#/PD 17
40 CPUCLKC1
18
19
20
21
22
39
38
37
36
35
FSLA
SRCCLKT1
SRCCLKC1
VDDSRC
IREF
GNDA
VDDA
CPUCLKT2_ITP/SRCCLKT_7
CPUCLKC2_ITP/SRCCLKC_7
SRCCLKT2
SRCCLKC2 23
SRCCLKT3 24
34 VDDSRC
33 SRCCLKT6
25
26
27
28
32
31
30
29
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
SRCCLKC6
SRCCLKT5
SRCCLKC5
GND
56-Pin SSOP and TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1
1
1
1
1
1
1
1
0
1
0934A—03/30/09
954141
Datasheet
Pin Description
PIN NAME
TYPE
PWR
PWR
OUT
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PIN #
1
VDDPCI
GND
2
3
PCICLK3
PCI clock output.
4
5
PCICLK4
PCICLK5
OUT
OUT
PCI clock output.
PCI clock output.
6
7
GND
PWR
PWR
Ground pin.
VDDPCI
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
8
ITP_EN/PCICLK_F0
I/O
0 = SRC pair
9
PCICLK_F1
PCICLK_F2
OUT
OUT
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
10
11
VDD48
PWR
Power pin for the 48MHz output.3.3V
12
13
14
15
USB_48MHz
GND
OUT
PWR
OUT
OUT
48.00MHz USB clock
Ground pin.
DOTT_96MHz
DOTC_96MHz
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
16
17
18
FSLB
IN
IN
IN
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Vtt_PwrGd#/PD
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
FSLA
19
20
SRCCLKT1
SRCCLKC1
OUT
OUT
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
21
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
22
23
SRCCLKT2
SRCCLKC2
OUT
OUT
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
24
25
26
27
28
SRCCLKT3
OUT
OUT
OUT
OUT
PWR
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
0934A—03/30/09
2
954141
Datasheet
Pin Description
PIN NAME
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
PIN #
29
GND
Ground pin.
30
31
32
33
34
SRCCLKC5
SRCCLKT5
SRCCLKC6
SRCCLKT6
VDDSRC
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
35
36
CPUCLKC2_ITP/SRCCLKC_7
CPUCLKT2_ITP/SRCCLKT_7
OUT
OUT
37
38
VDDA
GNDA
PWR
PWR
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
39
40
IREF
OUT
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
CPUCLKC1
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
41
42
43
CPUCLKT1
VDDCPU
OUT
PWR
OUT
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
CPUCLKC0
44
CPUCLKT0
OUT
45
46
47
48
49
GND
PWR
IN
Ground pin.
SCLK
SDATA
VDDREF
X2
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
I/O
PWR
OUT
50
51
52
X1
IN
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
GND
REFOUT
PWR
OUT
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
53
FSLC
IN
54
55
56
PCICLK0
PCICLK1
PCICLK2
OUT
OUT
OUT
PCI clock output.
PCI clock output.
PCI clock output.
0934A—03/30/09
3
954141
Datasheet
General Description
ICS954141A follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS954141A is driven with a 14.318MHz crystal.
Block Diagram
48MHz, USB
Frequency
Dividers
DOTT_96MHz
DOTC_96MHz
PLL2
X1
X2
XTAL
REFOUT
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT (6:1)
SRCCLKC (6:1)
PCICLK (5:0)
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
SCLK
SDATA
PLL1
Control
Logic
Vtt_PWRGD#/PD
FSLA
PCICLKF (2:0)
CPU_ITP/SRC7T
FSLB
FSLC
ITP_EN
CPU_ITP/SRC7C
I REF
0934A—03/30/09
4
954141
Datasheet
General I2C serial interface information for the ICS954141A
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0934A—03/30/09
5
954141
Datasheet
Table1: Frequency Selection Table
Bit2 Bit1 Bit0
CPU
SRC
MHz
SATA
MHz
PCI
Spread
%
Bit4 Bit3
FSLC FSLB FSLA
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
266.66 100.00 100.00
133.33 100.00 100.00
200.00 100.00 100.00
166.66 100.00 100.00
333.33 100.00 100.00
100.00 100.00 100.00
400.00 100.00 100.00
200.00 100.00 100.00
266.66 133.33 133.33
133.33 133.33 133.33
200.00 133.33 133.33
166.66 125.00 125.00
333.33 125.00 125.00
100.00 133.33 133.33
400.00 133.33 133.33
200.00 133.33 133.33
269.33 101.00 101.00
134.66 101.00 101.00
202.00 101.00 101.00
168.33 101.00 101.00
274.66 103.00 103.00
137.33 103.00 103.00
206.00 103.00 103.00
171.66 103.00 103.00
279.99 105.00 105.00
140.00 105.00 105.00
210.00 105.00 105.00
174.99 105.00 105.00
287.99 108.00 108.00
144.00 108.00 108.00
216.00 108.00 108.00
179.99 108.00 108.00
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.67
33.67
33.67
33.67
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
36.00
36.00
36.00
36.00
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
+/-0.25% Center
+/-0.25% Center
+/-0.25% Center
+/-0.25% Center
+/-0.25% Center
+/-0.25% Center
+/-0.25% Center
+/-0.25% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
+/-0.3% Center
0934A—03/30/09
6
954141
Datasheet
I2C Table: Frequency Select Register
Byte 0 Pin #
Name
Control Function
Type
0
1
PWD
-
Latch Inputs
IIC
FS Source
Frequency H/W IIC Select
RW
0
Bit 7
-
-
-
-
-
-
-
OFF
OFF
ON
ON
SS_EN1
SS_EN2
Bit4
PLL1 Spread Enable
PLL2 Spread Enable
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
RW
RW
RW
RW
RW
RW
RW
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Bit3
0
See Table 1: PLL 1 Frequency Selection Table
FSLC
FSLB
FSLA
Latch
Latch
Latch
I2C Table: Output Control Register
Byte 1 Pin #
Bit 7
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
-
PCICLK_F0
DOTT/C_96MHz
USB_48MHz
REFOUT
Output Control
Output Control
Output Control
Output Control
Reserved
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
Disable
Disable
Enable
Enable
CPUCLKT/C1
CPUCLKT/C0
Output Control
Output Control
PD Mode Output State
Control
-
Driven
Hi-Z
CPUCLK's
RW
0
Bit 0
I2C Table: Output Control Register
Byte 2 Pin #
Bit 7
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F2
PCICLK_F1
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Output Control Register
Byte 3 Pin #
Bit 7
Name
Control Function
Type
0
1
PWD
PD Mode Output State
Control
-
-
Driven
Hi-Z
SRCCLK's
RW
RW
0
1
CPUCLKT/C2 /
SRCCLK7
Disable
Enable
Output Control
Bit 6
-
-
-
-
-
-
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
SRCCLKT/C6
SRCCLKT/C5
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRCCLKT/C_SATA4
SRCCLKT/C3
SRCCLKT/C2
SRCCLKT/C1
0934A—03/30/09
7
954141
Datasheet
I2C Table: Output Control Register
Byte 4 Pin #
Bit 7
Name
Control Function
Type
0
1
PWD
-
PCI/SRC Stop EN
Stop all PCI / SRC clocks
Enable
Disable
1
-
-
-
-
-
-
-
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
-
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
-
PCICLK_F2
PCICLK_F1
Stop Control
Stop Control
Stop Control
Stop Control
Stop Control
Stop Control
Reserved
RW
RW
RW
RW
RW
RW
RW
0
0
0
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK_F0
SRCCLKT/C (7:5)
SRCCLKT/C 4
SRCCLKT/C (3:1)
Reserved
I2C Table: Programmable Skew Control Register
Byte 5
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
PCISkw1
PCISkw0
ASYNC1
ASYNC0
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0000:0
0100:150
0101:N/A
0110:N/A
0111:N/A
1000:300 1100:450
0
0
0
0
0
0
0
0
Bit 7
CPU-PCI 7 Steps Skew
Control (ps) (Also see
Table 3)
0001:N/A
0010:N/A
0011:N/A
1001:N/A 1101:600
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1010:N/A 1110:750
1011:N/A 1111:900
00 = PLL1/ PLL2
10 = 37.7
PCI Async Freq (see Table
6)
01 = 33.0
11 = 44.0
-
-
-
-
Reserved
Reserved
I2C Table: Output Drive Control Register
Byte 6
Pin #
Name
Control Function
Reserved
Type
0
1
PWD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
I2C Table: Vendor ID Register
Byte 7 Pin #
Bit 7
Name
Control Function
Type
0
1
PWD
-
-
-
PLL1
PLL1
PLL1
PLL2
PLL2
PLL2
SRC _SOURCE
PCI_SOURCE
SRC comes from
PCI comes from
SATA comes from
RW
RW
RW
0
0
0
Bit 6
Bit 5
SRC_SATA_Source
PLL2 (SATA, SRC,PCI )
Synchronization
-
Async
Sync
PLL2 Sync
RW
0
Bit 4
-
-
-
-
-
-
-
-
-
VID3
VID2
VID1
VID0
R
R
R
R
0
0
0
1
Bit 3
Bit 2
Bit 1
Bit 0
-
VENDOR ID
001 = ICS
-
0934A—03/30/09
8
954141
Datasheet
I2C Table: Byte Count Register
Byte 8 Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte Count Programming
b(7:0)
Writing to this register will configure how many
bytes will be read back, default is 0F = 15 bytes.
I2C Table: WD Time Control Register
Byte 9 Pin #
Name
Control Function
Type
RW
0
1
PWD
Watchdog Hard Alarm
Enable
-
-
WDH_EN
WDS_EN
Disable
Disable
Enable
Enable
0
0
Bit 7
Bit 6
Watchdog Soft Alarm
Enable
RW
-
-
Normal
Normal
Alarm
Alarm
WD Hard Status
WD Soft Status
WD Hard Alarm Status
WD Soft Alarm Status
R
R
X
X
Bit 5
Bit 4
Watch Dog Time base
Control
-
290ms Base
1160ms Base
WDTCtrl
RW
0
Bit 3
-
-
-
WD2
WD1
WD0
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
RW
RW
RW
1
1
1
Bit 2
Bit 1
Bit 0
These bits represent X*290ms (or 1.16S) the
watchdog timer waits before it goes to alarm mode.
Default is 7 X 290ms = 2s.
I2C Table: M/N Programming & WD Safe Frequency Control Register
Byte 10
Pin #
Name
Control Function
Type
0
1
PWD
PLL1 M/N Programming
Enable
-
Disable
Enable
M/N_EN
RW
0
Bit 7
-
-
-
-
-
-
-
-
-
Reserved
WD Safe Freq
Source
Reserved
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B10b(4:0)
Latch Inputs/B0(4:0)
WD Safe Freq Source
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe frequency
as Byte0 bit (4:0).
I2C Table: PLL1 Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
N Divider Prog bit 9
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N Divier in
Byte 11 and 12 will configure the PLL1 VCO
frequency. Default at power up = latch-in or Byte 0
Rom table. VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
M Divider Programming
bit (5:0)
0934A—03/30/09
9
954141
Datasheet
I2C Table: PLL1 Frequency Control Register
Byte 12
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N Divier in
Byte 11 and 12 will configure the PLL1 VCO
frequency. Default at power up = latch-in or Byte 0
Rom table. VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
N Divider Programming
Byte12 bit(7:0) and Byte11
bit(7:6)
I2C Table: PLL1 Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum
Programming bit(7:0)
These Spread Spectrum bits in Byte 13 and 14 will
program the spread pecentage of PLL1
I2C Table: PLL1 Spread Spectrum Control Register
Byte 14
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
-
-
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
Reserved
R
0
Bit 7
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum
Programming bit(14:8)
These Spread Spectrum bits in Byte 13 and 14 will
program the spread pecentage of PLL1
SSP8
I2C Table: PLL2 Frequency Control Register
Byte 15
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
N Divider Prog bit 9
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N Divier in
Byte 15 and 16 will configure the PLL2 VCO
frequency. Default at power up = latch-in or Byte 0
Rom table. VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
M Divider Programming
bits
0934A—03/30/09
10
954141
Datasheet
I2C Table: PLL2 Frequency Control Register
Byte 16
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N Divier in
Byte 15 and 16 will configure the PLL2 VCO
frequency. Default at power up = latch-in or Byte 0
Rom table. VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
N Divider Programming
b(7:0)
I2C Table: PLL2 Spread Spectrum Control Register
Byte 17
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum
Programming b(7:0)
These Spread Spectrum bits in Byte 17 and 18 will
program the spread pecentage of PLL2
I2C Table: PLL2 Spread Spectrum Control Register
Byte 18
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
-
-
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
Reserved
R
0
Bit 7
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum
Programming b(14:8)
These Spread Spectrum bits in Byte 17 and 18 will
program the spread pecentage of PLL2
SSP8
I2C Table: Programmable Output Divider Register
Byte 19
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
SRCDiv3
SRCDiv2
SRCDiv1
SRCDiv0
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2
0001:/3
0010:/5
0011:/7
0000:/2
0001:/3
0010:/5
0011:/7
0100:/4
0101:/6
0110:/10
1000:/8
1001:/12
1010:/20
1100:/16
1101:/24
1110:/40
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU Divider Ratio
Programming Bits for PLL1
0111:/14
0100:/4
1011:/28
1000:/8
1111:/56
1100:/16
0101:/6
1001:/12
1010:/20
1011:/28
1101:/24
1110:/40
SRC Divider Ratio
Programming Bits for PLL1
0110:/10
0111:/14
1111:/56
0934A—03/30/09
11
954141
Datasheet
Absolute Maximum Rating
PARAMETER
SYMBOL
VDD_A
CONDITIONS
MIN
TYP
MAX
UNITS
V
Notes
-
1
3.3V Core Supply Voltage
VDD + 0.5V
3.3V Logic Input Supply
Voltage
-
1
VDD_In
GND - 0.5
V
DD + 0.5V
V
Storage Temperature
Ambient Operating Temp
Case Temperature
Ts
-65
0
150
70
°C
°C
°C
V
-
-
-
-
1
1
1
1
Tambient
Tcase
115
Input ESD protection HBM
ESD prot
2000
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS*
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
Notes
VIH
VIL
IIH
3.3 V +/-5%
2
VSS - 0.3
-5
V
V
1
1
1
3.3 V +/-5%
VIN = VDD
5
uA
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
-5
uA
1
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
0.7
uA
V
1
1
1
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
VIH_FSL
3.3 V +/-5%
3.3 V +/-5%
VDD + 0.3
0.35
VIL_FSL
IDD3.3OP
IDD3.3OP
VSS - 0.3
V
Operating Supply Current
Operating Current
Full Active, CL = Full load;
all outputs driven
350
400
70
mA
mA
mA
mA
MHz
nH
1
1
1
1
2
1
1
1
1
all diff pairs driven
Powerdown Current
IDD3.3PD
all differential pairs tri-stated
VDD = 3.3 V
12
Input Frequency
Pin Inductance
Fi
14.31818
Lpin
7
5
6
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
pF
Input Capacitance
COUT
CINX
pF
pF
From VDD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
Clk Stabilization
Modulation Frequency
Tdrive_PD#
TSTAB
1.8
33
ms
kHz
us
1
1
1
30
CPU output enable after
PD# de-assertion
300
Tfall_Pd#
Trise_Pd#
PD# fall time of
PD# rise time of
5
ns
ns
V
1
1
1
1
5
SMBus Voltage
VDD
VOL
2.7
4
5.5
0.4
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
@ IPULLUP
V
IPULLUP
mA
1
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
TRI2C
TFI2C
1000
300
ns
ns
1
1
Clock/Data Fall Time
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
0934A—03/30/09
12
954141
Datasheet
Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
NOTES
1
V
O = Vx
Current Source Output Impedance
Zo
3000
Voltage High
Voltage Low
VHigh
VLow
Vovs
660
850
150
mV
mV
mV
mV
mV
1,3
1,3
1
Statistical measurement on single
ended signal
-150
Max Voltage
1150
Measurement on single ended
signal using absolute value.
Min Voltage
Vuds
-300
250
1
Crossing Voltage (abs)
Vx(abs)
550
140
1
Variation of crossing over all
edges
see Tperiod min-max values
Crossing Voltage (var)
Long Accuracy
d-Vx
ppm
mV
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
400MHz nominal
400MHz spread
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
2
333.33MHz nominal
2
333.33MHz spread
2
266.66MHz nominal
3.7511
3.77
2
266.66MHz spread
2
200MHz nominal
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
2
Average period
Tperiod
200MHz spread
2
166.66MHz nominal
2
166.66MHz spread
2
133.33MHz nominal
2
133.33MHz spread
2
100.00MHz nominal
2
100.00MHz spread
2
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
Tabsmin
Absolute min period
tr
tf
Rise Time
Fall Time
700
700
125
125
175
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
1
VOH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
1
dt3
Duty Cycle
Skew
45
55
%
1
1
tsk3
CPU(1:0), VT = 50%
100
ps
CPU(1:0) to CPU2_ITP,
VT = 50%
tsk4
Skew
150
ps
1
Measurement from differential
wavefrom (CPU2_ITP)
Measurement from differential
tjcyc-cyc
tjcyc-cyc
Jitter, Cycle to cycle
Jitter, Cycle to cycle
125
85
ps
ps
1
1
wavefrom, (CPU(1:0))
REF
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
0934A—03/30/09
13
954141
Datasheet
Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
1
V
O = Vx
Current Source Output Impedance
Zo
3000
Voltage High
Voltage Low
VHigh
VLow
Vovs
660
850
150
mV
mV
mV
mV
mV
1,3
1,3
1
Statistical measurement on single
ended signal
-150
Max Voltage
1150
Measurement on single ended
signal using absolute value.
Min Voltage
Vuds
-300
250
1
Crossing Voltage (abs)
Vx(abs)
550
140
1
Variation of crossing over all
edges
see Tperiod min-max values
Crossing Voltage (var)
Long Accuracy
d-Vx
ppm
mV
1
-300
9.9970
9.9970
9.8720
175
300
ppm
ns
1,2
2
100.00MHz nominal
100.00MHz spread
10.0030
10.0533
Average period
Tperiod
ns
2
Absolute min period
Rise Time
Tabsmin
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
ns
1,2
1
tr
tf
700
700
125
125
ps
Fall Time
175
ps
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
ps
1
VOH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
ps
1
dt3
tsk3
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
VT = 50%
250
125
Measurement from differential
wavefrom
tjcyc-cyc
Jitter, Cycle to cycle
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Electrical Characteristics - PCICLK/PCICLK_F
NOTES
PARAMETER
SYMBOL
CONDITIONS*
MIN
12
TYP
MAX
55
UNITS
RDSP
VO = VDD*(0.5)
Output Impedance
Output High Voltage
Output Low Voltage
1
1
1
1
1
1
1
1
1
1
1
1
1
VOH
VOL
IOH = -1 mA
IOL = 1 mA
2.4
V
V
0.55
-33
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
mA
mA
V/ns
ns
IOH
Output High Current
Output Low Current
IOL
38
4
tslewr/f
tr
Edge Rate
Rise Time
1
0.5
0.5
45
2
tf
Fall Time
2
ns
dt1
Duty Cycle
55
500
250
%
tskew
tjcyc-cyc
VT = 1.5 V
Group Skew
Jitter, Cycle to cycle
ps
VT = 1.5 V
ps
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 4 pF with Rs = 33 (unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
0934A—03/30/09
14
954141
Datasheet
Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
NOTES
1
PARAMETER
SYMBOL
CONDITIONS*
see Tperiod min-max values
48.00MHz output nominal
VO = VDD*(0.5)
MIN
-100
20.8313
12
TYP
MAX
100
UNITS
ppm
ns
Long Accuracy
ppm
Tperiod
RDSP
Clock period
20.8354
55
Output Impedance
Output High Voltage
Output Low Voltage
1
1
1
1
1
1
1
1
VOH
IOH = -1 mA
2.4
V
VOL
IOL = 1 mA
0.55
-33
V
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
-33
30
mA
mA
mA
mA
V/ns
IOH
Output High Current
Output Low Current
VOL @ MIN = 1.95 V
IOL
VOL @ MAX = 0.4 V
38
4
tslewr/f
Edge Rate
Edge Rate
Rising/Falling edge rate
1
1
tslewr/f_USB
USB48 Rising/Falling edge rate
2
V/ns
1
tr
tf
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
0.5
0.5
1
2
2
ns
ns
ns
ns
%
1
1
1
1
1
1
tr_USB
tf_USB
dt1
Rise Time
2
Fall Time
1
2
Duty Cycle
45
55
500
tjcyc-cyc
VT = 1.5 V
Jitter, Cycle to cycle
ps
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 4 pF with Rs = 33 (Rs is used in USB48MHz test only)
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
1
VO = Vx
Current Source Output Impedance
Zo
3000
Voltage High
Voltage Low
VHigh
VLow
Vovs
660
850
150
mV
mV
mV
mV
mV
1,3
1,3
1
Statistical measurement on single
ended signal
-150
Max Voltage
1150
Measurement on single ended
signal using absolute value.
Min Voltage
Vuds
-300
250
1
Crossing Voltage (abs)
Vx(abs)
550
140
1
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
mV
1
Long Accuracy
Average period
Absolute min period
Rise Time
ppm
Tperiod
Tabsmin
tr
see Tperiod min-max values
-100
10.4135
10.1635
175
100
ppm
ns
1,2
2
96.00MHz nominal
96.00MHz nominal
10.4198
ns
1,2
1
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
700
700
125
125
ps
tf
Fall Time
175
ps
1
d-tr
Rise Time Variation
Fall Time Variation
ps
1
d-tf
VOH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
Measurement from differential
ps
1
dt3
Duty Cycle
45
55
%
1
1
tjcyc-cyc
Jitter, Cycle to cycle
250
ps
wavefrom
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
0934A—03/30/09
15
954141
Datasheet
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
MIN
-300
TYP
MAX
300
UNITS
ppm
ns
Notes
Long Accuracy
ppm
1,2
2
Tperiod
VOH
Clock period
69.8270
2.4
69.8550
Output High Voltage
Output Low Voltage
V
1
VOL
IOL = 1 mA
0.4
-23
V
1
VOH @MIN = 1.0 V,
IOH
Output High Current
Output Low Current
-29
29
mA
mA
1
1
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
@MAX = 0.4 V
VOL
IOL
27
tslewr/f
tr1
Edge Rate
Rise Time
Fall Time
Duty Cycle
Jitter
Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
4
2
V/ns
ns
1
1
1
1
1
tf1
1
2
ns
dt1
45
55
1000
%
tjcyc-cyc
VT = 1.5 V
ps
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 4 pF with Rs = 39 (Rs is used in USB48MHz test only)
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0934A—03/30/09
16
954141
Datasheet
56-Lead, 300 mil Body, 25 mil, SSOP
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
A1
D mm.
D (inch)
- CC --
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
e
SEATING
PLANE
56
b
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
954141AFLF-T
Example:
XXXX A F LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0934A—03/30/09
17
954141
Datasheet
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
(240 mil)
(20 mil)
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
α
h x 45°
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
MAX
14.10
MIN
.547
MAX
.555
e
SEATING
PLANE
b
56
13.90
.10 (.004)
C
Ref erence Doc.: JEDEC Publicat ion 95, M O-153
10 - 0 0 3 9
Ordering Information
954141AGLF-T
Example:
XXXX A G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0934A—03/30/09
18
954141
Datasheet
Revision History
Rev.
Issue Date Description
Page #
N/A
10/13/2004 Added TSSOP ordering information
1. Corrected single-ended clock loading.
18
2. Updated part ordering information.
3. Removed water marks.
A
3/30/2009
Various
4. Moved to final.
0934A—03/30/09
19
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