952906BGLF [IDT]
TSSOP-48, Tube;
| 型号： | 952906BGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-48, Tube 外围集成电路 |
| 文件： | 总23页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS952906A
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
Features/Benefits:
VIA VN800/CN700/P4M800 style chipset for P4 processor
•
•
•
•
•
•
Programmable output frequency.
Programmable asynchronous 3V66&PCI frequency.
Programmable output divider ratios.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system
malfunctions.
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
Uses external 14.318MHz reference input.
Output Features:
•
•
•
•
•
•
•
3 - 0.7V current-mode differential CPU pairs
10 - PCI, 3 free running, 33MHz
2 - REF, 14.318MHz
3 - 3V66, 66.66MHz
1 - 48MHz
•
•
1 - 24/48MHz
2 - 25MHz @ 2.5V
•
Key Specifications:
•
•
•
•
•
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
CPU - AGP skew < +/- 350ps
AGP-PCI skew between 1~3.5ns
Functionality
Pin Configuration
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
AGP
MHz
PCI
MHz
33.33
*FS1/REF0
**FS0/REF1
VDDREF
1
48 VDDA
47 GND
46 IREF
45 CPUCLKT_ITP/(PCI_STOP#)
44 CPUCLKC_ITP/(CPU_STOP#)
43 GND
42 CPUCLKT1
41 CPUCLKC1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
100.00 66.67
200.00 66.67
133.33 66.67
166.67 66.67
200.00 66.67
400.00 66.67
266.67 66.67
333.33 66.67
100.99 67.33
201.98 67.33
134.65 67.33
168.31 67.32
115.00 76.67
230.00 76.67
153.33 76.66
191.67 76.67
100.00 66.66
200.00 66.66
133.33 66.66
166.67 71.43
200.00 66.66
400.00 66.66
266.67 66.66
333.33 66.66
105.00 69.99
210.00 69.99
140.00 69.99
175.00 69.99
110.00 73.33
220.00 73.33
146.66 73.33
183.34 73.33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X1
X2
GND
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
40
VDDCPU
39 CPUCLKT0
38 CPUCLKC0
37
GND
36 25Mhz_0
VDDPCI
GND
**MODE/PCICLK0
PCICLK1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
35 25Mhz_1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
GND
PCICLK5
PCICLK6
34
VDD2.5
33 VttPWR_GD/PD#
32 SDATA
31 SCLK
1
1
1
0
0
0
0
1
30
29
28
Reset#
3V66_0
GND
21
**FS3/48MHz
**Sel24_48#/24_48MHz 22
27 VDD3V66
26
1
1
1
1
1
1
1
1
1
1
1
1
1
23
24
GND
VDD48
3V66_1
25 3V66_2
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
48-pin SSOP & TSSOP
1
1
1
1
1
1
1
1
1
0
1
1236A—08/06/07
Integrated
Circuit
ICS952906A
Systems, Inc.
Pin Description
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
2
3
4
*FS1/REF0
**FS0/REF1
VDDREF
X1
I/O
I/O
PWR
IN
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
5
6
7
8
9
10
11
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
OUT
PWR
I/O
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
I/O
OUT
PWR
PWR
GND
Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP
inputs) / PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
12
**MODE/PCICLK0
I/O
13
14
15
16
17
18
19
20
21
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
GND
PCICLK5
PCICLK6
**FS3/48MHz
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
22
**Sel24_48#/24_48MHz
I/O
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz.
23
24
25
26
27
28
29
GND
PWR
PWR
OUT
OUT
PWR
PWR
OUT
Ground pin.
Power pin for the 48MHz output.3.3V
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
VDD48
3V66_2
3V66_1
VDD3V66
GND
3V66_0
Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is
active low.
30
Reset#
OUT
31
32
SCLK
SDATA
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready
to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the
device into a low power state.
33
VttPWR_GD/PD#
IN
34
35
36
37
VDD2.5
25Mhz_1
25Mhz_0
GND
PWR
OUT
OUT
PWR
Power supply, nominal 2.5V
25MHz clock output, 2.5V
25MHz clock output, 2.5V
Ground pin.
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
38
CPUCLKC0
OUT
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
39
40
41
CPUCLKT0
VDDCPU
OUT
PWR
OUT
CPUCLKC1
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
Ground pin.
42
43
44
CPUCLKT1
GND
OUT
PWR
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias. / Stops all CPUCLK besides the free running clocks
CPUCLKC_ITP/(CPU_STOP#) I/O
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias. / Stops all PCICLK besides the free running clocks
45
46
CPUCLKT_ITP/(PCI_STOP#) I/O
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard
IREF
OUT
value.
47
48
GND
VDDA
PWR
PWR
Ground pin.
3.3V power for the PLL core.
1236A—08/06/07
2
Integrated
Circuit
ICS952906A
Systems, Inc.
General Description
ICS952906A is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such
as the 93788, it provides all the necessary clock signals for such a system.
The ICS952906A is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
Frequency
Dividers
48MHz
PLL2
24_48MHz
X1
X2
XTAL
REF (1:0)
CPUCLKT (1:0)/ITP
CPUCLKC (1:0)/ITP
25MHz (1:0)
CPU_STOP#
PCI_STOP#
FS (4:0)
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
PLL1
SCLK
Control
Logic
3V66 (2:0)
Sel24_48#
SDATA
PCICLK (6:0)
PCICLK_F (2:0)
MODE
RESET#
I REF
VTTPWRGD#/PD#
Power Groups
Pin Number
Description
VDD
GND
3
6
11, 18
23
REF, Xtal
PCICLK outputs
48MHz Fix, Fix Digital, Fix analog
3V66 outputs
10, 17
24
27
28
34
37
43
2.5V for 25MHz outputs
CPU outputs
40
48
47
CPU Analog, CPU digital
1236A—08/06/07
3
Integrated
Circuit
ICS952906A
Systems, Inc.
General I2C serial interface information for the ICS952906A
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
1236A—08/06/07
4
Integrated
Circuit
ICS952906A
Systems, Inc.
Table1: QuadRom Frequency Selection Table
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
AGP
PCI
Spread
%
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0 MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100.00 66.67
200.00 66.67
133.33 66.67
166.67 66.67
200.00 66.67
400.00 66.67
266.67 66.67
333.33 66.67
100.99 67.33
201.98 67.33
134.65 67.33
168.31 67.32
115.00 76.67
230.00 76.67
153.33 76.66
191.67 76.67
100.00 66.66
200.00 66.66
133.33 66.66
166.67 71.43
200.00 66.66
400.00 66.66
266.67 66.66
333.33 66.66
105.00 69.99
210.00 69.99
140.00 69.99
175.00 69.99
110.00 73.33
220.00 73.33
146.66 73.33
183.34 73.33
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
33.33 0 to -0.5% Down
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
0.25% Center
0.25% Center
0.25% Center
0.25% Center
No Spread
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
No Spread
No Spread
No Spread
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
No Spread
No Spread
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
No Spread
No Spread
No Spread
No Spread
1236A—08/06/07
5
Integrated
Circuit
ICS952906A
Systems, Inc.
Table1: QuadRom Frequency Selection Table (Continued)
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
AGP
PCI
Spread
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0 MHz
MHz
MHz
34.33
34.33
34.33
34.33
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.66
35.66
35.66
35.66
35.66
35.66
35.66
35.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
%
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
103.00 68.66
206.00 68.66
137.33 68.66
171.67 68.66
228.89 68.66
412.00 68.66
274.67 68.66
343.33 68.66
105.00 69.99
210.00 69.99
140.00 69.99
175.00 69.99
233.33 69.99
420.00 69.99
280.00 69.99
350.00 69.99
107.00 71.33
214.00 71.33
142.66 71.33
178.34 71.33
237.78 71.33
428.00 71.33
285.34 71.33
356.66 71.33
110.00 73.33
220.00 73.33
146.66 73.33
183.34 73.33
244.44 73.33
440.00 73.33
293.34 73.33
366.66 73.33
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1236A—08/06/07
6
Integrated
Circuit
ICS952906A
Systems, Inc.
Table1: QuadRom Frequency Selection Table (Continued)
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
AGP
PCI
Spread
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0 MHz
MHz
63.33
MHz
31.66
31.66
31.66
31.66
31.66
31.66
31.66
31.66
30.00
30.00
30.00
30.00
30.00
30.00
30.00
30.00
28.33
28.33
28.33
28.33
28.33
28.33
28.33
28.33
26.66
26.66
26.66
26.66
26.66
26.66
26.66
26.66
%
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
95.00
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
190.00 63.33
126.66 63.33
158.34 63.33
211.11 63.33
380.00 63.33
253.34 63.33
316.66 63.33
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
90.00
59.99
180.00 59.99
120.00 59.99
150.00 59.99
200.00 59.99
360.00 59.99
240.00 59.99
300.00 59.99
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
85.00
56.66
170.00 56.66
113.33 56.66
141.67 56.66
188.89 56.66
340.00 56.66
226.67 56.66
283.33 56.66
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
80.00
53.33
160.00 53.33
106.66 53.33
133.34 53.33
177.78 53.33
320.00 53.33
213.34 53.33
266.66 53.33
1236A—08/06/07
7
Integrated
Circuit
ICS952906A
Systems, Inc.
Table1: QuadRom Frequency Selection Table (Continued)
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
AGP
PCI
Spread
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0 MHz
MHz
MHz
38.33
38.33
38.33
38.33
38.33
38.33
38.33
38.33
40.00
40.00
40.00
40.00
40.00
40.00
40.00
40.00
26.00
26.00
26.00
26.00
26.00
26.00
26.00
26.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
%
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
115.00 76.66
230.00 76.66
153.33 76.66
191.67 76.66
255.55 76.66
460.00 76.66
306.67 76.66
383.33 76.66
115.00 79.99
230.00 79.99
153.33 79.99
191.67 79.99
255.55 79.99
460.00 79.99
306.67 79.99
383.33 79.99
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
78.00
51.99
156.00 51.99
104.00 51.99
130.00 51.99
173.33 51.99
312.00 51.99
208.00 51.99
260.00 51.99
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75.00
50.00
150.00 50.00
100.00 50.00
125.00 50.00
166.67 50.00
300.00 50.00
200.00 50.00
250.00 50.00
1236A—08/06/07
8
Integrated
Circuit
ICS952906A
Systems, Inc.
I2C Table: Frequency Select Register
Control
Function
Byte 0
Pin #
Name
Type
0
1
PWD
Frequency H/W IIC
-
Latch Inputs
IIC
FS Source
RW
0
Bit 7
Select
-
-
-
-
-
-
-
FS6
FS5
FS4
FS3
FS2
FS1
FS0
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See Table 1: QuadRom Frequency
Selection Table
Freq Select Bit 0
I2C Table: Spreading and Device Behavior Control Register
Control
Byte 1
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
SS1
SS0
SS_EN
WDS_EN
Reserved
Spread Select 1**
Spread Select 0**
Spread Enable Control
WD Soft Reset Enable
Reserved
RW
RW
RW
RW
RW
00 = 0.20%
01 = 0.25%
10 = 0.35%
Reserved
OFF
0
1
1
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ON
ON
-
OFF
-
CPUCLKT/C_ITP,
CPU1T/C, CPU0T/C
CPUCLKT/C_1
45, 44
Disable
Enable
Output Control
RW
1
Bit 2
42,41
39, 38
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
Bit 1
Bit 0
CPUCLKT/C_0
** Spread programming only applies for ROM table entries 0001000 to 0001011 and 0010000 to 0010111
I2C Table: Output Control Register
Control
Byte 2
Pin #
Name
Type
0
1
PWD
Function
36
35
25MHz_0
25MHz_1
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
Bit 7
Bit 6
0: CPUT Driven during
PD#; 1: Tri-stated
-
Driven
Hi-Z
CPUT Stop Mode
RW
0
Bit 5
-
26
-
42,41
39, 38
Reserved
3V66_1
Reserved
CPUCLKT/C_1
CPUCLKT/C_0
Reserved
Output Control
Reserved
Output Stop Control
Output Stop Control
RW
RW
RW
RW
RW
-
-
1
1
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Disable
-
Free Run
Free Run
Enable
-
Stoppable
Stoppable
I2C Table: Output Control Register
Control
Function
Byte 3
Pin #
Name
Type
0
1
PWD
-
ASEL1
3V66/PCI Freq Select
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
See Table 5: Async AGP/PCI Freq Table
0
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
16
15
14
13
12
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Output Control
1236A—08/06/07
9
Integrated
Circuit
ICS952906A
Systems, Inc.
Table 5: Asynchronous 3V66/PCI Frequency Table
Byte6 Bit7
Byte3 Bit7
3V66/PCI Frequency
66.66/33.33
0
0
1
0
1
0
80.00/40.00
72.73/36.36
I2C Table: Output Control Register
Control
Function
Byte 4
Pin #
Name
Type
0
1
PWD
48MHz_0
2x output drive
-
-
2x drive
AGP/2
normal
0=2x drive
RW
RW
1
0
Bit 7
Bit 6
PCI Async Divider
Cntr
PLL3 Freq/24
PCI ADIV
-
29
-
9
8
Reserved
3V66_0
Reserved
PCICLK_F2
PCICLK_F1
PCICLK_F0
Reserved
Output Control
Reserved
Output Control
Output Control
RW
RW
RW
RW
RW
RW
-
-
1
1
1
1
1
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Disable
-
Disable
Disable
Disable
Enable
-
Enable
Enable
Enable
7
Output Control
I2C Table: Reserved Register
Control
Function
Reserved
Byte 5
Pin #
Name
Type
0
1
PWD
-
-
Reserved
Mode Sel1
Mode Sel0
3V66_2
M PLL2 Div3
M PLL2 Div2
M PLL2 Div1
M PLL2 Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL Mode Selection
Bits
See Table 4: Mode Selection Table
Disable Enable
-
25
-
-
-
0
1
X
X
X
X
Output Control
M Divider
Programming bits for
Async mode 2&3
The decimal representation of M PLL2 Div
(3:0) + 2 is equal to REF divider value for
PLL2
-
Table 4: Mode Selection Table
Mode
Standard Overclock Mode(I)
Byte 5 bit(6:5) = 00
PLL3
CPU Overclock Mode(II)
Byte 5 bit(6:5) = 01
PLL3
Graphic Overclock Mode(III)
Byte 5 bit(6:5) = 10
IIC Control
25MHz From?
3V66/PCI From?
Spreading
PLL1
PLL1 (Needed to be align w/ CPU) PLL3
CPU/3V66/PCI have spread Only CPU clocks have spread.
PLL3
Only CPU clocks have spread.
I2C Table: Vendor & Revision ID Register
Control
Function
Byte 6
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
ASEL0
3V66/PCI Freq Select
RW
RW
RW
RW
RW
RW
RW
RW
See Table 5: Async AGP/PCI Freq Table
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N PLL2 Div6
N PLL2 Div5
N PLL2 Div4
N PLL2 Div3
N PLL2 Div2
N PLL2 Div1
N PLL2 Div0
X
X
X
X
X
X
X
N Divider
Programming bits for
Async mode 2&3
The decimal representation of N PLL2 Div
(6:0) + 8 is equal to VCO divider value for
PLL2.
1236A—08/06/07
10
Integrated
Circuit
ICS952906A
Systems, Inc.
I2C Table: Vendor & Revision ID Register
Control
Function
Byte 7
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
0
0
1
I2C Table: Byte Count Register
Control
Function
Byte 8
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
Byte Count
Programming b(7:0)
I2C Table: Watchdog Timer Register
Control
Function
Byte 9
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
WD Timer Bit 7
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
0
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Timer Bit 6
WD Timer Bit 5
WD Timer Bit 4
WD Timer Bit 3
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
These bits represent X*290ms the
watchdog timer waits before it goes to
alarm mode. Default is 11 x 293ms =
3.2s.
I2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Byte 10
Pin #
Name
Type
0
1
PWD
Function
M/N Programming
Enable
-
-
-
Disable
Disable
Enable
Enable
M/NEN
WDEN
RW
R
0
0
0
Bit 7
Watchdog Enable
WD Safe Frequency
Mode
Bit 6
Bit 5
Latched FS/Byte0
WD B10 b(4:0)
WDFSEN
RW
-
-
-
-
-
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
RW
RW
RW
RW
RW
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
1236A—08/06/07
11
Integrated
Circuit
ICS952906A
Systems, Inc.
I2C Table: VCO Frequency Control Register
Control
Function
Byte 11
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
RW
RW
RW
RW
RW
RW
RW
RW
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(8:0)+8] /
[MDiv(6:0)+2]
X
X
X
X
X
X
M Divider
Programming bits
I2C Table: VCO Frequency Control Register
Control
Function
Byte 12
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(8:0)+8] /
[MDiv(6:0)+2]
N Divider
Programming b(8:0)
I2C Table: Spread Spectrum Control Register
Control
Function
Byte 13
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(7:0)
I2C Table: Spread Spectrum Control Register
Control
Function
Reserved
Reserved
Byte 14
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
R
R
-
-
-
-
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(13:8)
SSP8
1236A—08/06/07
12
Integrated
Circuit
ICS952906A
Systems, Inc.
I2C Table: Output Divider Control Register
Control
Function
Byte 15
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
25MHz Div3
25Mhz Div2
25MHz Div1
25MHz Div0
CPU Div3
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2
0001:/3
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
X
X
X
X
X
X
X
X
Bit 7
25MHz Divider Ratio
Programming Bits
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0010:/5 0110:/10 1010:/20 1110:/40
0011:/7 0111:/14 1011:/28 1111:/56
0000:/2
0001:/3
0010:/5 0110:/10 1010:/20 1110:/40
0011:/7 0111:/14 1011:/28 1111:/56
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
CPU Div2
CPU Div1
CPUDivider Ratio
Programming Bits
CPU Div0
I2C Table: Output Divider Control Register
Control
Function
Byte 16
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
3V66Div3
3V66Div2
3V66Div1
3V66Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
0000:/2
0001:/3
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
3V66/PCI Divider Ratio
Programming Bits for
Mode 1
0010:/5 0110:/10 1010:/20 1110:/40
0011:/7 0111:/14 1011:/28 1111:/56
I2C Table: Output Divider Control Register
Control
Function
Byte 17
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
CPUINV
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
X
X
X
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU Phase Invert
Reserved
Default
Inverse
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
I2C Table: Group Skew Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 18
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
1236A—08/06/07
13
Integrated
Circuit
ICS952906A
Systems, Inc.
I2C Table: Group Skew Control Register
Control
Function
Byte 19
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
3V66Skw3
3V66Skw2
3V66Skw1
3V66Skw0
PCISkw3
PCISkw2
PCISkw1
PCISkw0
RW
RW
RW
RW
RW
RW
RW
RW
0000:0 0100:150 1000:300 1100:450
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
0000:0 0100:150 1000:300 1100:450
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
0
0
0
0
1
1
0
0
Bit 7
CPU-3V66 7 Step
Skew Control (ps)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU-PCI 7 Step Skew
Control (ps)
I2C Table: Group Skew Control Register
Control
Function
Byte 20
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
PCISkw1
PCISkw0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0000:0 0100:150 1000:300 1100:450
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
1
1
0
0
0
0
0
0
Bit 7
CPU-PCI F(2:0) 7 Step
Skew Control (ps)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
I2C Table: Slew Rate Control Register
Control
Function
PCICLKF (2:0)
Strength Control
Byte 21
Pin #
Name
Type
RW
0
1
PWD
-
-
-
-
-
-
-
-
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
-
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
-
1
1
1
1
1
1
1
1
PCIFStr1
PCIFStr0
PCIFStr1
PCIFStr0
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK (6) Strength
Control
RW
Reserved
Reserved
RW
RW
RW
RW
-
-
00 = 0.70X
01 = 0.80X
10 = 0.90X
11 = 1.00X
AGPStr1
AGPStr0
AGPCLK Strength
Control
I2C Table: Slew Rate Control Register
Control
Function
Byte 22
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
RW
RW
00 = Medium
01 = Weak
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
10 = Strong
11 = N/A
1
0
1
1
1
1
1
1
Bit 7
REF_Slw
REF Slew Rate Control
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
PCIFStr1
PCIFStr0
PCIFStr1
PCIFStr0
PCIFStr1
PCIFStr0
PCICLK (5) Strength
Control
RW
RW
RW
PCICLK (4:2) Strength
Control
PCICLK (1:0) Strength
Control
1236A—08/06/07
14
Integrated
Circuit
ICS952906A
Systems, Inc.
I2C Table: Output Control Register
Control
Byte 23
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
-
-
-
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
0
0
48MHz_0
24_48MHz
REF1
REF0
REF2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
48MHz_1
Reserved
-
-
Reserved
Reserved
I2C Table: Read Back Register
Control
Function
WD Hard Alarm Status
Read back
WD Soft Alarm Status
Read back
Byte 24
Pin #
Name
Type
R
0
-
1
-
PWD
X
-
-
WDHRB
WDSRB
Bit 7
-
-
R
X
Bit 6
-
-
-
-
-
-
Reserved
FS4RB
FS3RB
FS2RB
FS1RB
FS0RB
Reserved
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
X
X
X
X
X
FS0 Read back
1236A—08/06/07
15
Integrated
Circuit
ICS952906A
Systems, Inc.
Absolute Maximum Ratings
Core Operating Voltage . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Operating Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V
Lo gic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
VIH
VMID
VIL
3.3V +/-5%
3.3V +/-5%
2
VDD + 0.3
V
V
1
VSS -0.3
-5
1.8
0.8
5
3.3V +/-5%
V
IIH
VIN = VDD
uA
VIN = 0 V; Inputs with no pull-
up resistors
IIL1
IIL2
IDD3.3OP
IDD3.3PD
-5
uA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
Powerdown Current
Full Active, CL = Full load;
350
mA
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
35
12
mA
mA
MHz
nH
pF
Input Frequency3
Pin Inductance1
Fi
14.31818
3
1
1
1
1
Lpin
7
5
6
5
CIN
Logic Inputs
Input Capacitance1
COUT
CINX
Output pin capacitance
pF
X1 & X2 pins
pF
From VDD Power-Up or de-
assertion of PD# to 1st clock.
Triangular Modulation
Clk Stabilization1,2
TSTAB
1.8
33
ms
1,2
1
Modulation Frequency
30
kHz
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
1236A—08/06/07
16
Integrated
Circuit
ICS952906A
Systems, Inc.
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL =2pF
PARAMETER
SYMBOL
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
Zo1
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1
1
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
1
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
tr
tf
d-tr
d-tf
see Tperiod min-max values
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
-300
175
175
300
700
700
125
125
ppm
ps
ps
ps
ps
1,2
1
1
1
1
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
100
125
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
1236A—08/06/07
17
Integrated
Circuit
ICS952906A
Systems, Inc.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Output High Voltage
Output Low Voltage
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
IOH = -1 mA
MIN
-300
2.4
TYP
MAX
300
UNITS Notes
ppm
V
1,2
VOH
VOL
IOL = 1 mA
0.55
-33
V
V
OH@MIN = 1.0 V
OH@MAX = 3.135 V
OL @MIN = 1.95 V
-33
30
mA
mA
mA
Output High Current
Output Low Current
IOH
IOL
V
V
V
OL@MAX = 0.4 V
38
4
4
mA
V/ns
V/ns
ns
Edge Rate
Edge Rate
Rise Time
Rising edge rate
Falling edge rate
1
1
0.5
1
1
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2
Fall Time
Duty Cycle
Skew
0.5
45
2
ns
%
1
1
1
1
dt1
tsk1
VT = 1.5 V
VT = 1.5 V
55
250
250
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V 3V66
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
300
UNITS Notes
Long Accuracy
Output High Voltage
Output Low Voltage
ppm
VOH
VOL
see Tperiod min-max values
IOH = -1 mA
-300
2.4
ppm
V
1,2
IOL = 1 mA
0.55
-33
V
V
OH@MIN = 1.0 V
-33
30
mA
mA
mA
mA
V/ns
V/ns
ns
Output High Current
Output Low Current
IOH
IOL
VOH@MAX = 3.135 V
VOL@MIN = 1.95 V
VOL@MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
38
4
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
1
1
1
1
1
1
1
1
1
4
2
tr1
tf1
0.5
0.5
45
2
ns
dt1
55
500
250
%
tsk1
VT = 1.5 V
ps
Jitter
tjcyc-cyc
VT = 1.5 V 3V66
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
1236A—08/06/07
18
Integrated
Circuit
ICS952906A
Systems, Inc.
Electrical Characteristics - 48MHz, 24MHz
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
Long Accuracy
Output High Voltage
Output Low Voltage
ppm
VOH
VOL
see Tperiod min-max values
IOH = -1 mA
-200
2.4
200
0.55
-33
ppm
V
1,2
IOL = 1 mA
V
V
OH@MIN = 1.0 V
VOH@MAX = 3.135 V
OL @MIN = 1.95 V
OL@MAX = 0.4 V
-33
30
mA
mA
mA
mA
V/ns
V/ns
Output High Current
Output Low Current
IOH
IOL
V
V
38
2
Edge Rate
Edge Rate
Rising edge rate
Falling edge rate
1
1
1
1
2
Rise Time
Fall Time
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
1
1
2
2
ns
ns
%
1
1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Duty Cycle
dt1
45
55
125us period jitter
(8kHz frequency modulation
amplitude)
Long Term Jitter
6
ns
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
ppm
CONDITIONS
MIN TYP MAX
UNITS Notes
Long Accuracy
Output High Voltage
see Tperiod min-max values
IOH = -1 mA
-300
2.4
300
ppm
V
1
1
VOH
1
Output Low Voltage
IOL = 1 mA
0.4
-23
V
VOL
V OH@MIN = 1.0 V, V OH@MAX
3.135 V
VOL @MIN = 1.95 V, VOL @MAX
0.4 V
=
1
Output High Current
-29
29
mA
IOH
=
1
Output Low Current
27
mA
IOL
1
Rise Time
Fall Time
Skew
VOL = 0.4 V, VOH = 2.4 V
1
1
2
2
ns
ns
ps
%
1
1
1
1
1
tr1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
tf1
1
500
55
tsk1
1
Duty Cycle
Jitter
dt1
VT = 1.5 V
45
1
tjcyc-cyc
VT = 1.5 V
1000
ps
1Guaranteed by design, not 100% tested in production.
1236A—08/06/07
19
Integrated
Circuit
ICS952906A
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
1236A—08/06/07
20
Integrated
Circuit
ICS952906A
Systems, Inc.
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
e
SEEAATTIINNGG
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952906AFLFT
Example:
ICS XXXX A F LF- T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator
Device Type
Prefix
ICS = Standard Device
1236A—08/06/07
21
Integrated
Circuit
ICS952906A
Systems, Inc.
6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
(240 mil)
(20 mil)
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
α
D
L
0.45
0.75
.018
.030
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
A
aaa
A2
VARIATIONS
A1
D mm.
D (inch)
- C -
N
MIN
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
48
12.40
b
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10-0039
Ordering Information
ICS952906AGLFT
Example:
ICS XXXX A G LF- T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator
Device Type
Prefix
ICS = Standard Device
1236A—08/06/07
22
Integrated
Circuit
ICS952906A
Systems, Inc.
Revision History
Rev.
N/A
0.1
Issue Date Description
06/15/06 Initial Release
08/29/06 Updated I2C
Page #
-
13
1. Updated 48/24MHz Electrical Characteristics
08/06/07 2. Final release
A
19
1236A—08/06/07
23
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