952606FT_技术文档

Integrated

Circuit

ICS952606

Systems, Inc.

Programmable Timing Control Hub™ for Next Gen P4™ processor

Recommended Application:

CK409 48-pin part

Output Features:

Features/Benefits:

•

Supports tight ppm accuracy clocks for Serial-ATA

Supports spread spectrum modulation, 0 to -0.5%

down spread and +/- 0.25% center spread

•

2 - 0.7V current-mode differential CPU pairs

1 - 0.7V current-mode differential CPU pairs for ITP

•

Supports CPU clks up to 400MHz in test mode

Uses external 14.318MHz crystal

•

1 - 0.7V current-mode differential SRC pair

9 - PCI (33MHz)

Supports undriven differential CPU, SRC pair in PD#

for power management.

•

1 - USB, 48MHz

1 - DOT, 48MHz

2 - REF, 14.318MHz

3 - 3V66, 66.66MHz

•

1 - 3V66/VCH, selectable 48MHz or 66MHz

Key Specifications:

•

CPU/SRC outputs cycle-cycle jitter < 125ps

3V66 outputs cycle-cycle jitter < 250ps

Pin Configuration

*FSA/REF0

*FSB/REF1

VDDREF

X1

X2

GND

PCICLK_F0

PCICLK_F1

PCICLK_F2

1

2

3

4

5

6

7

8

9

48 VDDA

47 GND

46 IREF

•

PCI outputs cycle-cycle jitter < 250ps

CPU outputs skew: < 100ps

45 CPUCLKT_ITP

44 CPUCLKC_ITP

43 GND

42 CPUCLKT1

41 CPUCLKC1

40 VDDCPU

39 CPUCLKT0

38 CPUCLKC0

37 GND

36 SRCCLKT

35 SRCCLKC

34 VDD

33 Vtt_Pwrgd#

32 SDATA

+/- 300ppm frequency accuracy on CPU & SRC clocks

Functionality

FS2

U

DOT

MHz

SB/

VDDPCI 10

GND 11

CPU

SRC

MHz

3V66

MHz MHz

PCI

REF

MHz

B6b5 FS_A FS_B MHz

0

1

0

1

0

1

0

1

0

1

0

1

100.00 100/200 66.66 33.33 14.318 48.00

200.00 100/200 66.66 33.33 14.318 48.00

133.33 100/200 66.66 33.33 14.318 48.00

166.66 100/200 66.66 33.33 14.318 48.00

200.00 100/200 66.66 33.33 14.318 48.00

400.00 100/200 66.66 33.33 14.318 48.00

266.66 100/200 66.66 33.33 14.318 48.00

333.33 100/200 66.66 33.33 14.318 48.00

PCICLK0 12

PCICLK1 13

PCICLK2 14

PCICLK3 15

VDDPCI 16

GND 17

PCICLK4 18

PCICLK5 19

PD# 20

0

1

31 SCLK

30 3V66_0

29 3V66_1

48MHz_DOT 21

48MHz_USB 22

GND 23

28 GND

27 VDD3V66

26 3V66_2

VDD48 24

25 3V66_3/VCH

**120KW pull-down

48-pin SSOP

0717F—06/10/05

Integrated

Circuit

ICS952606

Systems, Inc.

Pin Description

PIN #

PIN NAME

*FSA/REF0

*FSB/REF1

VDDREF

X1

PIN TYPE

DESCRIPTION

1

2

3

4

5

6

7

8

I/O

PWR

IN

Frequency select latch input pin / 14.318 MHz reference clock.

Ref, XTAL power supply, nominal 3.3V

Crystal input, Nominally 14.318MHz.

Crystal output, Nominally 14.318MHz

Ground pin.

Free running PCI clock not affected by PCI_STOP# .

Power supply for PCI clocks, nominal 3.3V

Ground pin.

X2

GND

OUT

PWR

OUT

PWR

OUT

PWR

OUT

PCICLK_F0

PCICLK_F1

PCICLK_F2

VDDPCI

GND

PCICLK0

PCICLK1

PCICLK2

PCICLK3

VDDPCI

GND

9

10

11

12

13

14

15

16

17

18

19

PCI clock output.

Power supply for PCI clocks, nominal 3.3V

Ground pin.

PCICLK4

PCICLK5

PCI clock output.

Asynchronous active low input pin, with 120Kohm internal pull-up

resistor, used to power down the device. The internal clocks are

disabled and the VCO and the crystal are stopped.

48MHz clock output.

Ground pin.

20

PD#

IN

21

22

23

24

48MHz_DOT

48MHz_USB

GND

OUT

PWR

VDD48

Power pin for the 48MHz output.3.3V

0717F—06/10/05

2

Integrated

Circuit

ICS952606

Systems, Inc.

Pin Description (Continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

30

25

26

27

28

29

30

31

32

3V66_0

OUT

PWR

OUT

IN

3.3V 66.66MHz clock output

3.3V 66.66MHz clock output / 48MHz VCH clock output.

3.3V 66.66MHz clock output

Power pin for the 3.3V 66MHz clocks.

Ground pin.

3.3V 66.66MHz clock output

Clock pin of SMBus circuitry, 5V tolerant.

Data pin for SMBus circuitry, 5V tolerant.

3V66_3/VCH

3V66_2

VDD3V66

GND

3V66_1

3V66_0

SCLK

SDATA

I/O

This 3.3V LVTTL input is a level sensitive strobe used to determine

when latch inputs are valid and are ready to be sampled. This is an

active low input.

33

Vtt_Pwrgd#

IN

34

35

VDD

PWR

OUT

Power supply, nominal 3.3V

Complement clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

SRCCLKC

True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

Ground pin.

36

37

SRCCLKT

GND

OUT

PWR

Complementary clock of differential pair CPU outputs. These are

current mode outputs. External resistors are required for voltage bias.

38

CPUCLKC0

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

Supply for CPU clocks, 3.3V nominal

39

40

CPUCLKT0

VDDCPU

OUT

PWR

Complementary clock of differential pair CPU outputs. These are

current mode outputs. External resistors are required for voltage bias.

41

CPUCLKC1

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

Ground pin.

42

43

CPUCLKT1

GND

OUT

PWR

Complementary clock of differential pair CPU outputs. These are

current mode outputs. External resistors are required for voltage bias.

44

45

CPUCLKC_ITP

CPUCLKT_ITP

OUT

True clock of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the appropriate current. 475 ohms is the

standard value.

46

IREF

OUT

47

48

GND

VDDA

PWR

Ground pin.

3.3V power for the PLL core.

0717F—06/10/05

3

Integrated

Circuit

ICS952606

Systems, Inc.

General Description

ICS952606 is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single

chip solution for next generation P4 Intel processors and Intel chipsets. ICS952606 is driven with a 14.318MHz crystal. It

generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.

Block Diagram

Frequency

Dividers

48MHz, USB, DOT, VCH

PLL2

X1

X2

XTAL

REF (1:0)

CPUCLKT (1:0)

CPUCLKC (1:0)

SRCCLKT0

Programmable

Spread

Programmable

Frequency

Dividers

STOP

Logic

SRCCLKC0

3V66(3:0)

SCLK

SDATA

PLL1

PCICLK_F (2:0)

VTTPWRGD#

PD#

Control

Logic

PCICLK (5:0)

CPUCLKT_ITP

CPUCLKC_ITP

FS_A

FS_B

I REF

Power Groups

Pin Number

Description

VDD

3

GND

6

Xtal, Ref

27

28

3V66 [0:3]

10,16

34

11,17

37

PCICLK outputs

SRCCLK outputs

48

24

--

47

23

47

Master clock, CPU Analog

48MHz, Fix Digital, Fix Analog

IREF

40

43

CPUCLK clocks

0717F—06/10/05

4

Integrated

Circuit

ICS952606

Systems, Inc.

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD_A

VDD_In

Ts

Tambient

Tcase

3.3V Core Supply Voltage

3.3V Logic Input Supply Voltage

Storage Temperature

V_{DD +}0.5V

150

V

°C

-0.5

-65

0

Ambient Operating Temp

Case Temperature

Input ESD protection

70

115

human body model

ESD prot

2000

V

Electrical Characteristics - Input/Supply/Common Output Parameters

T_A= 0 - 70°C; Supply Voltage V_DD= 3.3 V +/-5%

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

SYMBOL

CONDITIONS

3.3V +/-5%

MIN

2

TYP

MAX

V_DD+ 0.3

0.8

UNITS NOTES

V_IH

V_IL

I_IH

V

V_SS

0.3

-5

-

V_IN= V_DD

V_IN= 0 V; Inputs with no pull-up

resistors

5

uA

I_IL1

-5

Input Low Current

V_IN= 0 V; Inputs with pull-up

resistors

I_IL2

-200

uA

I_DD3.3OP

I_DD3.3PD

Full Active, C_L= Full load;

Operating Supply Current

Powerdown Current

260.000

350

mA

all diff pairs driven

all differential pairs tri-stated

V_DD= 3.3 V

31.000

0.300

14.31818

35

12

mA

MHz

nH

pF

Input Frequency³

Pin Inductance¹

F_i

L_pin

C_IN

C_OUT

C_INX

3

1

7

5

6

5

Logic Inputs

Output pin capacitance

Input Capacitance¹

pF

X1 & X2 pins

From VDD Power-Up or de-

assertion of PD# to 1st clock.

Triangular Modulation

CPU output enable after

PD# de-assertion

Clk Stabilization^1,2

Modulation Frequency

Tdrive_PD#

T_STAB

1.8

33

ms

kHz

us

1,2

1

30

300

1

Tfall_Pd#

Trise_Pd#

PD# fall time of

PD# rise time of

¹Guaranteed by design, not 100% tested in production.

²See timing diagrams for timing requirements.

5

ns

1

2

³Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet

ppm frequency accuracy on PLL outputs.

0717F—06/10/05

5

Integrated

Circuit

ICS952606

Systems, Inc.

Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair

T_A= 0 - 70°C; V_DD= 3.3V +/-5%; C_L=2pF

PARAMETER

SYMBOL

CONDITIONS

V_O= V_x

MIN

TYP

MAX

850

UNITS NOTES

Current Source Output

Impedance

Zo¹

3000

Ω

1

Statistical measurement on single

ended signal using oscilloscope

math function.

Voltage High

Voltage Low

VHigh

VLow

660

749

3

1

mV

-150

150

Measurement on single ended

signal using absolute value.

Max Voltage

Min Voltage

Crossing Voltage (abs)

Vovs

Vuds

Vcross(abs)

756

-7

350

1150

1

mV

-300

250

550

140

300

Variation of crossing over all

edges

see Tperiod min-max values

200MHz nominal

Crossing Voltage (var)

Long Accuracy

d-Vcross

ppm

12

1

-300

ppm

ns

ps

1,2

2

1,2

1

4.9985 5.000 5.0015

4.9985 5.0266

5.9982 6.000 6.0018

5.9982 6.0320

7.4978 7.500 7.5023

7.4978 5.4000

9.9970 10.000 10.0030

200MHz spread

166.66MHz nominal

166.66MHz spread

133.33MHz nominal

133.33MHz spread

100.00MHz nominal

100.00MHz spread

Average period

Tperiod

9.9970

4.8735

5.8732

7.3728

9.8720

175

10.0533

200MHz nominal

166.66MHz nominal/spread

133.33MHz nominal/spread

100.00MHz nominal/spread

V_OL= 0.175V, V_OH= 0.525V

T_absmin

Absolute min period

t_r

t_f

d-t_r

d-t_f

Rise Time

Fall Time

Rise Time Variation

Fall Time Variation

279

280

30

700

125

V_OH= 0.525V V_OL= 0.175V

175

ps

30

Measurement from differential

wavefrom

V_T= 50%

Measurement from differential

wavefrom

d_t3

t_sk3

Duty Cycle

Skew

45

50.9

8

55

%

ps

1

100

125

t_jcyc-cyc

Jitter, Cycle to cycle

40

¹Guaranteed by design, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at

14.31818MHz

SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.

0717F—06/10/05

6

Integrated

Circuit

ICS952606

Systems, Inc.

Electrical Characteristics - 3V66 Mode: 3V66 [3:0]

T_A= 0 - 70°C; V_DD= 3.3V +/-5%; C_L= 10-30 pF (unless otherwise specified)

PARAMETER

Long Accuracy

SYMBOL

ppm

CONDITIONS

see Tperiod min-max values

66.66MHz output nominal

66.66MHz output spread

I_OH= -1 mA

MIN

-300

14.9955

2.4

TYP

15

MAX

300

15.0045

15.0799

UNITS Notes

ppm

ns

1,2

2

T_period

Clock period

ns

2

V_OH

V_OL

Output High Voltage

Output Low Voltage

V

I_OL= 1 mA

V _OH@MIN= 1.0 V

0.55

-33

30

mA

V/ns

ns

I_OH

I_OL

Output High Current

Output Low Current

V

_OH@MAX= 3.135 V

_{OL @MIN}= 1.95 V

V_OL@MAX= 0.4 V

Rising edge rate

Falling edge rate

38

4

2

Edge Rate

Rise Time

Fall Time

1

0.5

1

t_r1

t_f1

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

1.79

1.69

49.9

80

ns

d_t1

V_T= 1.5 V

Duty Cycle

Skew

45

55

%

ps

1

t_sk1

250

t_jcyc-cyc

V_T= 1.5 V 3V66

Jitter

172

¹Guaranteed by design, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at

14.31818MHz

Electrical Characteristics - PCICLK

T_A= 0 - 70°C; V_DD= 3.3V +/-5%; C_L= 10-30 pF (unless otherwise specified)

PARAMETER

Long Accuracy

Clock period

SYMBOL

CONDITIONS

MIN

-300

TYP MAX

300

UNITS Notes

ppm

see Tperiod min-max values

33.33MHz output nominal

33.33MHz output spread

I_OH= -1 mA

ppm

ns

1,2

2

29.9910 30 30.0090

29.9910

2.4

T_period

30.1598

0.55

-33

ns

2

V_OH

V_OL

Output High Voltage

Output Low Voltage

V

mA

I_OL= 1 mA

V

_OH@MIN= 1.0 V

_OH@MAX= 3.135 V

_OL@MIN= 1.95 V

_OL@MAX= 0.4 V

-33

30

I_OH

I_OL

Output High Current

Output Low Current

V

38

Edge Rate

Rise Time

Fall Time

Duty Cycle

Skew

Rising edge rate

1

0.5

45

4

2

V/ns

ns

%

1

Falling edge rate

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

t_r1

t_f1

d_t1

1.79

1.69

51.2

59

2

55

500

250

t_sk1

V_T= 1.5 V

ps

t_jcyc-cyc

V_T= 1.5 V 3V66

Jitter

140

ps

¹Guaranteed by design, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is

at 14.31818MHz

0717F—06/10/05

7

Integrated

Circuit

ICS952606

Systems, Inc.

Electrical Characteristics - 48MHz DOT Clock

T_A= 0 - 70°C; V_DD= 3.3V +/-5%; C_L= 5-10 pF (unless otherwise specified)

PARAMETER

Long Accuracy

Clock period

SYMBOL

ppm

T_period

V_OH

CONDITIONS

see Tperiod min-max values

48.008 MHz output nominal

I_OH= -1 mA

MIN

-200

20.8257

2.4

TYP MAX

200

UNITS Notes

ppm

ns

1,2

2

20.8340

Output High Voltage

V

Output Low Voltage

V_OL

I_OL= 1 mA

0.55

-33

V

_OH@MIN= 1.0 V

-33

30

mA

V/ns

Output High Current

I_OH

V_OH@MAX= 3.135 V

V_{OL @MIN}= 1.95 V

Output Low Current

I_OL

V

_OL@MAX= 0.4 V

Rising edge rate

Falling edge rate

38

4

Edge Rate

2

1

4

Rise Time

t_r1

V_OL= 0.4 V, V_OH= 2.4 V

0.5

0.87

1

ns

1

Fall Time

t_f1

V_OH= 2.4 V, V_OL= 0.4 V

0.5

45

0.89

52.3

1

ns

%

1

Duty Cycle

d_t1

V_T= 1.5 V

125us period jitter

(8kHz frequency modulation

amplitude)

55

Long Term Jitter

0.64

2

ns

1

¹Guaranteed by design, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is

at 14.31818MHz

0717F—06/10/05

8

Integrated

Circuit

ICS952606

Systems, Inc.

Electrical Characteristics - VCH, 48MHz, 48MHz, USB

T_A= 0 - 70°C; V_DD= 3.3V +/-5%; C_L= 10-20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS Notes

Long Accuracy

Clock period

Output High Voltage

Output Low Voltage

ppm

T_period

V_OH

see Tperiod min-max values

48.008 MHz output nominal

I_OH= -1 mA

-200

20.8257

2.4

200

20.8340 ns

V

ppm

1,2

2

V_OL

I_OL= 1 mA

0.55

V

_OH@MIN= 1.0 V

-33

30

mA

V/ns

Output High Current

Output Low Current

I_OH

I_OL

V

_OH@MAX= 3.135 V

-33

V_{OL @MIN}= 1.95 V

V_OL@MAX= 0.4 V

Rising edge rate

Falling edge rate

38

2

Edge Rate

1

2

Rise Time

Fall Time

t_r1

t_f1

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

1

1.45

1.37

52.5

2

ns

%

1

Duty Cycle

d_t1

V_T= 1.5 V

125us period jitter

(8kHz frequency modulation

amplitude)

45

55

Long Term Jitter

0.63

6

ns

1

¹Guaranteed by design, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref

output is at 14.31818MHz

0717F—06/10/05

9

Integrated

Circuit

ICS952606

Systems, Inc.

Electrical Characteristics - REF-14.318MHz

T_A= 0 - 70°C; V_DD= 3.3V +/-5%; C_L= 10-20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS Notes

Long Accuracy

Clock period

ppm

T_period

see Tperiod min-max values

14.31818 MHz output nominal 69.8270

-300

300

69.8550

ppm

ns

V

1

I_OH= -1 mA

I_OL= 1 mA

Output High Voltage

Output Low Voltage

2.4

V_OH

1

0.4

-23

V

V_OL

V _OH@MIN= 1.0 V, V _OH@MAX

=

1

Output High Current

Output Low Current

-29

29

mA

I_OH

3.135 V

V_{OL @MIN}= 1.95 V, V_{OL @MAX}= 0.4

1

27

I_OL

V

1

V_OL= 0.4 V, V_OH= 2.4 V

Rise Time

Fall Time

Skew

1

1.93

1.92

14

2

ns

ps

%

1

t_r1

1

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

t_f1

1

500

55

t_sk1

1

V_T= 1.5 V

Duty Cycle

45

53.8

d_t1

1

V_T= 1.5 V

Jitter

400 1000

ps

t_jcyc-cyc

¹Guaranteed by design, not 100% tested in production.

Group to Group Skews at Common Transition Edges

GROUP

3V66 to PCI

DOT-USB

DOT-VCH

SYMBOL

S_3V66-PCI

S_{DOT_USB}

CONDITIONS

3V66 (3:0) leads 33MHz PCI

180 degrees out of phase

in phase

MIN TYP MAX

UNITS

1.50

0.00

2

3.50

1.00

ns

S_{DOT_VCH}

0717F—06/10/05

10

Integrated

Circuit

ICS952606

Systems, Inc.

General I²C serial interface information for the ICS952606

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2_(H)

• ICS clock will acknowledge

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2_(H)

• ICS clock will acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will acknowledge

• Controller (host) sends the begining byte

location = N

• Controller (host) sends the data byte count = X

• ICS clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

• ICS clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3_(H)

• ICS clock will acknowledge

(see Note 2)

• ICS clock will send the data byte count = X

• ICS clock sends Byte N + X -1

• ICS clock will acknowledge each byte one at a time

• ICS clock sends Byte 0 through byte X (if X_(H)

was written to byte 8).

• Controller (host) sends a Stop bit

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Read Operation

Index Block Write Operation

Controller (Host)

ICS (Slave/Receiver)

Controller (Host)

ICS (Slave/Receiver)

T

starT bit

T

Slave Address D2_(H)

WR

WRite

WR

WRite

ACK

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

RT

Repeat starT

Slave Address D3_(H)

RD

ReaD

ACK

Data Byte Count = X

Beginning Byte N

ACK

Byte N + X - 1

ACK

P

stoP bit

Byte N + X - 1

N

P

Not acknowledge

stoP bit

0717F—06/10/05

11

Integrated

Circuit

ICS952606

Systems, Inc.

I²C Table: Read-Back Register

Byte 0

Bit 7

Pin #

Name

RESERVED

Control Function

Type

-

0

1

PWD

X

-

RESERVED

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

-

R

Freq Select 1 Read

-

Bit 1

Bit 0

FSB

FSA

R

X

READBACK of

CPU(2:0) Frequency

Back

Freq Select 0 Read

Back

I²C Table: Spreading and Device Behavior Control Register

Byte 1

Pin #

Name

SRC/SRC#

SRC

Control Function

Type

0

1

PWD

SRC Free-Running

STOPPAB

Bit 7

RW

FREE-RUN

0

Control

Output Control

LE

Enable

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RW

R

Disable

1

X

1

RESERVED

CPUT1/CPUC1

CPUT0/CPUC0

Output Control

RW

Disable

Enable

1

I²C Table: Output Control Register

Byte 2

Pin #

Name

Control Function

Type

0

1

PWD

SRC_PD#

Drive Mode

Bit 7

0: Driven in PD#

RW

Driven

Hi-Z

0

SRC_Stop#

Drive Mode

0: Driven in PCI_Stop#

(byte3bit7)

Bit 6

RW

Driven

Hi-Z

0

RESERVED

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RESERVED

CPUT1_PD# Drive Mode

CPUT0_PD# Drive Mode

RESERVED

0:driven in PD#

1: Tri-stated

RESERVED

-

X

0

X

RW

-

Driven

Hi-Z

RESERVED

I²C Table: Output Control Register

Byte 3

Pin #

Name

Control Function

PCI_Stop# Control

Type

0

1

PWD

Bit 7

PCI_Stop#

RW

Enable

Disable

1

0:all stoppable PCI are

stopped

RESERVED

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

RESERVED

PCICLK5

PCICLK4

PCICLK3

PCICLK2

PCICLK1

PCICLK0

-

X

1

Output Control

RW

Disable

Enable

Disable

Enable

Bit 0

0717F—06/10/05

12

Integrated

Circuit

ICS952606

Systems, Inc.

I²C Table: Output Control Register

Byte 4

Pin #

Name

Control Function

Type

0

1

PWD

48MHz_USB

2x output drive

48MHz_USB

RESERVED

PCICLKF2

Bit 7

0=2x drive

RW

2x drive

normal

1

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Output Control

RESERVED

RW

-

Disable

Enable

1

X

1

RESERVED

-

Output Control

RW

Stoppable Free-run

PCICLKF1

PCICLKF0

1

I²C Table: Output Control Register

Byte 5

Bit 7

Pin #

Name

Control Function

Output Control

Type

RW

0

1

PWD

1

DOT_48MHZ

CPU_T/C_ITP

3V66_3/VHC

Select

Disable

Enable

Bit 6

Bit 5

Output Select

RW

3V66

VCH

0

Bit 4

3V66_3/VHC

Output Control

RW

Disable

Enable

1

RESERVED

Bit 3

Bit 2

Bit 1

Bit 0

RESERVED

3V66_2

3V66_1

RESERVED

Output Control

-

X

1

RW

Disable

Enable

3V66_0

I²C Table: Output Control and Fix Frequecy Register

Byte 6

Bit 7

Bit 6

Bit 5

Pin #

Name

Test Clock Mode

RESERVED

Control Function

Test Clock Mode

-

Type

-

0

1

Enable

-

PWD

0

Disable

-

FS_A and FS_B

CPU *2 Test Clock

-

Normal

Test Mode

200MHz

0

Operation

SRC Frequency

Select

Down/Center

Spread Spectrum

Enable

Bit 4

Bit 3

Bit 2

SRC Frequency Select

Spread Spectrum Type

Spread Spectrum Mode

-

100MHz

0

Down

Spread

OFF

Center

Spread

ON

Bit 1

Bit 0

REF1

REF0

Output Control

RW

Disable

Enable

1

I²C Table: Vendor & Revision ID Register

Byte 7

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

Name

RID3

RID2

RID1

RID0

VID3

VID2

VID1

VID0

Control Function

Type

R

0

-

1

-

PWD

-

0

1

REVISION ID

VENDOR ID

0717F—06/10/05

13

Integrated

Circuit

ICS952606

Systems, Inc.

I²C Table: Byte Count Register

Byte 8

Pin #

Name

Control Function

Type

0

1

PWD

-

Bit 7

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

RW

-

0

1

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Writing to this register

will configure how

many bytes will be read

back, default is 08 = 8

bytes.

I²C Table: Reserved

Byte 9

Pin #

Name

Control Function

RESERVED

Type

0

1

PWD

X

-

RESERVED

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RESERVED

-

RESERVED

I²C Table: Reserved

Byte 10

Pin #

Name

Control Function

M/N prog Enable

RESERVED

Type

0

1

PWD

0

X

-

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

M/N prog Enable

RESERVED

-

Disable

Enable

RESERVED

I²C Table: VCO Frequency Control Register

Byte 11

Bit 7

Pin #

Name

N Div8

Control Function

N Divider Bit 8

Type

RW

0

-

1

-

PWD

X

-

The decimal

representation of M Div

(6:0) is equal to

reference divider value.

Default at power up =

latch-in or Byte 0 Rom

table.

Bit 6

M Div6

RW

-

X

-

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

M Div5

M Div4

M Div3

M Div2

M Div1

M Div0

RW

-

X

0717F—06/10/05

14

Integrated

Circuit

ICS952606

Systems, Inc.

I²C Table: VCO Frequency Control Register

Byte 12

Bit 7

Pin #

Name

N Div7

N Div6

N Div5

N Div4

N Div3

N Div2

N Div1

N Div0

Control Function

Type

RW

0

-

1

-

PWD

X

-

The decimal

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

representation of N Div

(8:0) is equal to VCO

divider value. Default

at power up = latch-in

or Byte 0 Rom table.

I²C Table: Spread Spectrum Control Register

Byte 13

Bit 7

Pin #

Name

SSP7

SSP6

SSP5

SSP4

SSP3

SSP2

SSP1

SSP0

Control Function

Type

RW

0

-

1

-

PWD

X

-

These Spread

Spectrum bits will

program the spread

pecentage. It is

recommended to use

ICS Spread % table for

spread programming.

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I²C Table: Spread Spectrum Control Register

Byte 14

Bit 7

Pin #

Name

Reserved

SSP13

SSP12

SSP11

SSP10

SSP9

Control Function

Reserved

Type

RW

0

-

1

-

PWD

0

X

-

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

It is recommended to

use ICS Spread %

table for spread

programming.

SSP8

0717F—06/10/05

15

Integrated

Circuit

ICS952606

Systems, Inc.

PD#, Power Down

PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.

When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start

without glitches.

PWRDWN#

CPU

CPU #

SRC

SRC#

3V66

PCIF/PCI USB/DOT

REF

14.318MHz

Low

Note

1

0

Normal

Normal Normal Normal 66MHz

33MHz

Low

48MHz

Low

Iref * 2 or

Float

Iref * 2

or Float

Float

Low

Notes:

1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.

2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.

PD# Assertion

PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be

held low on their next high to low transition.

All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register

determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.

When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at

2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will the

tristated.

PWRDWN#

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC#, 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

0717F—06/10/05

16

Integrated

Circuit

ICS952606

Systems, Inc.

PD# De-assertion

The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive

mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of

200mV in less than 300µs of PD# deassertion.

Tstable

<1.8mS

PWRDWN#

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC# 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

Tdrive_PwrDwn#

<300µS, >200mV

3V66_3/VCH Pin Functionality

The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is

3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output

will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising

edge of DOT_48 clock.

3V66

3V66_4/VCH

DOT_48

7.49nS min

0717F—06/10/05

17

Integrated

Circuit

ICS952606

Systems, Inc.

Shared Pin Operation -

Input/Output Pins

Figure 1 shows a means of implementing this function

when a switch or 2 pin header is used. With no jumper is

installed the pin will be pulled high. With the jumper in

place the pin will be pulled low. If programmability is not

necessary, than only a single resistor is necessary. The

programming resistors should be located close to the series

termination resistor to minimize the current loop area. It is

more important to locate the series termination resistor

close to the driver than the programming resistor.

The I/O pins designated by (input/output) serve as dual

signal functions to the device. During initial power-up, they

act as input pins. The logic level (voltage) that is present on

these pins at this time is read and stored into a 5-bit internal

data latch. At the end of Power-On reset, (see AC

characteristics for timing values), the device changes the

mode of operations for these pins to an output function. In

this mode the pins produce the specified buffered clocks to

external loads.

To program (load) the internal configuration register for these

pins, a resistor is connected to either the VDD (logic 1) power

supplyortheGND(logic0)voltagepotential. A10Kilohm(10K)

resistor is used to provide both the solid CMOS programming

voltageneededduringthepower-upprogrammingperiodandto

provide an insignificant load on the output clock during the

subsequent operating period.

Via to

VDD

Programming

Header

2K W

Via to Gnd

Device

Pad

8.2K W

Clock trace to load

Series Term. Res.

Fig. 1

0717F—06/10/05

18

Integrated

Circuit

ICS952606

Systems, Inc.

c

In Millimeters

In Inches

N

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

MIN

2.41

0.20

0.13

MAX

2.80

0.40

0.34

0.25

MIN

.095

.008

.005

MAX

.110

.016

.0135

.010

L

A

A1

b

E1

E

INDEX

AREA

c

D

E

E1

e

SEE VARIATIONS

10.03

7.40

10.68

7.60

.395

.291

.420

.299

1

2

α

h x 45°

0.635 BASIC

0.025 BASIC

D

h

L

0.38

0.50

0.64

1.02

.015

.020

.025

.040

N

α

SEE VARIATIONS

A

0°

8°

0°

8°

A1

VARIATIONS

- C -

D mm.

D (inch)

N

e

SEATING

PLANE

MIN

15.75

MAX

16.00

MIN

.620

MAX

b

48

.630

.10 (.004)

C

Reference Doc.: JEDEC Publication 95, MO-118

10-0034

Ordering Information

ICS952606yFLFT

Example:

ICS XXXX y F LF T

Designation for tape and reel packaging

RoHS Compliant (Optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 to 7 digit numbers)

Prefix

ICS, AV = Standard Device

0717F—06/10/05

19

Integrated

Circuit

ICS952606

Systems, Inc.

Revision History

Rev.

Issue Date Description

Page #

1. Updated pinout and pin description.

6/9/2005 2. Updated LF Ordering Information to RoHS Compliant.

6/10/2005 Updated Block Diagram

E

F

1-3, 19

4

0717F—06/10/05

20


型号：	952606FT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Clock Generator, PDSO48 光电二极管
文件：	总20页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

952606FT [IDT]

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