8V97053LNLGI8_技术文档

Low Power Wideband Fractional 

8V97053L

Datasheet

RF Synthesizer / PLL

General Description

Features

The 8V97053L is a high performance Wideband RF Synthesizer /

PLL optimized for use as the local oscillator (LO) in Multi-Carrier,

Multi-mode FDD & TDD Base Station radio card. It is offered in a

compact 5x5, 32-VFQFN package.

• Dual Differential Outputs

• Output frequency range: 34.375MHz to 4400MHz (continuous

range)

• RF Output Divide by 1, 2, 4, 8, 16, 32, 64

The 8V97053L Wideband RF Synthesizer / PLL offers a default

Fractional Mode with the option to use it with an Integer mode. It

requires an external loop filter.

• Open Drain Outputs (see Output Distribution Section)

• Fractional-N synthesizer (also supports Integer-N mode)

• 16-bit integer and 12-bit fractional 

(16-bit fractional when using the extended registers)

The 8V97053L with integrated Voltage Controlled Oscillator (VCO)

supports output frequencies from 34.375MHz to 4400MHz and

maintains superior phase noise and spurious performance.

• 3- or 4-wire SPI interface (compatible with 3.3V and 1.8V)

• Single 3.3V supply

RF_OUT_[A:B]output drivers have independently programmable

output power ranging from –4dBm to +7dBm. The RF_OUT outputs

can be muted. The mute function is accessible via a SPI command

or mute pin.

• Logic compatibility: 1.8V

• Integrated high performance low dropout regulators (LDOs) for

excellent power supply noise rejection

The operation of the 8V97053L is controlled by writing to registers

through a 3-wire SPI interface. The 8V97053L also has an additional

option that allows users to read back values from registers by

configuring the MUX_OUT pin as a SDO for the SPI interface. The

SPI interface is compatible with 1.8V logic and tolerant to 3.3V.

• Programmable output power level: -4dBm to +5dBm

(up to +7 when using the extended registers)

• Mute Function

• Ultra low PN for 1.65GHz LO: -142.21dBc/Hz @ 1MHz Offset,

(typical)

In multi-service base stations, very low noise oscillators are required

to generate a large variety of frequencies to the mixers while

maintaining excellent phase noise performance and low power. The

8V97053L offers a large tuning range capable of providing multi-band

local oscillator (LO) frequency synthesis in multi-mode base stations,

thus limiting the use of multiple narrow band RF Synthesizers and

reducing the BOM complexity and cost. The device can operate over

-40°C to +85°C industrial temperature range.

• Lock Detect Indicators

• Input Reference frequency: 5MHz to 310MHz

• 32-Lead, 5x5 VFQFN package

• Automatic VCO band selection (Autocal feature)

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

• Supports case temperature  105°C operations

Applications

• Wireless Infrastructure

• Test Equipment

• CATV Equipment

• Military and Aerospace

• Wireless LAN

• Clock Generation

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August 18, 2016

8V97053L Datasheet

Table of Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

8V97053L Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin Description and Characteristic Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 1. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2. Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 3. Supply Pins and Associated Current Return Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Synthesizer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reference Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Reference Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4A. Lock Detect Precision (LDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Feedback Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 1. RF Feedback N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 4B. Fractional Spurs Due to the Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Phase and Frequency Detector (PFD) and Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 2. Simplified PFD Circuit using D-type Flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PFD Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

External Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Phase Detector Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Charge Pump High-Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Integrated Low Noise VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Output Distribution Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 3. Output Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Output Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 5. Broadband Matching Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 6. Optimal Matching Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Band Selection Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Phase Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Phase Resync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 7. 12-bit Counter for Fast Lock and Phase Resync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fast Lock Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 8. Example of Fast Lock Mode Loop Filter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

RF Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

MUX_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 4C. MUX_OUT Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Default Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Program Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 4D. Control Bits Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

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August 18, 2016

8V97053L Datasheet

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. SPI Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. SPI Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4E. SPI Read / Write Cycle Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3- or 4-Wire SPI Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4F. SPI Mode Serial Word Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5A. Register 0 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5B. Register 0: 16-Bit Feedback Divider Integer Value (INT). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5C. Register 0: 12-Bit Feedback Divider Fractional Value (FRAC). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5D. Register 0: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6A. Register 1 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6B. Register 1: 1-Bit BAND_SEL_DISABLE. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6C. Register 1: 12-Bit Phase Value (PHASE). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6D. Register 1: 12-Bit Modulus Value (MOD). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6E. Register 1: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7A. Register 2 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7B. Register 2: 2-Bit NOISE MODE. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7C. Register 2: 3-Bit MUX_OUT. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7D. Register 2: 1-Bit REF DOUBLER. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7E. Register 2: 1-Bit REF DIV2. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7F. Register 2: 10-Bit R COUNTER (R). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7G. Register 2: 1-Bit DOUBLE BUFFER. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7H. Register 2: 4-Bit Charge Pump Setting (ICP SETTING). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7I. Register 2: 1-Bit Lock Detect Function (LDF). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7J. Register 2: 1-Bit Lock Detect Precision. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7K. Register 2: 1-Bit Phase Detector Polarity. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7L. Register 2: 1-Bit Power Down. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7M. Register 2: 1-Bit Charge Pump High-Impedance. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7N. Register 2: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8A. Register 3 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8B. Register 3: 1-Bit Band Select Clock Mode. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8C. Register 3: 2-Bit Clock Divider Mode. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8D. Register 3: 12-Bit Clock Divider Value (CLKDIV). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8E. Register 3: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9A. Register 4 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9B. Register 4: 1-Bit Feedback Select. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9C. Register 4: 3-Bit RF Output Divider (÷ MO) Select. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9D. Register 4: 8-Bit Band Select Clock Counter. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9E. Register 4: 1-Bit VCO Power Down. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9F. Register 4: 1-Bit Mute Till Lock Detect. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9G. Register 4: 1-Bit RF_OUTB Select. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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8V97053L Datasheet

Table 9H. Register 4: 1-Bit RF_OUTB Enable. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9I. Register 4: 2-Bit RF_OUTB Output Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9I. Register 4: 1-Bit RF_OUTA Enable. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9J. Register 4: 2-Bit RF_OUTA Output Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 9K. Register 4: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 10A. Register 5 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 10B. Register 5: 2-Bit LD (Lock Detect) Pin Mode. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 10C. Register 5: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Extended Registers, (Registers 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 11A. Register 6 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 11B. Register 6: 1-Bit Digital Lock Detect. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 11C. Register 6: 1-Bit Band Select Status (Read Only). Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 11D. Register 6: 2-Bit Extra Lock Detect Precision. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 11E. Register 6: 1-Bit Extra Bit of RF_OUTB Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 11F. Register 6: 1-Bit Extra Bit of RF_OUTA Power. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11G. Register 6: 2-Bit Sigma Delta Modulator Order Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11H. Register 6: 2-Bit Dither Gain Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11I. Register 6: 1-Bit Dither Noise Shaping Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11J. Register 6: 1-Bit Sigma Delta Modulator Type Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 11K. Register 6: 2-Bit VCO Band Selection Accuracy Configuration. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 11N. Register 6: 4-Bit Extra Most Significant Bits of Band Select Divider. Function Description . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 11O. Register 6: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12A. Register 7 Bit Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12B. Register 7: 1-Bit Loss of Digital Lock. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12C. Register 7: 1-Bit Loss of Analog Lock. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12D. Register 7: 1-Bit SPI Error. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 12E. Register 7: 3-Bit Revision ID. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 12F. Register 7: 4-Bit Device ID. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 12G. Register 7: 1-Bit Resolution Select. Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 12J. Register 7: 4-Bit Extra Bits of MOD Value. Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 12K. Register 7: 4-Bit Extra Bits of FRAC Value. Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 12L. Register 7: 1-Bit SCLKE. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 12M. Register 7: 1-Bit READBACK_ADDR. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 12N. Register 7: 1-Bit SPI_R_WN. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 12O. Register 7: 3-Bit Control Bits. Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 14A. Power Supply DC Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T_A= -40°C to +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 14B. Output Divider Incremental Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 14C. Typical Current by Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 14D. LVCMOS DC Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T_A= -40°C to 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

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8V97053L Datasheet

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 15A. AC Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T_A= -40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 15B. RF_OUT[A:B] Phase Noise and Jitter Characteristics, V_DDX= V_DDA= 3.3V ± 5%, TA = -40°C to 85°C . . . . . . . . . . . . . . . . .48

Phase Noise (Closed-Loop) at 156.25MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Phase Noise (Closed-Loop) at 1.76GHz (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Phase Noise (Closed-Loop) at 2.05GHz (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Phase Noise (Open-Loop) at 745MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Phase Noise Performance (Open-Loop) at 1.1GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Phase Noise Performance (Open-Loop) at 1.65GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Phase Noise Performance (Open-Loop) at 2.3GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Phase Noise Performance (Open-Loop) at 3.8GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Phase Noise Performance (Open-Loop) at 4.4GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Loop Filter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2nd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 11. Typical 2^ndOrder Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

3rd Order Loop Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 12. Typical 3rd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Schematic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 13A. An 8V97053L General Application Schematic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 13B. Schematic Example for Driving Single Ended Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 16. Thermal Resistance _JAfor 32 Lead VFQFN, Forced Convection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Example 2: VCO Frequency Range = 2590MHz to 3624MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 17A. _JAvs. Air Flow Table for a 32 lead VFQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 17B. _JBvs. Air Flow Table for a 32 lead VFQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

32-Lead VFQFN Package Outline and Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

32-Lead VFQFN Package Outline and Package Dimensions (Continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 18. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 19. Pin 1 Orientation in Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

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8V97053L Datasheet

8V97053L Block Diagram

SDO

MUX_OUT

Lock

Detect

LD

CP_OUT

Charge

Pump

PFD

÷R

÷2

x2

REF_IN

External

Loop

Filter

V_TUNE

16/1^`2 or 16/

16 bit Frac-N

Divider

FLSW

SCLK

SPI

SDI

nCS

RF_OUTA

÷M0

nRF_OUTA

Logic & Registers

CE

RF_OUTB

nRF_OUTB

MUTE

NOTE: 16-Bit Integer / 16-Bit Fractional feedback divider is available when using extended register.

Pin Assignment

31 30 29 28 27 26 25

32

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SCLK

SDI

V_REF

V_COM

nCS

R_CP

CE

GNDA_VCO

V_TUNE

8V97053L

FLSW

V_{_CP}

V_BIAS

CP_OUT

GND_CP

GNDA_VCO

V_VCO

9

10 11 12 13 14 15 16

32-Lead 5mm x 5mm VFQFN

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August 18, 2016

8V97053L Datasheet

Pin Description and Characteristic Tables

1

Table 1. Pin Description

1

Name

SCLK

SDI

Type

LVCMOS Input

Description

Pulldown Serial Clock Input. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant.

2

LVCMOS Input

Pullup

Serial Data Input. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant.

Load Enable. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant. Active

Low.

3

4

5

6

nCS

CE

Pulldown

Chip Enable. On logic Low, powers down the device and puts the charge

pump into High-Impedance mode. Powers up the device on logic High.

LVCMOS Input

Analog

Pullup

Fast Lock Switch. A connection should be made from the loop filter to this pin

when using the fast lock mode.

FLSW

V_{_CP}

Charge Pump Power Supply. V_{_CP}must have the same value as V_DDA.Place

decoupling capacitors to the ground plane as close to this pin as possible.

Power

Charge Pump Output. When enabled, this output provides ±ICP to the

external loop filter. The output of the loop filter is connected to V_TUNEto drive

the internal VCO.

7

CP_OUT

Analog

8

9

GND_CP

GNDA

Ground

Charge Pump Power Supply Ground.

Analog Power Supply Ground.

Analog Supply. This pin ranges from 3.3V ± 5%. V_DDAmust have the same

value as V_DDD.

10

V_DDA

Power

11

12

13

14

15

GNDA_VCO

RF_OUT_A

nRF_OUT_A

RF_OUT_B

nRF_OUT_B

Ground

Output

VCO Analog Power Supply Ground.

Clock Output pair A. The output level is programmable.

Clock Output pair B. The output level is programmable.

VCO Supply. This pin ranges from 3.3V ± 5%. V_VCOmust have the same

value as V_DDA.

16

17

V_VCO

Power

VCO Supply. This pin ranges from 3.3V ± 5%. V_VCOmust have the same

value as V_DDA.

V_VCO

18

19

20

21

22

GNDA_VCO

V_BIAS

Ground

Analog

VCO Analog Power Supply Ground.

Place decoupling capacitors (10µF) to ground, as close to this pin as possible.

Control Input to tune the VCO.

V_TUNE

GNDA_VCO

R_CP

Ground

Analog

VCO Analog Power Supply Ground.

Sets the charge pump current. Requires external resistor.

Place decoupling capacitors (1µF – 10µF) to ground, as close to this pin as

possible.

23

24

25

V_COM

V_REF

LD

Analog

Place decoupling capacitors (10µF) to ground, as close to this pin as possible.

Lock Detect. Logic High indicates PLL lock. Logic Low indicates loss of PLL

lock.

LVCMOS Output

RF_OUT_Aand RF_OUT_BPower-Down. A logic low on this pin mutes the

RF_OUT outputs and puts them in High-Impedance.

26

27

MUTE

GNDD

LVCMOS Input

Ground

Pullup

Digital Power Supply Ground.

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8V97053L Datasheet

1

Table 1. Pin Description (Continued)

28

V_DDD

Power

Digital Supply. V_DDDmust have the same value as V_DDA.

Reference Input. This CMOS input has a nominal threshold of V_DDA/2 and a

DC equivalent input resistance of 100k. This input can be driven from a TTL

or CMOS crystal oscillator, or it can be AC-coupled.

29

REF_IN

LVCMOS Input

Analog

30

31

MUX_OUT

GND_SD

LVCMOS Output

Ground

Multiplexed Output and Serial Data Out. Refer to Table 4C, Page 18.

Digital Sigma Delta Modulator Power Supply Ground.

Digital Sigma Delta Modulator Supply. V_{DD_SD}must have the same value as

V_DDA.

32

V_{DD_SD}

Power

EP

Exposed Pad

Ground

Must be connected to GND.

NOTE 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_in

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

LVCMOS Output Impedance

Input Pullup Resistor

4

R_OUT

MUX_OUT & LD

38

51



R_PULLUP

k

R_PULLDOWNInput Pulldown Resistor

Table 3. Supply Pins and Associated Current Return Paths

Power Supply Pin Number

Power Supply Pin Name

Associated Ground Pin Number

Associated Ground Pin Name

10

28

V_DDA

V_DDD

9

GNDA

GNDD

27

32

V_{DD_SD}

V_VCO

31

11, 18, 21

8

GND_SD

GNDA_VCO

GND_CP

16, 17

6

V_{_CP}

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August 18, 2016

8V97053L Datasheet

Principles of Operation

Synthesizer Programming

The Fractional-N architecture is implemented via a cascaded programmable dual modulus prescaler. The N divider offers a division ratio in the

feedback path of the PLL, and is given by programming the value of INT, FRAC and MOD in the following equation:

N = INT + FRAC/MOD

(1)

INT is the divide ratio of the binary 16-bits counter (refer to Table 5B, Page 22).

FRAC is the numerator value of the fractional divide ratio. It is programmable from 0 to (MOD – 1). Refer to Table 5C when in 12-bit mode, or

Table 12K when in 16-bit mode.

MOD is the 12-bit or 16-bit modulus. It is programmable from 2 to 4095 in 12-bit mode, and 2 to 65535 in 16-bit mode. Refer to Table 6D when

in 12-bit mode, or Table 12J when in 16-bit mode.

The VCO frequency (f_VCO) at RF_OUT_Aor RF_OUT_Bis given by the following equation:

f

_VCO= f_PFDx (INT + FRAC/MOD)

(2)

f_PFDis the frequency at the input of the Phase and Frequency Detector (PFD).

The 8V97053L offers an Integer mode. To enable that mode, the user has to program the FRAC value to 0.

The device’s VCO features three VCO band-splits to cover the entire range with sufficient margin for process, voltage, and temperature

variations. These are automatically selected by invoking the Autocal feature. The charge pump current is also programmable via the ICP

SETTING register for maximum flexibility.

Via Register 4, one can enable RF_OUT_Aor both outputs. Similarly, one can disable RF_OUT_Bor both outputs.

Reference Input Stage

The 8V97053L features one single-ended reference clock input (REF_IN). This single-ended input can be driven by an ac-coupled sine wave

or square wave.

In Power Down mode this input is set to High-Impedance to prevent loading of the reference source.The reference input signal path also

includes an optional doubler.

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8V97053L Datasheet

Reference Doubler

To improve the phase noise performance of the device, the reference doubler can be used. By using the doubler, the PFD frequency is also

doubled and the phase noise performance typically improves by 3dB. When operating the device in Fractional mode, the speed of the Sigma

Delta modulator of the N counter is limited to 125MHz, which is also the maximum PFD frequency that can be used in the fractional mode.

When the part operates in Integer-N mode, the PFD frequency is limited to 310MHz.

The user has the possibility to select a higher PFD frequency (up to 310MHz in Integer mode) by doing the following steps using the extended

registers (Register 6 and 7):

1. The user needs to increase the size of the Band Select Clock Divider (normally 8-bits) by setting the bit [D6:D3] in the Register 6 to divide

down to a frequency lower than 500kHz and higher than 125kHz.

2. Use the Bit[D27:D26] to increase the lock detect precision for the faster PFD frequency.

The Lock Detect window should be set as large as possible but less than a period of the phase detector. The phase detector frequency should

be greater than 500kHz.

Table 4A. Lock Detect Precision (LDP)

LDP_Ext2

LDP_Ext1

LDP

(D27 of Register 6)

(D26 of Register 6)

(D7 of Register 2)

LDP value (ns)

0

1

10

6

Use of Extended Register 6

0

1

0

1

0

1

0

1

0

1

3

4

4.5

1.5

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August 18, 2016

8V97053L Datasheet

Feedback Divider

The feedback divider N supports fractional division capability in the PLL feedback path. It consists in an integer N divider of 16-bits, and a

Fractional divider of 12-bits (FRAC) over 12-bits (MOD). FRAC and MOD can be extended to 16-bits when using extended registers.

To select an integer mode only, the user sets FRAC to 0.

FROM VCO OUTPOUT

or FROM M0 OUTPUT

TO PFD

N counter

3^rdOrder

ΣΔ Modulator

12 Bit FRAC

16 Bit INT

+

12 Bit MOD

Figure 1. RF Feedback N Divider

The 16 INT bits (Bit[D30:D15] in Register 0) set the integer part of the feedback division ratio.

The 12 FRAC bits (Bit[D14:D3] in Register 0) set the numerator of the fraction that goes into the Sigma Delta modulator. FRAC can be extended

to 16-bits using the EXT_FRAC bits in Register 7.

The 12 MOD bits (Bit[D14:D3] in Register 1) set the denominator of the fraction that goes into the Sigma Delta modulator. MOD can be

extended to 16-bits using the EXT_MOD bits in Register 7.

From the relation (2), the VCO minimum step frequency is determined by (1/MOD) * f_PFD.

FRAC values from 0 to (MOD – 1) cover channels over a frequency range equal to the PFD reference frequency.

The PFD frequency is calculated as follows:

(3)

Use 2R instead of R if the Reference Divide by 2 is used. 

REF_CLK= the input reference frequency (REF_IN)

D

R

= the input reference doubler (0 if not active or 1 if active)

= the 10-Bits programmable input reference pre-divider

The programmable modulus (MOD) is determined based on the input reference frequency (REF_IN) and the desired channelization (or output

frequency resolution). The high resolution provided on the R counter and the Modulus allows the user to choose from several configuration (by

using the doubler or not) of the PLL to achieve the same channelization. Using the doubler may offer better phase noise performance. The

high resolution Modulus also allows to use the same input reference frequency to achieve different channelization requirements. Using a

unique PFD frequency for several needed channelization requirements allows the user to design a loop filter for the different needed setups

and ensure the stability of the loop.

The channelization is given by

(4)

In low noise mode (dither disabled), the Sigma Delta modulator can generate some fractional spurs that are due to the quantization noise.

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8V97053L Datasheet

The spurs are located at regular intervals equal to f_PFD/L where L is the repeat length of the code sequence in the Sigma Delta modulator. That

repeat length depends on the MOD value, as described in Table 4B.

Table 4B. Fractional Spurs Due to the Quantization Noise

Condition (Dither Disabled)

L

Spur intervals

MOD can be divided by 2, 

but not by 3

2 x MOD

f

_PFD/(2*MOD)

_PFD/(3*MOD)

MOD can be divided by 3, 

but not by 2

3 x MOD

6 x MOD

MOD

MOD can be divided by 6

Other conditions

f

_PFD/(6*MOD)

_PFD/MOD

(channel step)

In order to reduce the spurs, the user can enable the dither function to increase the repeat length of the code sequence in the Sigma Delta

modulator. The increased repeat length is 2²¹cycles so that the resulting quantization error is spread to appear like broadband noise. As a

result, the in-band phase noise may be degraded when using the dither function.

When the application requires the lowest possible phase noise and when the loop bandwidth is low enough to filter most of the undesirable

spurs, or if the spurs won’t affect the system performance, it is recommended to use the low noise mode with dither disabled.

Phase and Frequency Detector (PFD) and Charge Pump

The phase detector compares the outputs from the R counter and from the N counter and generates an output corresponding to the phase and

frequency difference between the two inputs the PFD. The charge pump current is programmable through the serial port (SPI) to several

different levels.

The PFD offers an anti-backlash function that helps to avoid any dead zone in the PFD transfer function.

I

CP

VDD

D1

Q1

REF_IN x (1+D)/R

CP_OUT

DELAY

VDD

FB

D1

Q1

I

CP

Figure 2. Simplified PFD Circuit using D-type Flip-flop

The Band Select logic operates between 125kHz and 500kHz. The Band Select clock divider needs to be set to divide down the PFD frequency

to between 125kHz to 500kHz (logic maximum frequency).

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8V97053L Datasheet

PFD Frequency

The VCO Band Selection can be used while operating at PFD frequencies up to 310MHz.

If the application requires the PFD frequency to be higher than 125MHz, the user can use one of the following two techniques (Technique A is

the recommended procedure):

A.The user can use the extended register ExtBndSelDiv[4:1] bits (Bits[D6:D3]) in Register 6. These additional band select divider bits

extend the band select divider from 8-bits (available in Register 4) to 12-bits. The four additional band select divider bits in Register 4 are

the most significant bits of the divide value. For proper VCO band selection, the PFD frequency divided by the band select divide value

must be 500kHz and 125kHz.

B.If choosing this second technique, the user must follow the three following steps:

1. Disable the Phase Adjust function by setting the bit D28 In Register 1 to 0, keep the PFD frequency lower than 125MHz, and program

the desired VCO frequency.

2. Enable the phase adjust function by setting BAND_SEL_DISABLE (Bit D28 in Register 1) to 1.

3. Set the desired PFD frequency and program the relevant 

R divider and N counter values.

In either technique, the Lock Detect Precision should be programmed to be lower than the PFD period using the bit [D7] in Register 2 and the

bits [D27:D26] in Register 6 (Refer to Table 4A, Page 10).

External Loop Filter

The 8V97053L requires an external loop filter. The design of that filter is application specific. For additional information, refer to the Applications

Information section.

Phase Detector Polarity

The phase detector polarity is set by bit D6 in Register 2. This bit should be set to 1 when using a passive loop filter or a non-inverting active

loop filter. If an inverting active filter is used, this bit should be set to 0.

Charge Pump High-Impedance

In order to put the charge pump into three-state mode, the user must set the bit D4 [CP HIGHZ] in Register 2 to 1. This bit should be set to 0

for normal operation.

Integrated Low Noise VCO

The VCO function of the 8V97053L consists in three separate VCOs. This allows keeping narrow tuning ranges for the VCOs while offering a

large frequency tuning range for VCO core. Keeping narrow VCO tuning ranges allows for lower VCO sensitivity (K_VCO), which results in the

best possible VCO phase noise and spurious performance.

The user does not have to select the different VCO bands. The VCO band select logic of the 8V97053L will automatically select the most

suitable band of operation at power up or when Register 0 is written.

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8V97053L Datasheet

Output Distribution Section

The 8V97053L device provides two outputs. These two outputs can generate the same frequency (f_VCO/ M0) or two integer related different

frequencies (in this case, RF_OUT_Bwould generate a frequency equal to the VCO frequency and RF_OUT_Awould generate f_VCO/ M0).

Figure 3. Output Clock Distribution

RF_OUT and nRF_OUT are derived from the drain of an NMOS differential pair driven by the VCO output (or by the M0 Divider), as shown in

Figure 4, Output Stage.

RF_OUT

nRF_OUT

÷ M0

Figure 4. Output Stage

Eight programmable output power levels can be programmed from -4dBm to +7dBm (see RF Output Power section).

The 8V97053L offers an auxiliary output (RF_OUT_B). If the auxiliary output stage is not used, it can be powered down by using the

RF_OutB_En bit in Register 4.

The supply current to the output stage can be shut down until the part achieves lock. To enable this mode, the user will set the MTLD bit in

Register 4. The MUTE pin can be used to mute all outputs and be used as a similar function.

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8V97053L Datasheet

Output Matching

The outputs of the 8V97053L are Open Drain Output and can be matched in different ways.

A simple broadband matching is to terminate the open drain RF_OUT output with, for example, a 50 to V_DDA, and with an AC coupling

capacitor in series. An example of this termination scheme is shown on Figure 5, Broadband Matching Termination.

Figure 5. Broadband Matching Termination

This termination scheme allows to provide one of the selected output power on the differential pair when connected to a 50 load. (See the

RF Output Power section for more information about the output power selection).

The 50 resistor connected to V_DDAcan also be replaced by a choke, for better performance and optimal power transmission.

The pull up inductor value is frequency dependent. For impedance 

of 50 pull-up, the inductance value can be calculated as 

L = 50/(2*3.14*F), where F is operating frequency. In this example, 

L = 3.9nF is for an operating frequency of approximately 2GHz.

Figure 6. Optimal Matching Termination

See Applications Information section for more recommendations on the termination scheme.

Band Selection Disable

For a given frequency, the output phase can be adjusted when using the Band_Sel_Disable bit (Bit D28 in Register 1). When this bit is enabled

(Bit D28 set to 1), the part does not do a VCO band selection or phase resync after an update to Register 0.

When the Band_Sel_Disable bit is set to 0, and when Register 0 is updated, the part proceeds to a VCO band selection, and to a phase resync

if phase_resync is also enabled in Register 3 (Bits[D16:D15] set to D16 = 1 and D15 = 0).

The “Band_Sel_Disable” bit is useful when the user wants to make small changes in the output frequency (<1MHz from the nominal frequency)

without recalibrating the VCO and minimizing the settling time.

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8V97053L Datasheet

Phase Adjust

The output phase is controlled by the 12-Bit phase value Bits[D26:D15] in Register 1. The output phase can vary over 360° with a 360°/MOD

step. For dynamic adjustments of the phase after an initial phase setting, it is recommended to select the BAND_SEL_DISABLE function by

setting the Band_Sel_Disable bit (D28 in Register 1) to 1.

The PHASE value can be extended to 16-bits when using the extended registers. In this 16 bit mode, both registers 1 and 7 define the PHASE

value.

Phase Resync

The phase alignment function operates based on adjusting the “fractional” phase, so the phase can settle to any one of the MOD phase offsets,

MOD being the modulus of the fractional feedback divider.

The phase adjustment can provide a 0-360° of phase adjust, assuming that the output divider ratio is set to 1.

The phase step is TVCO/MOD for the normal case of fundamental feedback. TVCO is the period of the VCO.

The feedback select bit (FbkSel bit, Bit D23 in Register 4) gives the choices of fundamental feedback or divided feedback. This bit controls the

mux that sends the VCO signal or the output divider signal to the feedback loop. The user can get larger phase steps in the divided mode, but

the phase noise may be degraded, especially in fractional mode. Should the user select this option, the phase adjustment step would be

~T_OUT/MOD, where T_OUTis the output signal period.

When the part is in fractional mode, the device is dithering the feedback divider value. As an example, when using a 4GHz VCO frequency,

the feedback divider value may dither between Div-by-20 and Div-by-21. Since the period is 250ps, there will be 250ps of jitter added to the

phase detector. This jitter is filtered by the loop, but can still show up at the output if the loop bandwidth is high. When using a divider before

the feedback divider, the effective VCO period is increased. If a Div-by-64 is used for example, the period becomes 64x250ps = 16ns. This

means that there could be an additional 16ns of jitter at the PFD, rather than 250ps. It is more challenging for the loop to filter this larger amount

of jitter and this will degrade the overall performance of the part, unless the user chooses to use a very low loop bandwidth. With normal loop

bandwidth configurations (for optimal noise), the phase noise would be degraded when using a divided feedback mode.

The Phase Resync is controlled by setting Bits[D16:D15] in Register 3 to D16 = 1 and D15 = 0. When phase resync is used, an internal timer

generates sync signals every T_SYNCwhere:

T_SYNC= ClkDiv x MOD x T_PFD

(5)

ClkDiv = the value (from 1 and 4095) programmed in the 12-bit clock counter in Bits[D14:D3] in Register 3. The 12-bit counter is used as a

timer for Fast Lock and for the Phase Resync function.

MOD = the Modulus value (Bits[D14:D3] of Register 1)

T_PFD= the PFD period

In Equation 5, the minimum of either MOD value or 4095 is used for calculating T_SYNCwhen in 16-bit mode.

Figure 7. 12-bit Counter for Fast Lock and Phase Resync

After the user program a frequency, the second sync pulse coming from the 12-bit counter, after the nCS is asserted high, is used to

resynchronize the output phase to the input phase. To ensure that the PLL is locked before to resynchronize the output phase, TSYNC must

be larger than the worst case lock time.

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8V97053L Datasheet

Fast Lock Function

The device uses a fast-lock mode to decrease lock time.

In order to allow the Fast Lock mode, the Fast Lock Switch (FLSW) is shorted to Ground and the charge pump current (ICP) is changed

temporarily until the Fast Lock mode is disabled.

The loop bandwidth needs to be increased temporarily in order to allow a faster lock time. By doing this, the loop filter needs to be initially

designed so that it addresses the risk of instability of having the zero and the poles too close to the actual bandwidth knee, when the user

switches to a fast lock mode.

The loop bandwidth is proportional to:

RS and ICP (BW ~ RS * ICP)

Where:

BW = the loop bandwidth

RS = the damping resistor

ICP = the programmable charge pump current

In order to enable the fast lock mode, the charge pump current is increased to the maximum value in order to increase the loop bandwidth. In

parallel, the FLSW filter is set to ON so that the RS value is ¼ of its initial value in order to maintain the loop stability. By doing so, the zero and

the first pole are moved (by a factor of 4x in the example below), so that the zero and the pole are kept at a suitable distance around the loop

bandwidth.

Figure 8. Example of Fast Lock Mode Loop Filter Topology

In the example of Figure 8, Example of Fast Lock Mode Loop Filter Topology, the damping resistor RS is equal to:

RS1 + RS2 in normal mode (FSLW switch OFF), with RS2 = 3 * RS1

When the FLSW switch is ON, the damping resistor value is reduced by ¼ of its initial value (RS = RS1).

The second pole defined by R3 and C3 need needs to be designed so that there is no risk of instability when widening the loop bandwidth.

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8V97053L Datasheet

RF Output Power

For RF_OUT_Aand RF_OUT_B,the output power can be programmed from -4dBm to +7dBm.

Refer to Table 9I, Page 33, Table 9J, Table 11E, Page 37 and Table 11F in the Register Map section for more information.

MUX_OUT

MUX_OUT is a multipurpose output that can be programmed to provide the user with some internal status and values for test and debugging

purpose. In addition, MUX_OUT can also be programmed to provide an additional Serial Data Out Pin for a 4-wire SPI interface when needed.

The MUX_OUT function is described in the Table 4C and can be programmed in Bits[D28:D26] in Register 2.

Table 4C. MUX_OUT Pin Configuration

MUX_OUT Register Value

MUX_OUT Function

High-Impedance Output

V_DDD

000

001

010

011

100

101

110

111

GNDD

R Counter Output

N counter Output

Reserved

Lock Detect

MUX_OUT configured as SDO

Power-Down Mode

When power-down is activated, the following events occur:

1. Counters are forced to their load state conditions

2. VCO is powered down

3. Charge pump is forced into three-state mode

4. Digital lock detect circuitry is reset

5. RF_OUT buffers are disabled

6. The input stage is powered down and set to High-Impedance

7. Input registers remain active and capable of loading and latching data

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8V97053L Datasheet

Default Power-Up Conditions

All the RF outputs are muted at power up until the loop is locked. Refer to the Register Map section for default values in registers.

Program Modes

Table 4D and the Register Map indicate how the program modes are set up in the 8V97053L.

Table 4D. Control Bits Configuration

Control Bits (CB)

C3

0

C2

0

C1

0

Register

Register 0

0

1

Register 1

0

1

0

Register 2

0

1

Register 3

1

0

Register 4

1

0

1

Register 5

1

0

Extended Register 6

Extended Register 7

1

Double Buffering

The following bits are Doubled Buffered:

1. PHASE (Bits[D26:D15] in Register 1)

2. MOD (Bits[D14:D3] in Register 1)

3. REF DOUBLER (Bit D25 in Register 2)

4. REF DIV2 (Bit D24 in Register 2)

5. R COUNTER (Bits[D23:D14] in Register 2)

6. ICP SETTING (Bits[D12:D9] in Register 2)

The user must proceed to the following steps before any value written in these bits are used.

1. The new values are written in the double buffered bits

2. A new Write is performed on Register 0

The RF DIVIDER value in Register 4 (Bits[D22:D20]) is also double buffered, but only if the DOUBLE BUFFER bit (Bit D13 in Register 2) is

set to 1.

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8V97053L Datasheet

Timing Characteristics

t_SUt_H

t_LOt_HI

t_PW

nCS

SCLK

SDI

D31

D30

D29

D28

D1

D0

Start Write Command

Complete Write Command

Figure 9. SPI Write Cycle Timing Diagram

t_PW

nCS

SCLK

D1

D0

SDI

SDO (SCLKE = 1)

SDO (SCLKE = 0)

D31

D30

D29

D28

D1

D0

D31

D30

D29

D28

D1

D0

Start Read Transmission

Complete read command (Write to Register 7)

Complete Read Transmission

Figure 10. SPI Read Cycle Timing Diagram

Table 4E. SPI Read / Write Cycle Timing Parameters

Symbol

f_CLK

t_SU

Parameter

Minimum

Maximum

Unit

MHz

ns

SCLK Frequency

-

20

-

nCS, SDI Setup Time to SCLK

SCLK to nCS, SDI Hold Time

SCLK Low Pulse Width

SCLK High Pulse Width

nCS De-asserted Pulse Width

10

25

20

t_H

-

ns

t_LO

-

ns

t_HI

-

ns

t_PW

-

ns

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August 18, 2016

8V97053L Datasheet

3- or 4-Wire SPI Interface Description

The 8V97053L has a serial control port capable of responding as a slave in an SPI compatible configuration to allow access to any of the

internal registers (see section, “Register Map” on page 22) for device programming or examination of internal status. See the specific sections

for each register for details on meanings and default conditions.

SPI mode slave operation requires that a device external to the 8V97053L has performed any necessary serial bus arbitration and/or address

decoding at the level of the board or system. The 8V97053L begins a cycle by detecting an asserted (low) state on the nCS input at a rising

edge of SCLK. This is also coincident with the first bit of data being shifted into the device. In SPI mode, the first bit is the Most Significant Bit

(MSB) of the data word being written. Data must be written in 32-bit words, with nCS remaining asserted and one data bit being shifted in to

the 8V97053L on every rising edge of SCLK. If nCS is de-asserted (high) at any time except after the complete 32^ndSCLK cycle, this is treated

as an error and the shift register contents are discarded. No data is written to any internal registers. If nCS is de-asserted (high) as expected

at a time at least t_SUafter the 32^ndfalling edge of SCLK, then this will result in the shift register contents being acted on according to the control

bit in it.

It is recommended to write the registers in reverse sequential order, starting with the highest register number first and ending with Register 0.

The word format of the 32-bit quantity in the shift register is shown in Table 4F. The register fields in the 8V97053L have been organized so

that the three LSBs in each 32-bit register row are not used for data transfer. These bits will represent the base address for the 32-bit register

row.

To perform a register Read, the user needs set the MUX_OUT bits (Bits[28:D26]) in Register 2 to 111 to configure the MUX_OUT pin as SDO.

Register 7 (Instruction register) needs to be set for Read operation. Bit D3 of Register 7 will set the Read or Write command, and Bits[D4:D6]

determine the read back address.

If a read operation is requested, 32-bits of read data will be provided in the immediately subsequent access. nCS must be de-asserted (high)

for at least t_PW,and then reasserted (low).

If SCLKE = 1 (default condition), one data bit will be transmitted on the SDO output at the falling edge of nCS and each falling edge of SCLK

as long as nCS remains asserted (low), and the master device should capture data on the rising edge of SCLK. If SCLKE = 0, one data bit will

be transmitted on the SDO output at each rising edge of SCLK as long as nCS remains asserted (low), and the master device should capture

data on the falling edge of SCLK.

If nCS is de-asserted (high) before 32-bits of read data have been shifted out, the read cycle will be considered to be completed. If nCS remains

asserted (low) longer than 32-bit times, then the data during those extra clock periods will be undefined. The MSB of the data will be presented

first.

Table 4F. SPI Mode Serial Word Structure

MSB

31

LSB

0

Bit #

…

5

4

3

2

1

Meaning

Width

D[31:3]

29

Control Bits

3

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8V97053L Datasheet

Register Map

Register 0

Table 5A. Register 0 Bit Allocation

FEEDBACK DIVIDER FRACTIONAL VALUE

(FRAC)

CONTROL

BITS

FEEDBACK DIVIDER INTEGER VALUE (INT)

Table 5B. Register 0: 16-Bit Feedback Divider Integer Value (INT). Function Description

Name

Description

Factory Default

Function

0000 0000 0000 0000 = Not allowed

0000 0000 0000 0001 = Not allowed

...

0000 0000 0000 0111 = Not allowed

0000 0000 0000 1000 = 8

…

0000 0000 0110 0100

(INT = 100)

NDiv[16:1]

Feedback Divider Integer Value (INT)

0000 0000 0001 0111 = 23

0000 0000 0001 1000 = 24

…

1111 1111 1111 1111 = 65,535

1

Table 5C. Register 0: 12-Bit Feedback Divider Fractional Value (FRAC). Function Description

Name

Description

Factory Default

Function

0000 0000 0000 = 0

0000 0000 0001 = 1

…

0000 0000 0000

(FRAC = 0)

FDiv[12:1]

Feedback Divider Fractional Value (FRAC)

1111 1111 1111 = 4095

NOTE 1. This table is used when bit 16b_12b_sel is set to 0 (default). If the 16b_12b_sel is set to 1, refer to Table 12K, Page 42.

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8V97053L Datasheet

1

Table 5D. Register 0: 3-Bit Control Bits. Function Description

Name

Description

Function

000 = Register 0 is programmed

CB[3:1]

Control Bits

NOTE 1. The user has to set CB[3:1] to 000 in order to write to Register 0.

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8V97053L Datasheet

Register 1

Table 6A. Register 1 Bit Allocation

CONTROL

BITS

RESERVED

PHASE VALUE (PHASE)

MODULUS VALUE (MOD)

Table 6B. Register 1: 1-Bit BAND_SEL_DISABLE. Function Description

Name

Description

Factory Default

Function

0 = VCO Band Selection occurs after a Write to Register 0

Band_Sel_Disable BAND_SEL_DISABLE

0

1 = VCO Band selection is not active and hold to previous VCO band

selection

Table 6C. Register 1: 12-Bit Phase Value (PHASE). Function Description

16b_12b_sel

Name

Description

(Bit D20, Register7)

Factory Default

Function

0000 0000 0000 = 0

0000 0000 0001 = 1

…...

0

0000 0000 0001

1111 1111 1111 = 4095

0000 0000 0000 = 0

0000 0000 0001 = 16

…...

Phase [12:1]

PHASE

1

0000 0000 0001

1111 1111 1111 = 65520

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1

Table 6D. Register 1: 12-Bit Modulus Value (MOD). Function Description

Name

Description

Factory Default

Function

0000 0000 0000 = Not Allowed

0000 0000 0001 = Not Allowed

0000 0000 0010 = 2

…

Mod[12:1]

MOD

0000 0000 0010

1111 1111 1111 = 4095

NOTE 1. This table is used when bit D20 in Register 7 (16b_12B_sel) is set to 0 (default). If 16b_12b_sel is set to 1, refer to Table 12J, Page

42.

1

Table 6E. Register 1: 3-Bit Control Bits. Function Description

Name

Description

Function

CB[3:1]

Control Bits

001 = Register 1 is programmed

NOTE 1. The user has to set CB[3:1] to 001 in order to write to Register 1.

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8V97053L Datasheet

Register 2

Table 7A. Register 2 Bit Allocation

CONTROL

BITS

MUX_OUT

R COUNTER

ICP SETTING

Table 7B. Register 2: 2-Bit NOISE MODE. Function Description

Name

Description

Factory Default

Function

00 = Low Noise Mode (Dither OFF)

01 = Reserved

ModeNoise[2:1]

NOISE MODE

00

10 = Reserved

11 = Low Spur Mode (Dither Enabled)

Table 7C. Register 2: 3-Bit MUX_OUT. Function Description

Name

Description

Factory Default

Function

000 = High-Impedance output

001 = V_DDD

010 = GNDD

011 = R counter output

100 = N counter output

101 = Reserved

MUX_OUT[3:1]

MUX_OUT

000

110 = Lock Detect

111 = MUX_OUT configured as SDO

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8V97053L Datasheet

Table 7D. Register 2: 1-Bit REF DOUBLER. Function Description

Name

Description

Factory Default

Function

0 = Disabled

1 = Enabled

RefDoub

REF DOUBLER

0

Table 7E. Register 2: 1-Bit REF DIV2. Function Description

Name

Description

Factory Default

Function

0 = Disabled

1 = Enabled

RDIV2

REF DIV2

0

Table 7F. Register 2: 10-Bit R COUNTER (R). Function Description

Name

Description

Factory Default

Function

00 0000 0000 = Not Allowed

00 0000 0001 = 1

00 0000 0010 = 2

…

R[10:1]

R

00 0000 0001

11 1111 1111 = 1023

1

Table 7G. Register 2: 1-Bit DOUBLE BUFFER. Function Description

Name

Description

Factory Default

Function

0 = Disabled

1 = Enabled

DoubBuff1

DOUBLE BUFFER

0

NOTE 1. Bit D13 enables or disables Double Buffering of Bits[D22:D20] in Register 4. Refer to Program Modes section.

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8V97053L Datasheet

Table 7H. Register 2: 4-Bit Charge Pump Setting (ICP SETTING). Function Description

Name

Description

Factory Default

Function

Icp (mA) assuming RCP = 5.1k

0000 = 0.31

0001 = 0.63

0010 = 0.94

0011 = 1.25

0100 = 1.56

0101 = 1.88

0110 = 2.19

ChrgPmp[4:1]

ICP SETTING

0000

0111 = 2.50

1000 = 2.81

1001 = 3.13

1010 = 3.44

1011 = 3.75

1100 = 4.06

1101 = 4.38

1110 = 4.69

1111 = 5.00

1

Table 7I. Register 2: 1-Bit Lock Detect Function (LDF). Function Description

Name

Description

Factory Default

Function

0 = 40 consecutive cycles (recommended for FRAC-N mode)

1 = 5 consecutive cycles (recommended for INT-N mode)

LDF

0

NOTE 1. LDF controls the number of PFD cycles that needs to be considered by the Lock Detect function to decide if the part has achieved

lock.

Table 7J. Register 2: 1-Bit Lock Detect Precision. Function Description

Name

Description

Factory Default

Function

0 = 10ns

1 = 6ns

LDP

0

Table 7K. Register 2: 1-Bit Phase Detector Polarity. Function Description

Name

Description

Factory Default

Function

0 = NEGATIVE

1 = POSITIVE

PD_Pol

PD POLARITY

1

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8V97053L Datasheet

Table 7L. Register 2: 1-Bit Power Down. Function Description

Name

Description

Factory Default

Function

0 = Disabled

1 = Enabled

PwrDwn

POWER DOWN

0

Table 7M. Register 2: 1-Bit Charge Pump High-Impedance. Function Description

Name

Description

Factory Default

Function

0 = Disabled

1 = Enabled

CP_HIGHZ

CP HIGHZ

0

1

Table 7N. Register 2: 3-Bit Control Bits. Function Description

Name

Description

Function

010 = Register 2 is programmed

CB[3:1]

Control Bits

NOTE 1. The user has to set CB[3:1] to 010 in order to write to Register 2.

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8V97053L Datasheet

Register 3

Table 8A. Register 3 Bit Allocation

CONTROL

BITS

RESERVED

CLOCK COUNTER VALUE

1

Table 8B. Register 3: 1-Bit Band Select Clock Mode. Function Description

Name

Description

Factory Default

Function

0 = LOW (125kHz)

BandSelCM

BAND SELECT (CLOCK RATE)

0

1 = HIGH (up to 500kHz logic sequence for

Faster Lock applications)

NOTE 1. BAND SELECT (CLOCK RATE) selects the speed of the logic sequence for the band selection. BandSelCM = 1 sets the logic se-

quence rate faster, which is recommended for fast lock operation and when high PFD frequencies are used. BandSelCM = 0 is rec-

ommended when low PFD frequencies (125kHz) are used. When using BandSelCM = 1, the value of the BAND SELECT CLOCK

COUNTER (BndSelDiv[8:1]) must be less than or equal to 254.

Table 8C. Register 3: 2-Bit Clock Divider Mode. Function Description

Name

Description

Factory Default

Function

00 = Clock Divider OFF

01 = Fast Lock Enabled

10 = Resync Enabled

11 = Reserved

ClkDivMode[2:1] CLK DIV MODE

00

Table 8D. Register 3: 12-Bit Clock Divider Value (CLKDIV). Function Description

Name

Description

Factory Default

Function

0000 0000 0000 = Not allowed

0000 0000 0001 = 1

0000 0000 0010 = 2

…

ClkDiv[12:1]

CLKDIV

0000 0000 0001

1111 1111 1111 = 4095

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8V97053L Datasheet

1

Table 8E. Register 3: 3-Bit Control Bits. Function Description

Name

Description

Function

011 = Register 3 is programmed

CB[3:1]

CONTROL BITS

NOTE 1. The user has to set CB[3:1] to 011 in order to write to Register 3.

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8V97053L Datasheet

Register 4

Table 9A. Register 4 Bit Allocation

BAND SELECT CLOCK

COUNTER

CONTROL

BITS

RESERVED

Table 9B. Register 4: 1-Bit Feedback Select. Function Description

Name

Description

Factory Default

Function

0 = Divided

FbkSel

FEEDBACK SELECT

1

1 = Fundamental

Table 9C. Register 4: 3-Bit RF Output Divider (÷ MO) Select. Function Description

Name

Description

Factory Default

Function

000 = Div by 1

001 = Div by 2

010 = Div by 4

011 = Div by 8

100 = Div by 16

101 = Div by 32

110 = Div by 64

111 = Reserved

RFDiv[3:1]

RF OUTPUT DIVIDER

000

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8V97053L Datasheet

1

Table 9D. Register 4: 8-Bit Band Select Clock Counter. Function Description

Name

Description

Factory Default

Function

0000 0000 = Not Allowed

0000 0001 = 1

0000 0010 = 2

...

BndSelDiv[8:1]

BAND SELECT CLOCK COUNTER

0000 0001

1111 1111 = 255

NOTE 1. BAND SELECT CLOCK COUNTER sets the value of the divider for the band select logic clock input. By default, the output frequency

of the R counter is used to clock the band select logic. If this frequency is larger than 125kHz, the Band Select Clock counter can

be used to divide the R counter output to a smaller frequency suitable for the band selection logic.

Table 9E. Register 4: 1-Bit VCO Power Down. Function Description

Name

Description

Factory Default

Function

0 = VCO Powered Up

VCOPwrDwn

VCO POWER DOWN

0

1 = VCO Powered Down

Table 9F. Register 4: 1-Bit Mute Till Lock Detect. Function Description

Name

Description

Factory Default

Function

0 = Mute Disabled

1 = Mute Enabled

MTLD

0

Table 9G. Register 4: 1-Bit RF_OUTB Select. Function Description

Name

Description

Factory Default

Function

0 = Divided Output

1 = Fundamental

RF_OUTB_Sel

RF_OUTB SELECT

0

Table 9H. Register 4: 1-Bit RF_OUTB Enable. Function Description

Name

Description

Factory Default

Function

0 = Disabled (High-Impedance)

1 = Enabled¹

RF_OUTB_En

RF_OUTB ENABLE

0

NOTE 1. RF_OUT_Amust also be enabled.

Table 9I. Register 4: 1-Bit RF_OUTA Enable. Function Description

Name

Description

Factory Default

Function

0 = Disabled¹(High-Impedance)

1 = Enabled

RF_OUTA_En

RF_OUTA ENABLE

0

NOTE 1. RF_OUT_Bwill also disable.

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8V97053L Datasheet

1

Table 9J. Register 4: 2-Bit RF_OUTA Output Power. Function Description

Name

Description

Factory Default

Function

00 = -4dBm

01 = -1dBm

10 = +2dBm

11 = +5dBm

RF_OUTA_Pwr[2:1]

RF_OUTA OUTPUT POWER

10

NOTE 1. f_{RF_OUT}= 34.375MHz.

1

Table 9K. Register 4: 3-Bit Control Bits. Function Description

Name

Description

Function

100 = Register 4 is programmed

CB[3:1]

CONTROL BITS

NOTE 1. The user has to set CB[3:1] to 100 in order to write to Register 4.

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8V97053L Datasheet

Register 5

1

Table 10A. Register 5 Bit Allocation

CONTROL

BITS

RESERVED

NOTE 1. D19 and D20 must be set to 1.

Table 10B. Register 5: 2-Bit LD (Lock Detect) Pin Mode. Function Description

Name

Description

Factory Default

Function

00 = Low

01 = Digital Lock Detect

10 = Low

LDPInMode[2:1]

LD PIN MODE

01

11 = High

1

Table 10C. Register 5: 3-Bit Control Bits. Function Description

Name

Description

Function

CB[3:1]

CONTROL BITS

101 = Register 5 is programmed

NOTE 1. The user has to set CB[3:1] to 101 in order to write to Register 5.

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8V97053L Datasheet

Extended Registers, (Registers 6 and 7)

Register 6

1 2 3

Table 11A. Register 6 Bit Allocation

EXT_BND_SE CONTROL

RESERVED (RO)

L_DIV

BITS

NOTE 1. It is recommended that the user writes to Register 0 after writing to Register 6.

NOTE 2. Bit D7 must be set to 0 for correct operation.

NOTE 3. RO Bits are Read Only Bits.

Table 11B. Register 6: 1-Bit Digital Lock Detect. Function Description

Name

Description

Function

0 = PLL Not Locked

DigLock

DIGITAL LOCK

1 = PLL Locked (according LDF and LDP in Register 2)

Table 11C. Register 6: 1-Bit Band Select Status (Read Only). Function Description

Name

Description

Function

0 = Band Selection Not Complete

1 = Band Selection Complete

Band_select_done

BAND_SELECT_DONE

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1

Table 11D. Register 6: 2-Bit Extra Lock Detect Precision. Function Description

Function

Name

Description

Factory Default

Extra Bit

LDP Bits in Register 2

Value

10ns

6ns

0

1

0

1

0

1

0

1

00

3ns

01

10

11

3ns

LDP_EXT

LDP_Ext[2:1]

00

Extra Lock Detect Precision

4ns

4.5ns

1.5ns

NOTE 1. LDP_Ext[2:1] are Extra Lock Detect Precision bits. When these bits are set to 00, then the precision of the Lock Detect precision

only relies on the LDP bit in Register 2, so that the lock detect window is 10ns or 6ns, depending on the LDP bit in Register 2. For

high PFD frequencies, the 6ns window may be larger than the entire ref/FB period. The LDP_ext bits reduce the size of the lock

detect window to the value described in Table 11B, Page 36, allowing an accurate lock detection with higher PFD frequencies.

1 2

Table 11E. Register 6: 1-Bit Extra Bit of RF_OUTB Power. Function Description

Function

RF_OUTB OUTPUT POWER Bits

Name

Description

Factory Default

Extra Bit

in Register 4

Value (dBm)

00

01

10

11

00

01

10

11

-4

-1

0

+2

+5

+2

+5

+6

+7

rf_outb_hi_pwr

RF_OUTB_HI_PWR

0

1

NOTE 1. RF_OUTB_HI_PWR is an Extra Bit of RF_OUTB Power that increases the output power to the RF_OUT_Boutput.

NOTE 2. f_{RF_OUT}= 34.375MHz.

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8V97053L Datasheet

1 2

Table 11F. Register 6: 1-Bit Extra Bit of RF_OUTA Power. Function Description

Function

RF_OUTA OUTPUT POWER Bits

in Register 4

Name

Description

Factory Default

Extra Bit

Value (dBm)

00

01

10

11

00

01

10

11

-4

-1

0

+2

+5

+2

+5

+6

+7

rf_outa_hi_pwr

RF_OUTA_HI_PWR

0

1

NOTE 1. RF_OUTA_HI_PWR is an Extra Bit of RF_OUTA Power that increases the output power to the RF_OUT_Aoutput.

NOTE 2. f_{RF_OUT}= 34.375MHz.

Table 11G. Register 6: 2-Bit Sigma Delta Modulator Order Configuration. Function Description

Name

Description

Factory Default

Function

00 = OFF. The device operates in integer mode and the fractional

part is ignored.

01 = 1^storder

10 = 2^ndorder

11 = 3^rdorder

SDMOrder[2:1]

SDM_ORDER

11

Table 11H. Register 6: 2-Bit Dither Gain Configuration. Function Description

Name

Description

Factory Default

Function

0 = LSB Dither (Recommended)

1 = LSB x4 Dither

DitherG

DITHER GAIN

0

Table 11I. Register 6: 1-Bit Dither Noise Shaping Configuration. Function Description

Name

Description

Factory Default

Function

0 = Dither Noise Shaping Disabled

1 = Dither Noise Shaping Enabled

ShapeDitheren

SHAPE_DITHER_EN

1

Table 11J. Register 6: 1-Bit Sigma Delta Modulator Type Configuration. Function Description

Name

Description

Factory Default

Function

00 = Reserved

01 = SSMF-II

10 = SSMF-I

11 = SSMF-B

SDMType[2:1]

SDM_TYPE

01

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Table 11K. Register 6: 2-Bit VCO Band Selection Accuracy Configuration. Function Description

Name Description Factory Default Function

00 = 1 cycle of the band select clock (output of the Band Select Divider)

01 = 2 cycles

10 = 4 cycles

11 = Reserved

band_select_acc[2:1] BAND_SELECT_ACC 00

1 2

Table 11N. Register 6: 4-Bit Extra Most Significant Bits of Band Select Divider. Function Description

Name

Description

Factory Default

Value

Function

0000 = [BSCC_R4]

0001 =[BSCC_R4]+256

0010 = [BSCC_R4] + 512

….…

BSCC_R4 +

[EXT_BND_SEL_DIV]x256

ExtBndSelDiv[4:1]

EXT_BND_SEL_DIV

0000

1111 = [BSCC_R4]+3840

NOTE 1. EXT_BND_SEL_DIV are Extra 4 MSBs that extend the Band Select Clock Counter in Register 4. These additional bits are necessary

for band selection to divide down to <500kHz when high PFD frequencies are used.

NOTE 2. BSCC_R4 is the BAND SELECT CLOCK COUNTER value in Register 4.

1

Table 11O. Register 6: 3-Bit Control Bits. Function Description

Name

Description

Function

CB[3:1]

CONTROL BITS

110 = Register 6 is programmed

NOTE 1. The user has to set CB[3:1] to 110 in order to write to Register 6.

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8V97053L Datasheet

Register 7

1 2

Table 12A. Register 7 Bit Allocation

REV_ID

(RO)

CONTROL

BITS

DEV_ID (RO)

EXT_MOD

EXT_FRAC

NOTE 1. SB Bits are Sticky Bits and need to be cleared.

NOTE 2. RO Bits are Read Only Bits.

1

Table 12B. Register 7: 1-Bit Loss of Digital Lock. Function Description

Name

Description

Function

0 = Locked since last time register was cleared

Loss_Dig_Lock

LOSS_DIG_LOCK

1 = Loss of Digital Lock since last time register was cleared

NOTE 1. This bit is a sticky bit and needs to be cleared with a SPI write of 1 to detect further Loss of Digital Lock occurrences.

1

Table 12C. Register 7: 1-Bit Loss of Analog Lock. Function Description

Name

Description

Function

0 = Band Selection remained the same since last time register was cleared

1 = Band selection occurred since last time register was cleared

Loss_Anlg_Lock

LOSS_ANLG_LOCK

NOTE 1. This bit is a sticky bit and needs to be cleared with a SPI write of 1 to detect further Band Selection occurrences.

1

Table 12D. Register 7: 1-Bit SPI Error. Function Description

Name

Description

Function

0 = No SPI write error detection

1 = SPI Write error

Spi_error

SPI_ERROR

NOTE 1. Spi_error Bit goes high if the SPI interface detects a cycle with the incorrect number of SCLK cycles between nCS asserted Low

and nCS asserted High. The SPI interface expects 32 clock cycles between nCS asserted Low and nCS asserted High. Any

Read/Write via the SPI interface with more or less than 32 clock cycles will result in the Spi_error Bit switched to 1. This bit is a sticky

bit and needs to be cleared with a SPI write of 1 in order to detect further possible SPI Write/Read errors.

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Table 12E. Register 7: 3-Bit Revision ID. Function Description

Name

Description

Factory Default

Rev_ID[3:1]

REV_ID

001

Table 12F. Register 7: 4-Bit Device ID. Function Description

Name

Description

Factory Default

Dev_ID[4:1]

DEV_ID

0110

Table 12G. Register 7: 1-Bit Resolution Select. Function Description

Name

Description

Factory Default

Function

0 = FRAC, PHASE and MOD set to 12-Bit resolution,

Bit[D19:D8] set to 0 and unused

16b_12b_sel

16b_12b_SEL

0

1 = FRAC, PHASE and MOD set to 16-Bit resolution

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1

Table 12J. Register 7: 4-Bit Extra Bits of MOD Value. Function Description

Function

EXT_MOD

0000

Name

Description

Factory Default

MOD

Value

Not Allowed

0001

Not Allowed

0000 0000 0000

0000 0000 0001

1111 1111 1111

0010

2

. . . .

15

1111

0000

16

ext_mod[4:1]

EXT_MOD

0000

. . . .

31

1111

. . . .

0000

65520

. . . .

1111

65535

NOTE 1. Bit D20 in Register 7 (16b_12b_SEL) is required to be set to 1 when using this table. If Bit D20 in Register 7 (16b_12b_SEL) is set

to 0, refer to Table 6D, Page 25.

1

Table 12K. Register 7: 4-Bit Extra Bits of FRAC Value. Function Description

Function

Name

Description

Factory Default

FRAC

EXT_FRAC

0000

0001

. . . .

Value

0

1

0000 0000 0000

. . . .

15

1111

0000

. . . .

16

ext_fdiv[4:1]

EXT_FRAC

0000

0000 0000 0001

. . . .

31

1111

. . . .

0000

. . . .

65520

. . . .

1111 1111 1111

1111

65535

NOTE 1. Bit D20 in Register 7 (16b_12b_SEL) is required to be set to 1 when using this table. If Bit D20 in Register 7 (16b_12b_SEL) is set

to 0, refer to Table 5C, Page 22.

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8V97053L Datasheet

Table 12L. Register 7: 1-Bit SCLKE. Function Description

Name

Description

Factory Default

Function

0 = Output Data in a Read Cycle on a Rising Edge of SCLK

Sclke

SCLKE

1

1 = Output Data in a Read Cycle on a Falling Edge of

SCLK

1

Table 12M. Register 7: 1-Bit READBACK_ADDR. Function Description

Name

Description

Function

000 = Register 0

001 = Register 1

010 = Register 2

011 = Register 3

100 = Register 4

101 = Register 5

110 = Register 6

111 = Register 7

Rd_Addr[3:1]

READBACK_ADDR

NOTE 1. In order to Read a register, the user must write to Register 7 first and set the SPI_R_WN Bit to 1 (READ) and indicate the address

of the register to read in the READBACK_ADDR Bit (Bits[D6:D4]).

1

Table 12N. Register 7: 1-Bit SPI_R_WN. Function Description

Name

Description

Factory Default

Function

0 = WRITE

1 = READ

SPI_R_WN

0

NOTE 1. Writing this bit to a ‘1’ will allow the user to read back the register selected in READBACK_ADDR on the next 32 SCLK cycle. This

bit will revert back to ‘0’ once it is written with ‘1’ and will not retain the ‘1’ value.

1

Table 12O. Register 7: 3-Bit Control Bits. Function Description

Name

Description

Function

CB[3:1]

CONTROL BITS

111 = Register 7 is programmed

NOTE 1. The user has to set CB[3:1] to 111 in order to write to Register 7.

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8V97053L Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum

Ratings may cause permanent damage to the device. 

These ratings are stress specifications only. Functional operation of

product at these conditions or any conditions beyond 

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for 

extended periods may affect product reliability.

Table 13. Absolute Maximum Ratings

Item

Rating

3.63V

Supply Voltage, V_DDX

Analog Supply Voltage, V_DDA

Input, V_I

REF_IN

-0.5 to V_DDA+ 0.5V

Other Inputs (MUTE, SDI, FLSW, V_TUNE

)

Outputs, V_O

-0.5 to V_DDA+ 0.5V

RF_OUT_A-B, nRF_OUT_A-B

Outputs, V_O(SCLK, LD, nCS, MUX_OUT)

Outputs, I_O

Continuous Current

Surge Current

40mA

65mA

Outputs, I_O(SCLK, LD, nCS, MUX_OUT)

Continuous Current

8mA

13mA

Surge Current

Junction Temperature, T_J

Storage Temperature, T_STG

125°C

-65°C to 150°C

NOTE: V_DDXdenotes V_DDD,V_{_CP,}V_{DD_SD,}V_VCO.

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DC Electrical Characteristics

1 2 3

Table 14A. Power Supply DC Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T_A= -40°C to +85°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

Maximum

Units

V

V_DDX

V_DDA

Core Supply Voltage

3.3

95

3.465

105

Analog Supply Voltage

Power Supply Current

3.135

V

4

I_DDX

mA

RF_OUT_A/ nRF_OUT_A- Active

RF_OUT_B/ nRF_OUT_B- Muted

60

80

37

75

100

45

mA

RF_OUT_A/ nRF_OUT_A- Active

RF_OUT_B/ nRF_OUT_B- Active

5

I_DDA

Analog Supply Current

RF_OUT_A/ nRF_OUT_A- Muted

RF_OUT_B/ nRF_OUT_B- Muted

I_VCO

VCO Supply Current

Power Down Mode

60

15

mA

20

NOTE 1. V_DDXdenotes V_DDD,V_{_CP,}V_{DD_SD,}V_VCO.

NOTE 2. RF Outputs Terminated 50to V_DDA.

NOTE 3. Output Power set to +2dBm.

NOTE 4. I_DDXdenotes I_DDD+ I_{_CP}+ I_{DD_SD}+ I_VCO.

NOTE 5. I_DDAis dependent on the value of the M0 output divider. The numbers indicated for I_DDAshow the current consumption when using

the output divider M0 = 64, for which I_DDAis higher than when using any other M0 divider value.

1

Table 14B. Output Divider Incremental Current

Parameter

Test Conditions

Divide by 2

Minimum

Typical

8.0

Maximum

Units

mA

Divide by 4

7.0

Divide by 8

1.5

Output Divider Supply Current

Divide by 16

Divide by 32

Divide by 64

1.5

NOTE 1. RF Output divider (÷MO) has an incremental increase in current as the divider value increases. This specification is the incremental

current change per output divider step. For example, current of divide-by-2 is 8mA more than divide-by-1, current of divide-by-4 is

7mA more than divide-by-2, and so on. The total increase from ÷1 to ÷64 is 8mA + 7mA + 1.5mA + 1.5mA + 1.5mA + 1.5mA = 21mA.

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1

Table 14C. Typical Current by Power Domain

Pin Name

V_{_CP}

Pin Number

Typical Current

Unit

mA

6

24

15

0.5

6

V_VCO

16, 17

28

V_DDD

V_{DD_SD}

V_DDA

32

10

52

NOTE 1. Operating conditions are:

REF_IN = 25MHz

INT = 100 (integer mode)

RF Divider = ÷1

RF_OUT_A= RF_OUT_B= 2.5GHz

RF_POWER= -1dBm

Charge Pump = 0.31mA

1

Table 14D. LVCMOS DC Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

1.8

Typical

Maximum

Units

V

MUTE, CE

V_DDx

0.6

V_IH

Input High Voltage

Input Low Voltage

Input High Current

SDI, SCLK, nCS

1.5

V

V_IL

-0.3

V

SDI, MUTE, CE

SCLK, nCS

V_DDx= 3.465V, V_IN= 1.8V

5

µA

V

I_IH

150

SDI, MUTE, CE

SCLK, nCS

V

_DDx= 3.465V, V_IN= 0V

-150

-5

I_IL

Input Low Current

V

V_OH

V_OL

Output High Voltage MUX_OUT, LD

Output Low Voltage MUX_OUT, LD

V_DDx= 3.465V; I_OH= -500µA

V_DDx= 3.465V; I_OL= 500µA

V_DDX- 0.4

0.4

V

NOTE 1. V_DDXdenotes V_DDD,V_{_CP,}V_{DD_SD,}V_VCO.

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8V97053L Datasheet

AC Electrical Characteristics

1

Table 15A. AC Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Ref Doubler Disabled

Ref Doubler Enabled

Biased at V_DDA/2³

Minimum

Typical

Maximum

Units

MHz

V

5

310

100

REF_IN

Input Reference Frequency²

V_PP

Input Sensitivity

VCO Frequency

Output Frequency

REF_IN

0.7

V_DDA

4400

125

f_VCO

Fundamental VCO Mode

Divider Values: 1, 2, 4, 8, 16, 32, 64

Fractional Mode

2200

34.375

MHz

MHz/V

f_{RF_OUT}

f_PFD

PFD Frequency

Integer Mode

310

K_VCO

t_LOCK

VCO Sensitivity

PLL Lock Time

40

Time from Low to High nCS until

at Normal Mode, Low to High LD

200

µs

-

Output Power Variation

RF Output Power

±1

dB

dBm

V

Muted, (M0  1)

80

Min/Max VCO Tuning Voltage

0.5 / 2.5

NOTE 1. V_DDXdenotes V_DDD,V_{_CP,}V_{DD_SD,}V_VCO.

NOTE 2. For REF_IN <10MHz, the slew rate must be >21V/µs.

NOTE 3. AC-coupling the reference signal ensures V_DDA/2 biasing.

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8V97053L Datasheet

1 2

Table 15B. RF_OUT

Phase Noise and Jitter Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T = -40°C to 85°C

[A:B]

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f = 156.25MHz

Integration Range: 12kHz - 20MHz

220

218

166

fs

f = 2.05GHz

Integration Range: 12kHz - 20MHz

tjit(Ø)

RMS Phase Jitter (Random)

fs

f = 1.76GHz

Integration Range: 12kHz - 20MHz

_N(100k)

_N(800k)

_N(1M)

_N(5M)

_N(10M)

_N()

100kHz Offset from Carrier

800kHz Offset from Carrier

1MHz Offset from Carrier

5MHz Offset from Carrier

10MHz Offset from Carrier

Noise Floor (30MHz from Carrier)

100kHz Offset from Carrier

800kHz Offset from Carrier

1MHz Offset from Carrier

5MHz Offset from Carrier

10MHz Offset from Carrier

Noise Floor (30MHz from Carrier)

100kHz Offset from Carrier

800kHz Offset from Carrier

1MHz Offset from Carrier

5MHz Offset from Carrier

10MHz Offset from Carrier

Noise Floor (30MHz from Carrier)

100kHz Offset from Carrier

800kHz Offset from Carrier

1MHz Offset from Carrier

5MHz Offset from Carrier

10MHz Offset from Carrier

Noise Floor (30MHz from Carrier)

100kHz Offset from Carrier

800kHz Offset from Carrier

1MHz Offset from Carrier

5MHz Offset from Carrier

10MHz Offset from Carrier

Noise Floor (30MHz from Carrier)

-122.76

-146.18

-147.80

-155.36

-156.50

-157.31

-114.07

-136.57

-138.67

-151.50

-154.42

-155.93

-114.30

-139.19

-141.38

-152.70

-154.39

-155.79

-108.48

-131.19

-133.38

-147.77

-152.47

-155.77

-103.22

-127.59

-129.92

-145.39

-150.27

-153.72

dBc/Hz

RF Output

Phase Noise Performance

@ 745MHz (Open Loop)

_N(100k)

_N(800k)

_N(1M)

_N(5M)

_N(10M)

_N()

RF Output

Phase Noise Performance

@ 1.1GHz (Open Loop)

_N(100k)

_N(800k)

_N(1M)

_N(5M)

_N(10M)

_N()

RF Output

Phase Noise Performance

@ 1.65GHz (Open Loop)

_N(100k)

_N(800k)

_N(1M)

_N(5M)

_N(10M)

_N()

RF Output

Phase Noise Performance

@ 2.3GHz (Open Loop)

_N(100k)

_N(800k)

_N(1M)

_N(5M)

_N(10M)

_N()

RF Output

Phase Noise Performance

@ 3.8GHz (Open Loop)

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8V97053L Datasheet

1 2

Table 15B. RF_OUT

Phase Noise and Jitter Characteristics, V_DDX= V_DDA= 3.3V ± 5%, T = -40°C to 85°C

[A:B]

A

Symbol

_N(100k)

_N(800k)

_N(1M)

_N(5M)

_N(10M)

_N()

Parameter

Test Conditions

100kHz Offset from Carrier

800kHz Offset from Carrier

1MHz Offset from Carrier

5MHz Offset from Carrier

10MHz Offset from Carrier

Noise Floor (30MHz from Carrier)

Minimum

Typical

Maximum

Units

-100.26

-125.80

-128.17

-143.81

-148.47

-153.01

dBc/Hz

RF Output

Phase Noise Performance

@ 4.4GHz (Open Loop)

Spurious Signals

Due to PFD Frequency

f_PFD= 50MHz;

RF_OUT_A= 2.2GHz

-

-74

dBc

RF Output Phase Noise

Performance @ 745MHz

(Open Loop)

_N(100k)

100kHz Offset from Carrier

-106.75

dBc/Hz

NOTE 1. V_DDXdenotes V_DDD,V_{_CP,}V_{DD_SD,}V_VCO.

NOTE 2. RF_OUT_[A:B]output power setting = +2dBm.

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8V97053L Datasheet

Phase Noise (Closed-Loop) at 156.25MHz (3.3V)

Offset Frequency (Hz)

Phase Noise (Closed-Loop) at 1.76GHz (3.3V)

Offset Frequency (Hz)

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8V97053L Datasheet

Phase Noise (Closed-Loop) at 2.05GHz (3.3V)

Offset Frequency (Hz)

Phase Noise (Open-Loop) at 745MHz (3.3V)

Offset Frequency (Hz)

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August 18, 2016

8V97053L Datasheet

Phase Noise Performance (Open-Loop) at 1.1GHz (3.3V)

Offset Frequency (Hz)

Phase Noise Performance (Open-Loop) at 1.65GHz (3.3V)

Offset Frequency (Hz)

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August 18, 2016

8V97053L Datasheet

Phase Noise Performance (Open-Loop) at 2.3GHz (3.3V)

Offset Frequency (Hz)

Phase Noise Performance (Open-Loop) at 3.8GHz (3.3V)

Offset Frequency (Hz)

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August 18, 2016

8V97053L Datasheet

Phase Noise Performance (Open-Loop) at 4.4GHz (3.3V)

Offset Frequency (Hz)

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August 18, 2016

8V97053L Datasheet

Applications Information

Loop Filter Calculations

nd

2

Order Loop Filter

This section helps design a 2^ndorder loop filter for the 8V97053L. A general 2^ndorder loop filter is shown in Figure 11, Typical 2^ndOrder Loop

Filter. Step-by-step calculations to determine Rz, Cz and Cp values for a desired loop bandwidth are described below. Required parameters

are provided. A spreadsheet for calculating the loop filter values is also available.

R_Z

C_p

C_Z

Figure 11. Typical 2^ndOrder Loop Filter

1. Determine desired loop bandwidth fc.

2. Calculate Rz:

2* *fc* N

Rz 

Icp* Kvco

Where,

Icp is charge pump current. Icp is programmable from 310µA to 5mA.

N is effective feedback divider. N must be programmed into the following value.

Fvco

N 

Fpd

F_VCOis VCO frequency. 

VCO frequency range: 2200MHz to 4400MHz

Fpd is phase detector input frequency.

F _ ref

Fpd 

Pv

F_ref is reference clock (REF_IN) input frequency.

Pv is overall pre-divider setting.

Kvco is VCO gain. Kvco = 40MHz/V

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8V97053L Datasheet

3. Calculate Cz:



Cz 

2* * fc* Rz

Where,

 = fc/ fz, user can determine an  number. 

 > 6 is recommended.

fz is frequency at zero.

4. Calculate Cp:

Cz

Cp 

 * 

Where,

 = fp/fc, user can determine  number. 

 > 4 is recommended.

fp is frequency at pole.

5. Verify Phase Margin (PM)

Where,

Cz

b  1

Cp

The phase margin (PM) should be greater than 50°.

A spreadsheet for calculating the loop filter component values is available at www.IDT.com. To use the spreadsheet, the user simply enters the

following parameters:

fc, F_ref, P_V, Icp, F_VCO,  and .

The spreadsheet will provide the component values, Rz, Cz and Cp as the result. The spreadsheet also calculates the maximum phase margin

for verification.

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8V97053L Datasheet

3^rdOrder Loop Filter

This section helps design a 3^rdorder loop filter for the 8V97053L. A general 3^rdorder loop filter is shown in Figure 12, Typical 3rd Order Loop Filter

.

R_P2

Rp2

Rz

R_Z

C_P2

C

Cp

Cp2

P

C

Cz

Z

rd

Figure 12. Typical 3 Order Loop Filter

The Rz, Cz and Cp can be calculated as 2^ndorder loop filter. 

The following equation help determine the 3^rdorder loop filter Rp2 and Cp2.

Pick an Rp2 value. Rp2 ~ 1.5xRz is suggested.

Where,

 is ratio between the 1^stpole frequency and the 2^ndpole frequency. > 4 is recommended.

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullup and pulldown resistors; additional resistance is not required but can be added for additional protection. A

1k resistor can be used.

Outputs:

Output Pins

For any unused output, it can be left floating and disabled.

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8V97053L Datasheet

Schematic Example

Figure 13A and Figure 13B show general application schematic examples for the 8V97053L.

For power rails, bypass capacitors must be provided to all power supply pins. Suggest at least one bypass capacitor per power pin. Value can

be ranged from 0.01uF or 0.1uF. Mix values of bypass capacitor can help filtering wider range of power supply noise.

The 8V97053L input is high impedance. The input termination depends on the driver type termination requirements. In these examples, the

8V97053L REF_IN input is terminated with a matched load termination. For transmission line with characteristic impedance Zo = 50, the

termination resistor R8 is 50. The input is self biased to proper DC offset after the AC coupling.

The loop filter values can be calculated to meet the loop bandwidth requirement. Please refer to the section, "Loop Filter Calculations" for

detailed calculations. For fast lock mode, the loop filter can be configured as Fast Lock Loop Filter Option 1 or Fast Lock Loop Filter Option 2

shown in Figure 13A.

Fast Lock Loop Filter Option 1 is Parallel Resistor Configuration. For normal operating mode, only R5 is active and R5 = Rs, where Rs is the

resistor value for normal operating mode loop bandwidth. In fast lock mode, the combination of R4 in parallel with R5 is active. For example,

in normal operation mode, if the charge pump current is set at 0000 (ICP = 310uA), then, in fast lock mode, the loop bandwidth is set larger by

increasing the charge pump current to ICP~5mA (ICP setting = 1111 or 16 times the normal charge pump current). The combination of the R4

and R5 in parallel is 1/4 * Rs.

Fast Lock Loop Filter Option 2 is Series Resistor Configuration. 

For normal operating mode, both R6 and R7 are active and 

R6 + R7 = Rs. For fast lock mode, only R6 is active. For example, in normal operation mode, if the charge pump current is set at 0000 (ICP =

310uA), then, in fast lock mode, the loop bandwidth is set larger by increasing the charge pump current to ICP~5mA (ICP setting = 1111 or 16

times the normal charge pump current). 

The sum of R6 and R7 equals to Rs, i.e. R6 + R7 = Rs. 

R6 = 1/4 * Rs and R7 = 3/4 * Rs.

The 8V97053L output pull-up loading can be resistors or inductors. The pull up resistor value is typically 50. Resistor pull up loading covers

wide range of output frequencies. For inductor pull up loading, the inductor value is frequency dependent. One inductor value cannot cover all

the output frequency range. This example shows the L = 3.9nF that is suitable for approximately 2GHz operating frequency. The output can

also drive single ended LO input. Figure 13B shows an example of the 8V97053L output driving single ended LO input of the mixer through an

LC balun. The LC balun component values are frequency dependent. These values can be adjusted to optimize the performance. Single ended

LO receiver input also can tap to one side of the differential driver using resistor loading or inductor loading. For single ended LO input, both

sides of the differential driver still need to be loaded with pull up. The output power level can also be adjusted further through programming.

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August 18, 2016

8V97053L Datasheet

Inductor Loading

C1

C2

C3

C6

1u

VDD

C4

C5

10u

0.1u

10u

R1

4.7k

V_vco

L2

3.9n

L1

3.9n

Resistor Loading

nREF_OUTA

REF_OUTA

VDD

R2

50

R1

50

25

26

27

28

29

30

31

32

16

VDD

LD

VVCO

nRF_OUTB

RF_OUTB

nRF_OUTA

RF_OUTA

GNDA_VCO

VDDA

15

14

13

12

11

10

9

C7

1n

C8

1n

MUTE

Zdiff=100

GNDD

VDDD

REF_IN

MUX_OUT

GND_SD

VDD_SD

nREF_OUTA

REF_OUTA

C9

1n

RF Mixer

LO input

Zo = 50

R8

50

RF IN

GNDA

C10

33

E_PAD

1n

Zo = 50

U1

VDD

CP_OUT

VTUNE

SPI Compatible Serial Bus

C11

R5

R3

C12

C13

Loop Filter

All power supply pins require Bypass capacitors

without Fast Lock

Fast Lock Loop Filter Options 2

R3

Fast Lock Loop Filter Options 1

CP_OUT

C11

VTUNE

R3

CP_OUT

VTUNE

C13

C11

R6

R4

FLSW

C12

R5

C12

C13

R7

Figure 13A. An 8V97053L General Application Schematic Example

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August 18, 2016

8V97053L Datasheet

Resistor Loading

Inductor Loading

VDD

R2

50

R1

50

L2

L1

3.9n

C1

C2

nREF_OUTA

REF_OUTA

C3

C6

1u

nREF_OUTA

REF_OUTA

C4

C5

10u

0.1u

C9

0.1u

C9

0.1u

10u

R1

4.7k

V_v co

VDD

RF to IF Dual Down

converter Mixer

VDD

L2

L1

RFin_A

IFout_A

25

26

27

28

29

30

31

32

16

LD

VVCO

nRF_OUTB

RF_OUTB

nRF_OUTA

RF_OUTA

GNDA_VCO

VDDA

15

14

13

12

11

10

9

C7

1n

C8

1n

VDD

MUTE

C9

IDT F1100

IDT F1102

IDT F1150

IDT F1152

IDT F1160

IDT F1178

GNDD

VDDD

REF_IN

MUX_OUT

GND_SD

VDD_SD

LO input

Zo = 50

C14

RF IN

R8

50

GNDA

L3

33

E_PAD

C15

U1

RFin_B

IFout_B

VDD

R3

VTUNE

C13

SPI Compatible Serial Bus

C11

R5

R4

Optional

C12

All power supply pins require Bypass capacitors

Figure 13B. Schematic Example for Driving Single Ended Mixer

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8V97053L Datasheet

Power Considerations

The 8V97053L device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The

ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,

such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable

junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. The power calculation example below was

generated using a typical configuration. For many applications, the power consumption can vary depending on configuration. Please contact

IDT technical support for any concerns on calculating the power dissipation for your own specific configuration.

Example 1: VCO Frequency Range = 1991MHz to 2846MHz

1. Power Dissipation.

The total power dissipation for the 8V97053L is the sum of the core power plus the power dissipation in the output driver. 

The following is the power dissipation for V_DD= 3.465V, which gives worse case results.

•

Power (core)_MAX= V_{DD_MAX}* (I_DDA+ I_VCO+ I_CP+ I_{DD_SD}+ I_{DDD MAX}

)

= V_{DD_MAX}* (I_DDA+ I_DDX)_MAX= 

3.465V * (100mA + 105) = 710.33mW

Total Power (with two outputs active at 2dBm output power level) = 710.33mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 34.34°C/W per Table 16 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs active is:

85°C + 0.710W * 34.34°C/W = 109.39°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 16. Thermal Resistance _JAfor 32 Lead VFQFN, Forced Convection



_JAby Velocity

0

Meters per Second

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

34.34°C/W

30.7°C/W

29.12°C/W

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August 18, 2016

8V97053L Datasheet

Example 2: VCO Frequency Range = 2590MHz to 3624MHz

1. Power Dissipation.

The total power dissipation for the 8V97053L is the sum of the core power plus the power dissipation in the output driver. 

The following is the power dissipation for V_DD= 3.465V, which gives worse case results.

•

Power (core)_MAX= V_{DD_MAX}* (I_DDA+ I_VCO+ I_CP+ I_{DD_SD}+ I_{DDD MAX}

)

= V_{DD_MAX}* (I_DDA+ I_DDX)_MAX= 

3.465V * (90mA + 95mA) = 640mW

Total Power (with two outputs active at 2dBm output power level) = 640mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 34.34°C/W per Table 16.

Therefore, Tj for an ambient temperature of 85°C with all outputs active is:

85°C + 0.640W * 34.34°C/W = 107°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

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8V97053L Datasheet

Reliability Information

Table 17A. _JAvs. Air Flow Table for a 32 lead VFQFN

_JAvs. Air Flow

Meters per Second

0

1

2

Multi-Layer PCB, JEDEC Standard Test Boards

34.34°C/W

30.7°C/W

29.12°C/W

Table 17B. _JBvs. Air Flow Table for a 32 lead VFQFN



_JBvs. Air Flow

Meters per Second

0

Multi-Layer PCB, JEDEC Standard Test Boards

0.472°C/W

NOTE: _JBis independent of airflow.

Transistor Count

The 8V97053L transistor count is: 404,777

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August 18, 2016

8V97053L Datasheet

32-Lead VFQFN Package Outline and Package Dimensions

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8V97053L Datasheet

32-Lead VFQFN Package Outline and Package Dimensions (Continued)

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August 18, 2016

8V97053L Datasheet

Ordering Information

Table 18. Ordering Information

Part/Order Number

8V97053LNLGI

Marking

Package

Shipping Packaging

Tray

Temperature

-40°C to +85°C

IDT8V97053LNLGI

32-lead VFQFN, Lead Free

8V97053LNLGI8

8V97053LNLGI/W

Tape & Reel

Table 19. Pin 1 Orientation in Tape and Reel Packaging

Part Number Suffix

Pin 1 Orientation

Illustration

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

Correct Pin 1 ORIENTATION

NLGI8

Quadrant 1 (EIA-481-C)

USER DIRECTION OF FEED

Correct Pin 1 ORIENTATION

CARRIER TAPE TOPSIDE

(Round Sprocket Holes)

NLGI/W

Quadrant 2 (EIA-481-D)

USER DIRECTION OF FEED

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August 18, 2016

8V97053L Datasheet

Revision History

Revision Date

Description of Change

This is the first release of the 8V97053L Datasheet.

August 18, 2016

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August 18, 2016

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Fax: 408-284-2775

www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether

express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

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型号：	8V97053LNLGI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Power Wideband Fractional RF Synthesizer / PLL
文件：	总68页 (文件大小：1094K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V97053LNLGI8 [IDT]

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