8V31012_技术文档

1-to-12, Differential HCSL Fanout Buffer

8V31012

DATA SHEET

General Description

Features

The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The

8V31012 is designed to translate any differential signal levels to

differential HCSL output levels. An external reference resistor is

used to set the value of the current supplied to an external

load/termination resistor. The load resistor value is chosen to equal

the value of the characteristic line impedance of 50. The 8V31012

is characterized at an operating supply voltage of 3.3V.

• Twelve differential HCSL outputs

• Translates any differential input signal (LVPECL, LVHSTL, LVDS,

HCSL) to HCSL levels without external bias networks

• Maximum output frequency: 250MHz

• Output skew: 265ps (typical)

• V_OH:850mV (maximum)

• Full 3.3V supply voltage

• Available in lead-free (RoHS 6) package

• -40°C to 85°C ambient operating temperature

The differential HCSL outputs, accurate crossover voltage and duty

cycle make the 8V31012 ideal for interfacing to PCI Express and

FBDIMM applications.

Block Diagram

Pin Assignment

CLK

nCLK

48 47 46 45 44 43 42 41 40 39 38 37

Q0

Q6

nQ6

36

35

34

33

32

31

30

29

28

27

26

25

1

V_DD

nQ9

Q9

Q0

nQ0

V_DD

Q1

nQ0

2

3

Q1

nQ1

Q7

nQ7

4

GND

nQ8

Q8

5

nQ1

GND

Q2

nQ2

Q8

nQ8

6

8V31012

7

V_DD

nQ7

Q7

8

nQ2

V_DD

Q3

Q9

nQ9

9

nQ3

10

11

12

V_DD

nQ6

Q6

Q4

Q10

nQ10

nQ3

V_DD

nQ4

13 14 15 16 17 18 19 20 21 22 23 24

Q11

Q5

nQ11

nQ5

IREF

48-pin, 7mm x 7mm VFQFN Package

8V31012 REVISION 1 10/21/15

1

8V31012 DATA SHEET

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Q0

Type

Output

Power

Output

Power

Output

Power

Output

Power

Description

1

2

Differential output pair. Differential HCSL interface levels.

Power supply pin.

nQ0

V_DD

Q1

3

4

Differential output pair. Differential HCSL interface levels.

Power supply ground.

5

nQ1

GND

Q2

6

7

Differential output pair. Differential HCSL interface levels.

Power supply pin.

8

nQ2

V_DD

Q3

9

10

11

12

13

Differential output pair. Differential HCSL interface levels.

Power supply pin.

nQ3

V_DD

GND

Power supply ground.

External fixed precision resistor (950) from this pin to ground provides a reference current

used for differential current-mode Qx, nQx clock outputs.

14

IREF

Input

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Q4

nQ4

V_DD

Q5

Output

Power

Output

Power

unused

Power

Output

Power

Output

Power

Differential output pair. Differential HCSL interface levels.

Power supply pin.

Differential output pair. Differential HCSL interface levels.

Power supply pin.

nQ5

V_DD

nc

Power supply pin.

No connect.

V_DD

GND

Q6

Power supply pin.

Power supply ground.

Differential output pair. Differential HCSL interface levels.

Power supply pin.

nQ6

V_DD

Q7

Differential output pair. Differential HCSL interface levels.

Power supply pin.

nQ7

V_DD

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

2

REVISION 1 10/21/15

8V31012 DATA SHEET

Table 1. Pin Descriptions

Number

31

Name

Q8

Type

Output

Power

Output

Power

Input

Description

Differential output pair. Differential HCSL interface levels.

Power supply ground.

32

nQ8

GND

Q9

33

34

Differential output pair. Differential HCSL interface levels.

Power supply pin.

35

nQ9

V_DD

GND

CLK

nCLK

V_DD

nc

36

37

Power supply ground.

38

Non-inverting differential input.

39

Input

Inverting differential clock input.

40

Power

unused

Output

Power

Output

unused

Power

Power supply pin.

41

No connect.

42

Q10

nQ10

V_DD

Q11

nQ11

nc

Differential output pair. Differential HCSL interface levels.

Power supply pin.

43

44

45

Differential output pair. Differential HCSL interface levels.

No connect.

46

47

48

V_DD

Power supply pin.

Output Driver Current

The 8V31012 outputs are HCSL differential current drive with

the current being set with a resistor from I_REFto ground. For

a single load and a 50 PC board trace, the drive current would

typically be set with a R_REFof 950 which products an I_REFof 1.16mA.

The I_REFis multiplied by a current mirror to an output drive of

12*1.16mA or 13.90mA. See Figure 1 for current mirror and output

drive details.

IREF

RREF

950Ω

RL

Figure 1. HCSL Current Mirror and Output Drive

REVISION 1 10/21/15

3

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond 

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for 

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

Inputs, V_I

4.6V

-0.5V to V_DD+ 0.5V

125°C

Outputs, I_O

Maximum Junction Temperature

Storage Temperature, T_STG

-65C to 150C

DC Electrical Characteristics

Table 2A. Power Supply DC Characteristics, V_DD= 3.3V 5%, T_A= -40°C to 85°C

Symbol Parameter

V_DDCore Supply Voltage

I_DDPower Supply Current

Test Conditions

Minimum

Typical

Maximum

3.465

Units

V

3.135

3.3

Output Unterminated

105

mA

Table 2B. Differential DC Characteristics, V_DD= 3.3V 5%, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

I_IH

CLK, nCLK

V_DD= V_IN= 3.465V

5

µA

High Current

Input

I_IL

V_DD= 3.465V, V_IN= 0V

5

µA

Low Current

V_PP

Peak-to-Peak Voltage¹

0.15

1.3

V

V_CMR

Common Mode Input Voltage^{1, 2}

GND + 0.5

V_DD– 0.85

NOTE 1. V_ILshould not be less than -0.3V.

NOTE 2. Common mode input voltage is defined as V_IH.

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

4

REVISION 1 10/21/15

8V31012 DATA SHEET

AC Electrical Characteristics

1, 2, 3

Table 3. HCSL AC Characteristics, V_DD= 3.3V 5%, T_A= -40°C to 85°C

Symbol

f_MAX

Parameter

Test Conditions

Minimum

Typical

Maximum

250

Units

MHz

ns

Output Frequency

Propagation Delay⁴

Output Skew^{5, 6}

Part-to-Part Skew^{6, 7}

t_PD

Measured on at V_OX

2.35

265

335

2.75

tsk(o)

tsk(pp)

395

ps

Buffer Additive Phase Jitter, RMS; refer

to Additive Phase Jitter Section

CLK = 200MHz, Integration

Range: 12kHz – 30MHz

tjit

0.15

ps

V_MAX

Absolute Max Output Voltage⁸

Absolute Min Output Voltage⁸

Absolute Crossing Voltage^{9, 10, 11}

ƒ  150MHz

500

-150

250

850

150

550

mV

V_MIN

V_CROSS

Total Variation of V_CROSSover all

edges^{9, 10, 12}

V_CROSS

140

mV

Rise/Fall Edge Rate^{13, 14}

Rise/Fall Time Matching¹⁵

Output Duty Cycle¹⁶

0.6

45

4.0

20

55

V/ns

%

odc

%

NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE 2. Current adjust set for V_OH= 0.7V. Measurements refer to PCIEX outputs only.

NOTE 3. Characterized using an R_REFvalue of 950 resistor.

NOTE 4. Measured from the differential input cross point to the differential output crossing point.

NOTE 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output

cross point.

NOTE 6. This parameter is defined in accordance with JEDEC Standard 65.

NOTE 7. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.

NOTE 8. Measurement using R_REF= 950, R_LOAD= 50.

NOTE 9. Measurement taken from single-ended waveform.

NOTE 10. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.

See Parameter Measurement Information Section.

NOTE 11. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement. See Parameter Measurement Information Section.

NOTE 12. Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the

V_CROSSfor any particular system. See Parameter Measurement Information Section.

NOTE 13. Measurement taken from differential waveform.

NOTE 14. Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic

through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

NOTE 15. Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a 75mV window centered on the

median cross point where Qx rising meets nQx falling.

NOTE 16. Assuming 50% input duty cycle. Data taken at ƒ 200MHz, unless otherwise specified.

REVISION 1 10/21/15

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1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have

issues relating to the limitations of the measurement equipment. The

noise floor of the equipment can be higher or lower than the noise

floor of the device. Additive phase noise is dependent on both the

noise floor of the input source and measurement equipment.

The additive phase jitter for this device was measured using a

Stanford Research Systems CG635 input source and an Agilent

E5052 phase noise analyzer.

REVISION 1 10/21/15

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1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

Applications Information

Recommendations for Unused Output Pins

Outputs:

Differential Outputs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage V₁= V_DD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V₁in the center of the input voltage swing. For

example, if the input clock is driven from a single-ended 2.5V

LVCMOS driver and the DC offset (or swing center) of this signal is

1.25V, the R1 and R2 values should be adjusted to set the V1 at

1.25V. The values below are for when both the single ended swing

and V_DDare at the same voltage. This configuration requires that the

sum of the output impedance of the driver (Ro) and the series

resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the input will attenuate the signal in half. This

can be done in one of two ways. First, R3 and R4 in parallel should

equal the transmission line impedance. For most 50 applications,

R3 and R4 can be 100. The values of the resistors can be increased

to reduce the loading for slower and weaker LVCMOS driver. When

using single-ended signaling, the noise rejection benefits of

differential signaling are reduced. Even though the differential input

can handle full rail LVCMOS signaling, it is recommended that the

amplitude be reduced while maintaining an edge rate faster than 

1V/ns. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_DD+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

REVISION 1 10/21/15

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1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

Differential Clock Input Interface

The CLK/nCLK accepts HCSL, LVDS, LVPECL and LVHSTL and

other differential signals. Both differential signals must meet the V_PP

and V_CMRinput requirements. Figure 3A to Figure 3E show interface

examples for the CLK, nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

Figure 3A. CLK/nCLK Input Driven by an IDT

Open Emitter LVHSTL Driver

Figure 3D. CLK/nCLK Input Driven by a 

3.3V LVPECL Driver

3.3V

R3

125

R4

125

3.3V

Zo = 50Ω

CLK

R1

100

nCLK

Zo = 50Ω

Differential

Input

LVPECL

Differential

Input

LVDS

R1

84

R2

84

Figure 3B. CLK/nCLK Input Driven by a 

Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver

3.3V LVPECL Driver

3.3V

*R3

CLK

nCLK

Differential

Input

*R4

HCSL

Figure 3C. CLK/nCLK Input Driven by a

3.3V HCSL Driver

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8

REVISION 1 10/21/15

8V31012 DATA SHEET

Recommended Termination

Figure 4A is the recommended source termination for applications

where the driver and receiver will be on a separate PCBs. This

termination is the standard for PCI Express™and HCSL output types.

All traces should be 50Ω impedance single-ended or 100Ω

differential.

Rs

0.5" Max

L1

0-0.2"

L2

1-14"

L4

0.5 - 3.5"

L5

22 to 33 +/-5%

L1

L2

L4

L5

PCI Express

Connector

PCI Express

Driver

PCI Express

Add-in Card

0-0.2" L3

L3

49.9 +/- 5%

Rt

Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)

Figure 4B is the recommended termination for applications where a

point-to-point connection can be used. A point-to-point connection

contains both the driver and the receiver on the same PCB. With a

matched termination at the receiver, transmission-line reflections will

be minimized. In addition, a series resistor (Rs) at the driver offers

flexibility and can help dampen unwanted reflections. The optional

resistor can range from 0Ω to 33Ω. All traces should be 50Ω

impedance single-ended or 100Ω differential.

Rs

0.5" Max

L1

0-18"

L2

0-0.2"

L3

0 to 33

L1

L2

L3

PCI Express

Driver

49.9 +/- 5%

Rt

Figure 4B. Recommended Termination (where a point-to-point connection can be used)

REVISION 1 10/21/15

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1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 5. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

LAND PATTERN

(GROUND PAD)

PIN PAD

GROUND PLANE

PIN PAD

THERMAL VIA

Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

10

REVISION 1 10/21/15

8V31012 DATA SHEET

Power Considerations

This section provides information on power dissipation and junction temperature for the 8V31012. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 8V31012 is the sum of the core power plus the power dissipated in the load(s). 

The following is the power dissipation for V_DD= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.



Power (core)_MAX= V_{DD_MAX}* (I_{DD_MAX}) = 3.465V *(105mA) = 363.825mW

•

Power (outputs)_MAX= 44.5mW/Loaded Output pair

If all outputs are loaded, the total power is 12 * 44.5mW = 534mW

Total Power__MAX= (3.465V, with all outputs switching) = 363.825mW + 534mW = 897.825mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 29°C/W per Table 4 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.898W *29°C/W = 111°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 4. Thermal Resistance  for 48Lead VFQFN, E-Pad, Forced Convection

JA

_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

29.0°C/W

25.4°C/W

22.7°C/W

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1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

3. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.

HCSL output driver circuit and termination are shown in Figure 6.

VDDO

I_OUT= 17mA

V_OUT

R_REF

=

⁴⁷⁵Ω 1%

R_L

50Ω

IC

Figure 6. HCSL Driver Circuit and Termination

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,

use the following equations which assume a 50 load to ground.

The highest power dissipation occurs when V_{DDO MAX}.

_

Power = (V_{DDO_MAX}– V_OUT) * I_{OUT }

,

since V_OUT– I_OUT* R_L

= (V_{DDO_MAX}– I_OUT* R_L) * I_OUT

= (3.465V – 17mA * 50) * 17mA

Total Power Dissipation per output pair = 44.5mW

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

12

REVISION 1 10/21/15

8V31012 DATA SHEET

Reliability Information

Table 5. _JAvs. Air Flow Table for a 48 Lead VFQFN, E-Pad, Forced Convention

_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

29.0°C/W

25.4°C/W

22.7°C/W

Transistor Count

The transistor count for 8V31012 is: 843

REVISION 1 10/21/15

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8V31012 DATA SHEET

48-Lead VFQFN (NL) Package Outline and Package Dimensions

1

Table 6. Package Dimensions for 48-Lead Package

DIMENSIONS

SYMBOL

MIN

NOM

7.00 BSC

5.65

MAX

D

E

D2

E2

L

5.50

0.35

5.80

0.45

5.65

0.40

e

0.50 BSC

48

N

A

0.80

0.00

0.85

0.90

0.05

A1

A3

b

0.02

0.2 REF

0.25

0.18

0.30

NOTE 1. The drawing and dimension data originates from IDT

Package Outline Drawing PSC-4203, Rev 04.

All dimensions are in millimeters. All angles are in

degrees.

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

14

REVISION 1 10/21/15

8V31012 DATA SHEET

Package Outline and Package Dimensions (Continued)

RECOMMENDED LAND PATTERN

NOTE:

THE RECOMMENDED LAND PATTERN ORIGINATES FROM IDT PACKAGE

OUTLINE DRAWING PSC‐4203, REV04.

1. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN

DEGREES.

2. TOP DOWN VIEW. AS VIEWED ON PCB.

3. COMPONENT OUTLINE SHOW FOR REFERENCE IN BLACK.

4. LAND PATTERN IN BLUE. NSMD PATTERN ASSUMED.

5. LAND PATTERN RECOMMENDATION PER IPC‐7351B GENERIC

REQUIREMENT FOR SURFACE MOUNT DESIGN AND LAND

PATTERN.

REVISION 1 10/21/15

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1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

8V31012 DATA SHEET

Ordering Information

Table 7. Ordering Information

Part/Order Number

8V31012NLGI

Marking

Package

Shipping Packaging

Tray

Temperature

-40°C to 85°C

IDT8V31012NLGI

48 Lead VFQFN, Lead-Free

8V31012NLGI8

Tape & Reel

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

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REVISION 1 10/21/15

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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether

express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or

other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as

those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any

circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected

names, logos and designs, are the property of IDT or their respective third party owners.


型号：	8V31012
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	1-to-12, Differential HCSL Fanout Buffer
文件：	总17页 (文件大小：455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V31012 [IDT]

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