8V19N478BDGI_技术文档

®

FemtoClock NG Jitter Attenuator

8V19N478

Datasheet

and Clock Synthesizer

Description

Features

▪ High-performance clock RF-PLL:

The 8V19N478 is a fully integrated FemtoClock NG jitter

attenuator and clock synthesizer designed as a high-performance

clock solution for conditioning and frequency/phase management

of 10/40/100/400 Gigabit-Ethernet line cards. The device is

optimized to deliver excellent phase noise performance as

required to drive physical layer devices, and provides the clean

clock frequencies of 625MHz, 500MHz, 312.5MHz, 250MHz,

156.25MHz, and 125MHz.

ꢀ Optimized for low phase noise: -157.7dBc/Hz (1MHz offset;

156.25MHz clock), design target

ꢀ Integrated phase noise, RMS (12kHz–20MHz): 73fs

(typical), design target

▪ Dual-PLL architecture:

ꢀ 1st-PLL stage with external VCXO for clock jitter attenuation

ꢀ 2nd-PLL stage with internal FemtoClock NG PLL at

A two-stage PLL architecture supports both jitter attenuation and

frequency multiplication. The first stage PLL is the jitter attenuator,

and uses an external VCXO for best possible phase noise

characteristics. The second stage PLL locks on the VCXO-PLL

output signal, and synthesizes the target frequency. This PLL has

a VCO circuit at 2500MHz.

2500MHz

▪ Four output banks with a total of 18 outputs, organized in:

ꢀ Three clock banks with one integer frequency divider and

four differential outputs

ꢀ One clock bank with one fractional divider and six

differential outputs

The 8V19N478 generates the output clock signals from the VCO

by frequency division. Four independent frequency dividers are

available; three support integer-divider ratios, and one integer as

well as fractional-divider ratios. Delay circuits can be used for

achieving alignment and controlled phase delay between clock

signals. The two redundant inputs are monitored for activity. Four

selectable clock switching modes are provided to handle clock

input failure scenarios. Auto-lock, individually programmable

output frequency dividers, and phase adjustment capabilities are

added for flexibility.

ꢀ One VCXO-PLL output bank with one selectable LVDS and

two LVCMOS outputs

▪ Four output banks contain a phase delay circuit with steps of

the VCO clock period (400ps)

▪ Supported clock output frequencies include:

ꢀ From the integer dividers: 2500MHz, 1250MHz, 625MHz,

500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz

ꢀ From the fractional divider: 80–300MHz

▪ Low-power LVPECL and LVDS outputs support configurable

signal amplitude, DC and AC coupling, and LVPECL, LVDS,

and line termination techniques

The device is configured through an I²C interface and reports lock

and signal loss status in internal registers and via a lock detect

(LOCK) output. Internal status bit changes can also be reported

via the nINT output. The device is ideal for driving converter

circuits in wireless infrastructure, radar/imaging, and

▪ Redundant input clock architecture:

ꢀ Two inputs

ꢀ Individual input signal monitor

ꢀ Digital holdover

instrumentation/medical applications. The device is a member of

the high-performance clock family from IDT.

ꢀ Manual and automatic clock selection

ꢀ Hitless switching

▪ Status monitoring and fault reporting:

Typical Applications

▪ Sub 70fs – low phase noise clock generation

▪ 10/40/100 Gigabit-Ethernet line cards

▪ Wireless Infrastructure

ꢀ Input signal status

ꢀ Hold-over and reference loss status

ꢀ Lock status with one status pin

ꢀ Mask-able status interrupt pin

▪ Voltage supply:

▪ Reference clock for ADC and DAC circuits

▪ Radar and Imaging

▪ Instrumentation and Medical

ꢀ Device core supply voltage: 3.3V

ꢀ Output supply voltage: 3.3V, 2.5V, or 1.8V

ꢀ I/O voltage: 1.8V or 3.3V (selectable), and 3.3V tolerant

inputs when set to 1.8V

▪ Package: 11  11  1 mm ball pitch 100-FPBGA

▪ Temperature range: -40°C to +85°C

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May 15, 2018

8V19N478 Datasheet

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Principles of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Phase-Locked Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Frequency Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

VCXO-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

FemtoClock NG PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Channel Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Redundant Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input Re-Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Holdover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Manual Holdover Control (nHO_EN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Automatic with Holdover (nHO_EN = 1, nM/A[1:0] = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Hold-off Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revertive Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

VCXO-PLL Lock Detect (LOLV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FemtoClock NG Loss-of-lock (LOLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Output Phase-Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Status Conditions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Serial Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Control Port Configuration Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

I2C Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PLL Frequency Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Input Selection Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Clock Phase Noise Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

VCXO-PLL Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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8V19N478 Datasheet

Step-by-step Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

FemtoClock NG PLL Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

LVPECL-style Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

LVDS-Style Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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8V19N478 Datasheet

Block Diagram

VCXO-PLL

Loop Filter

VDD_LCF

R_Z

C_Z

4.7µF

C_P

CLK_0

nCLK_0

8V19N478

Clock

Monitor

and

Selector

CR

÷P_V

÷M_V

BYPV

CLK_1

nCLK_1

FDF

OSC

nOSC

÷P_F

x2

PFD

CP

LFV

PFD

CP

EXT_SEL

f_VCO

2400-2500MHz

LFF

C_PF

Dual FemtoClockNG

C_ZF

R_ZF

FemtoClock NG

PLL Loop Filter

÷M_F

Holdover

SRC

0

1

LFFR

QCLK_V

nQCLK_V

VCXO-PLL Channel

QCLK_A[0:3]

nQCLK_A[0:3]

÷N_A

(int)

_CLKA

QCLK_B[0:3]

nQCLK_B[0:3]

÷N_B

(int)

_CLKB

_CLKC

_CLKD

RES_CAL

2.8k

QCLK_C[0:3]

nQCLK_C[0:3]

÷N_C

(int)

QCLK_D[0:5]

nQCLK_D[0:5]

÷N_D

(frac)

ADR0

ADR1

ADR2

ADR3

SCL

nINT

I²C

1.8V/3.3V

LOCK

Register

File

SDAT

I2C_A

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May 15, 2018

8V19N478 Datasheet

Pin Assignments

Figure 1. Pin Assignments for 11  11  1 mm, 100-FPBGA Package (Bottom View )

nQCLK

_A0

QCLK

_A0

QCLK

_D0

QCLK

_D1

QCLK

_D2

A

B

C

D

E

F

RES-CAL

EXT_SEL

GND

VDD_CPV

LFV

nOSC

OSC

nQCLK_V

QCLK_V

nINT

VDD_OSC

I2C_A

VDD_I2C

SDAT

SCL

nQCLK

_A1

nQCLK

_D0

nQCLK

_D1

nQCLK

_D2

QCLK_A1

nQCLK

_A2

QCLK

_A2

QCLK

_D3

QCLK

_D4

VDD_INP

CLK_0

nCLK_0

GND

LOCK

CLK_1

nCLK_1

GND

nQCLK

_A3

QCLK

_A3

nQCLK

_D3

nQCLK

_D4

GND

ADR3

VDDO

_QCLKA

VDD

_QCLKA

nQCLK

_D5

QCLK

_D5

GND

ADR2

VDD

_QCLKD

VDDO

_QCLKD

GND

ADR1

ADR0

GND

nQCLK

_B0

QCLK

_B0

VDD

_QCLKB

VDD

_QCLKC

G

H

J

VDD_CPF

GND

nQCLK

_B1

QCLK

_B1

VDDO

_QCLKB

VDDO

_QCLKC

QCLK

_C0

nQCLK

_C0

CLDO

CR

CBIAS

VDD_LCV

GND

nQCLK

_B2

QCLK

_B2

nQCLK

_C3

QCLK

_C1

nQCLK

_C1

GND

nQCLK

_B3

QCLK

_B3

QCLK

_C3

QCLK

_C2

nQCLK

_C2

K

GND

LFF

LFFR

VDD_LCF

GND

10

9

8

7

6

5

4

3

2

1

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May 15, 2018

8V19N478 Datasheet

Pin Descriptions

[a]

Table 1. Pin Descriptions

[b]

Ball

Name

Type

Description

A10

A9

A8

A7

A6

nQCLK_A0

QCLK_A0

RES_CAL

Output

Analog

Power

Differential clock output A0 (Channel A). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKA

Connect a 2.8k (1%) resistor to GND for output current calibration.

V

Positive supply voltage (3.3V) for internal VCXO_PLL circuits.

DD_CPV

nOSC

Input (PD/ PU)

VCXO non-inverting and inverting differential clock input. Compatible with LVPECL,

LVDS and LVCMOS signals.

A5

nQCLK_V

Output

Differential VCXO-PLL clock outputs. Selectable LVPECL, LVDS (2x LVCMOS 1.8V)

style.

A4

A3

V

Power

Output

Positive supply voltage (3.3V) for the VCXO input.

DD_OSC

QCLK_D0

QCLK_D1

QCLK_D2

Differential clock output D0 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKD

A2

A1

Output

Differential clock output D1 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKD

Differential clock output D2 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKD

B10

B9

B8

B7

B6

nQCLK_A1

QCLK_A1

EXT_SEL

LFV

Output

Differential clock output A1 (Channel A). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKA

Input (PD)

Output

Clock reference select. 1.8V interface levels with hysteresis and 3.3V tolerance.

VCXO-PLL charge-pump output. Connect to the loop filter for the external VCXO.

OSC

Input (PD)

VCXO non-inverting and inverting differential clock input. Compatible with LVPECL,

LVDS and LVCMOS signals.

B5

QCLK_V

Output

Differential VCXO-PLL clock outputs. Selectable LVPECL, LVDS/(2x LVCMOS 1.8V)

style.

2

B4

B3

I2C_A

Input (PD/ PU)

Output

Serial Interface I C addresses. Three-level signals (see Table 15).

nQCLK_D0

Differential clock output D0 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKD

B2

B1

nQCLK_D1

nQCLK_D2

Output

Differential clock output D1 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKD

Differential clock output D2 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKD

C10

C9

C8

C7

C6

nQCLK_A2

QCLK_A2

GND

Output

Power

Output

Differential clock output A2 (Channel A). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKA

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Positive supply voltage (3.3V) for the differential inputs (CLK[1:0]).

V

DD_INP

LOCK

PLL lock detect status output for both PLLs. Selectable 1.8V/3.3V LVCMOS/LVTTL

interface levels.

C5

nINT

Output

Status output pin for signaling internal changed conditions. Selectable 1.8V/3.3V

LVCMOS/LVTTL interface levels.

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May 15, 2018

8V19N478 Datasheet

Table 1. Pin Descriptions (Cont.)^[a]

[b]

Ball

Name

Type

Description

Positive supply voltage (3.3V) for I2C_A.

C4

C3

C2

V

Power

Output

DD_I2C

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Differential clock output D3 (Channel D). Configurable LVPECL, LVDS style and

QCLK_D3

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKD

C1

QCLK_D4

Output

Differential clock output D4 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKD

D10

D9

nQCLK_A3

QCLK_A3

GND

Output

Differential clock output A3 (Channel A). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKA

D8

Power

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Device clock 0 inverting and non-inverting differential clock input. Inverting input is

D7

CLK_0

Input (PD)

biased to V

/2 by default when left floating. Compatible with LVPECL, LVDS and

DD_V

LVCMOS signals.

D6

CLK_1

Input (PD)

Device clock 1 inverting and non-inverting differential clock input. Inverting input is

biased to V

/2 by default when left floating. Compatible with LVPECL, LVDS and

DD_V

LVCMOS signals.

D5

D4

D3

D2

ADR3

SDAT

Input (PU/PD)

I/O (PU)

Power

Device mode selection (see Table 12).

2

I C data input/output. 1.8V interface levels with hysteresis and 3.3V tolerance

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

nQCLK_D3

Output

Differential clock output D3 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKD

D1

nQCLK_D4

Output

Differential clock output D4 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKD

E10

E9

V

Power

Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_A[3:0] outputs.

Positive supply voltage (3.3V) for Channel A.

DDO_QCLKA

V

DD_QCLKA

E8

GND

Power

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Device clock 0 inverting and non-inverting differential clock input. Inverting input is

E7

nCLK_0

nCLK_1

Input (PD/ PU)

biased to V

/2 by default when left floating. Compatible with LVPECL, LVDS and

DD_V

LVCMOS signals.

E6

Input (PD/ PU)

Device clock 1 inverting and non-inverting differential clock input. Inverting input is

biased to V

/2 by default when left floating. Compatible with LVPECL, LVDS and

DD_V

LVCMOS signals.

E5

E4

E3

E2

E1

F10

F9

ADR2

SCL

Input (PD/ PU)

Input (PU)

Power

Control input for output Bank D. 3-level signal (see Table 12 and Table 14).

2

I C clock input. 1.8V interface levels with hysteresis and 3.3V tolerance.

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

nQCLK_D5

QCLK_D5

GND

Output

Differential clock output D5 (Channel D). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKD

Output

Power

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

GND

Power

F8

GND

Power

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May 15, 2018

8V19N478 Datasheet

Table 1. Pin Descriptions (Cont.)^[a]

[b]

Ball

Name

Type

Description

F7

F6

F5

F4

GND

Power

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Control input for output Bank B. 3-level signal (see Table 12 and Table 14).

Power

ADR1

ADR0

Input (PD/ PU)

Control input for output Bank A and Bank C. Three-level signal (see Table 12 and

Table 14).

F3

F2

GND

Power

Output

Power

Output

Power

Analog

Power

Output

Power

Analog

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Positive supply voltage (3.3V) for Channel D.

V

DD_QCLKD

F1

V

Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_D[5:0] outputs.

DDO_QCLKD

G10

G9

G8

G7

G6

G5

G4

G3

G2

G1

H10

H9

H8

H7

H6

H5

H4

H3

H2

H1

J10

J9

nQCLK_B0

QCLK_B0

Differential clock output B0 (Channel B). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKB

V

Positive supply voltage (3.3V) for Channel B.

DD_QCLKB

V

Positive supply voltage (3.3V) for internal FemtoClock NG circuits.

DD_CPF

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Positive supply voltage (3.3V) for Channel C.

GND

V

DD_QCLKC

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

GND

nQCLK_B1

QCLK_B1

Differential clock output B1 (Channel B). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKB

V

Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_B[3:0] outputs.

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Analog internal LDO bypass for VCO. Connect a 10µF capacitor to GND.

Internal bias circuit for VCO. Connect a 4.7µF capacitor to GND.

DDO_QCLKB

GND

CLDO

CBIAS

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_C[3:0] outputs.

V

DDO_QCLKC

QCLK_C0

nQCLK_C0

nQCLK_B2

QCLK_B2

GND

Differential clock output C0 (Channel C). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKC

Differential clock output B2 (Channel B). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKB

J8

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

Internal VCO regulator bypass capacitor. Use a 4.7µF capacitor between the CR and

J7

GND

J6

CR

the V

terminals.

DD_LCF

J5

J4

V

Power

Positive supply voltage (3.3V) for the VCXO-PLL.

DD_LCV

GND

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

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May 15, 2018

8V19N478 Datasheet

Table 1. Pin Descriptions (Cont.)^[a]

[b]

Ball

Name

Type

Description

Differential clock output C3 (Channel C). Configurable LVPECL, LVDS style and

J3

nQCLK_C3

Output

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKC

J2

J1

QCLK_C1

nQCLK_C1

nQCLK_B3

QCLK_B3

GND

Output

Power

Output

Differential clock output C1 (Channel C). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKC

K10

K9

K8

K7

Differential clock output B3 (Channel B). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKB

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

LFF

Loop filter/charge-pump output for the FemtoClock NG PLL. Connect to the external

loop filter.

K6

K5

LFFR

Analog

Power

Ground return path pin for the VCO loop filter.

V

Positive supply voltage (3.3V) for the internal oscillator of the FemtoClock NG PLL.

For essential information on power supply filtering, see Power Supply Filtering.

DD_LCF

K4

K3

GND

Power

Output

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

nQCLK_C3

Differential clock output C3 (Channel C). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V

supply voltage.

DDO_QCLKC

K2

K1

QCLK_C2

Output

Differential clock output C2 (Channel C). Configurable LVPECL, LVDS style and

amplitude. Output levels are determined by the V supply voltage.

DDO_QCLKC

nQCLK_C2

[a] For essential information on power supply filtering, see Power Supply Filtering.

[b] Pull-up (PU) and pull-down (PD) internal input resistors are indicated in parentheses. For typical values, see Input Characteristics, Table 41.

Principles of Operation

Overview

The device generates low-phase noise, synchronized clock output signals locked to an input reference frequency. The device contains

two PLLs with configurable frequency dividers. The first PLL (VCXO-PLL, suffix V) uses an external VCXO as the oscillator and provides

jitter attenuation. The external loop filter is used to set the VCXO-PLL bandwidth frequency in conjunction with internal parameters. The

second, low-phase noise PLL (FemtoClock NG, suffix F) multiplies the VCXO-PLL frequency to the VCO frequency of 2500MHz. The

FemtoClock NG PLL is completely internal and provides a central reference timing reference point for all output signals. From this point,

fully synchronous dividers generate the output frequencies.

The device has four output channels A – D, four channels with one integer output divider A – C and one channel with a fractional output

divider (D). The clock outputs are configurable with support for LVPECL and LVDS formats, and a variable output amplitude. In channels

A – D, the clock phase can be adjusted in phase. Individual outputs, channels, and unused circuit blocks support powered-down states

for operation at reduced power consumption. The register map, accessible through a selectable I²C interface with read-back capability

controls the main device settings and delivers device status information. For redundancy purpose, there are two selectable reference

frequency inputs and a configurable switch logic with manual, auto-selection, and holdover support.

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8V19N478 Datasheet

Phase-Locked Loop Operation

Frequency Generation

The 8V19N478 supports four operation modes: Dual-PLL and VCXO-PLL with jitter attenuation, frequency synthesis, and the buffer/

divider mode. Frequencies higher than the input frequency can be generated by the device by utilizing one or both PLLs. Using the

PLL(s) require(s) the user to set the frequency dividers to match input, VCXO and VCO frequency and to achieve frequency and phase

lock on the used PLLs. The frequency of the external VCXO is chosen by the user. The internal VCO frequency range is 2400–2500MHz.

Available frequency dividers for each of the four modes are displayed in Table 2. Example divider configurations are shown in Table 3 and

Table 4.

Dual-PLL Jitter Attenuation Mode: Input clock jitter is attenuated by the VCXO-PLL (1st stage PLL). The 2nd stage PLL (FemtoClock NG)

is locked to the 1st stage PLL and synthesizes a frequency in the range of 2400–2500MHz. Output dividers scale the frequency down to

the target frequency. Dividers P_V, M_V, P_F, M_F, N_x, and (optionally) N_Drequire a user configuration. This is the main operation mode of the

device with the highest flexibility in frequency generation. Best phase noise is achieved with internal frequency doubler turned on.

VCXO-PLL Jitter Attenuation Mode: Input clock jitter is attenuated by the VCXO-PLL (1st stage PLL). The VCXO-output signal is divided

by the output dividers to the target frequency. Dividers P_V, M_V, and N_xrequire a user configuration. The VCXO sets the highest frequency

the device can achieve. The output phase noise is equivalent to the phase noise of the VCXO scaled by the output divider.

Frequency Synthesis Mode: The 1st stage PLL is bypassed. The 2nd stage PLL (FemtoClock NG) is directly locked to the input source

and synthesizes a frequency in the range of 2400–2500MHz. output dividers scale the frequency down to the target frequency. Dividers

P_V, P_F, M_F, N_x, and (optionally) N_Drequire a user configuration. This mode is recommend for applications with a low-jitter input source.

Divider/Buffer Mode: Both PLLs are bypassed. Output dividers scale the input frequency to the target frequency. Dividers P_Vand N_x

require a user configuration. In this mode, the PLL frequency specifications do not apply.

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May 15, 2018

8V19N478 Datasheet

Table 2. PLL Divider Values

Operation

Frequency

Synthesis

Jitter Attenuation

VCXO-PLL

Divider/Buffer

Dual-PLL

(BYPV  0, SRC  0)

(BYPV  0,

SRC  1)

VCXO-PLL bypassed Both PLLs bypassed

(BYPV  1, SRC  0) (BYPV  1, SRC  1)

Divider

Range

VCXO-PLL

1…32767:

Input clock frequency

[a]

Pre-Divider P

(15 bit)

V

f_VCXO

-------------------

M_V

No external VCXO required

f_CLK

=

 P_V

VCXO-PLL

Feedback Divider

1…32767:

(15 bit)

M

V

FemtoClock NG

Pre-Divider P

1…63: (6 bit)

Input clock

frequency:

VCXO frequency:

F

P_F

---------

FemtoClock NG

Feedback

8 …511: (9 bit)

P_F

f_VCXO= f_VCO

---------

f_CLK= f_VCO

M_F

—

Output frequency

Dividers M

F

[b]

f

: Note

f_CLK

VCO

[b]

f_OUT

=

-------------------------

f

: Note

[c]

VCO

P : Note

N_X P_V

F

[c]

P : Note

F

Output Divider Nx 1…160:

Output frequency

[d]

(x  [A:C])

(Integer)

f_VCO

f_VCXO

f_VCO

f_OUT

=

f_OUT

=

f_OUT

=

--------------

-------------------

--------------

N_X

Output Divider ND Fractional

Output frequency

[e]

Divider :

f_VCO

4

f_OUT

=

--------------

N

: 4…2 – 1:

INT

N_E

(Integer part)

24

—

N

: 1…2 – 1:

FRAC

N_FRAC

---------------------

₂24

(Fractional part)







N_E= 2  N_INT

+



[a] P_Vdivider settings are in the PV0 register (for CLK_0), and in the PV1 register (for CLK_1). The PV divider is automatically loaded from PV0 or

PV1 according to the input selection (Clock Selection Settings, Table 11).

[b] f_VCO 2400–2500MHz.

[c] Set P_Fto 0.5 in the equation if the frequency doubler is engaged (FDF  1).

[d] For a list of supported integer output dividers Nx (Table 8).

[e] Greatest ND fractional divider is 2  (14  [2²⁴– 1] / 2²⁴) ≈ 29.99999988.

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May 15, 2018

8V19N478 Datasheet

VCXO-PLL

The prescaler P_Vand the VCXO-PLLs feedback divider M_Vrequire configuration to match the input frequency to the VCXO-frequency.

With the M_Vand P_Vdivider value range of 15 bit, the device support is very flexible and supports a wide range of input and VCXO-

frequencies.

In addition, the range of available inputs and feedback dividers allow to adjust the phase detector frequency independent of the used

input and VCXO frequencies (Table 3 and Table 4). The VCXO-PLL charge-pump current is controllable via internal registers, and can be

set in 50µA steps, from 50µA to 1.6mA. The VCXO-PLL can be bypassed (BYPV): when in bypass, the FemtoClock NG PLL locks to the

pre-divided input frequency.

Table 3. Example Configurations for f_VCXO 125MHz

VCXO-PLL Divider Settings

Input Frequency (MHz)

PV

MV

f

(MHz)

PFD

19.44

486

1

3125

5

0.04

20

5

4

20

80

320

1

25

16

64

1

1.25

0.390625

125

5

25

125

25

125

5

25

125

4

5

1

31.25

3.125

0.3125

156.25

50

500

40

400

Table 4. Example Configurations for f_VCXO 156.25MHz

VCXO- PLL Divider Settings

Input Frequency (MHz)

PV

MV

f

(MHz)

PFD

19.44

20

1944

400

4

15625

3125

25

0.01

0.05

6.25

25

125

40

250

2500

5

0.625

0.0625

31.25

3.125

0.3125

156.25

15.625

1.5625

400

4

40

50

400

1

500

1

156.25

10

100

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May 15, 2018

8V19N478 Datasheet

Table 5. VCXO-PLL Bypass Settings

BYPV

Operation

0

1

VCXO-PLL operation.

VCXO-PLL bypassed and disabled. The reference clock for the FemtoClock NG PLL is the selected input

clock. The input clock selection must be set to manual by the user. Clock switching and holdover are not

defined. The device synthesizes an output frequency, but will not attenuate input jitter. An external VCXO

component and loop filter is not required.

FemtoClock NG PLL

The FemtoClock NG PLL is the second stage PLL, and locks to the output signal of the VCXO-PLL (BYPV  0). It requires configuration from

the frequency doubler FDF, or the pre-divider PF and the feedback divider MF to match the VCXO-PLL frequency to the VCO frequency of

2500MHz. Best phase noise is typically achieved by engaging the internal frequency doubler (FDF  1, 2). If engaged, the signal from the first

PLL stage is doubled in frequency, increasing the phase detector frequency of the FemtoClock NG PLL. When the frequency doubler is

enabled, the frequency pre-divider PF is disabled. If the frequency doubler is not used (FDF  0), the PF pre-divider has to be configured.

Typically, the PF is set to 1 to keep the phase detector frequency as high as possible. Set the PF to other divider values to achieve specific

frequency ratios between the first and second PLL stage. This PLL is internally configured to high-bandwidth.

Table 6. Frequency Doubler

FDF

Operation

0

1

Frequency doubler off. The PF divides the clock signal from the VCXO-PLL or input (in bypass).

Frequency doubler on (2). A signal from the VCXO-PLL or input (in bypass) is doubled in frequency. The

PF divider has no effect.

Table 7. Example PLL Configurations

FemtoClock NG Divider Settings for VCO  2500MHz

VCXO-Frequency (MHz)

FDF

PF

MF

25

2

–

1

–

1

50

10

20

8

125

2

–

156.25

16

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May 15, 2018

8V19N478 Datasheet

Channel Frequency Divider

The device supports four independent output channels A–D. The channels A–C have one configurable integer frequency divider Nx

(x  A – C), that divides the VCO frequency to the desired output frequency with very low phase noise. The integer divider values can be

selected from the range of 1 to 160 (Table 8). Channel D supports fractional divider ratios (Table 9).

Table 8. Integer Frequency Divider Settings

[a]

Channel Divider Nx

Output Clock Frequency (MHz) for VCO  2500MHz

1

2

2500

1250

3

833.333

625

4

5

500

8

312.5

250

10

16

20

30

32

40

50

60

64

80

100

120

128

160

156.25

125

83.333

78.125

62.5

50

41.667

39.0625

31.25

25

20.833

19.53125

15.625

[a] x  A – D.

Table 9. Typical Fractional Frequency Divider Settings

[a]

Channel Divider ND

Output Clock Frequency (MHz) for VCO 2500MHz

15.51

161.1328125

133.333

18.75

[a] Greatest ND fractional divider is 2  (14  [2²⁴– 1] / 2²⁴) ≈ 29.99999988.

Table 10. PLL Feedback Path Settings

SRC

Operation

0

1

The output divider input signal is the FemtoClock NG PLL.

The output divider input signal is the VCXO-PLL output signal. FemtoClock NG PLL is bypassed.

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May 15, 2018

8V19N478 Datasheet

Redundant Inputs

The two inputs are compatible with LVDS and LVPECL signal formats, and also support single-ended LVCMOS signals. For applicable

input interface circuits, see Applications Information.

Definitions

▪ Primary clock – The CLK_n input selected by the selection logic.

▪ Secondary clock – The CLK_n input not selected by the selection logic.

▪ PLL reference clock – The CLK_n input selected as the PLL reference signal by the selection logic. In automatic switching mode, the

selection can be overwritten by a state machine.

Monitoring

Loss of Input Signal (LOS)

In operation, a clock input is declared invalid (LOS) with the corresponding ST_CLK_n and LS_CLK_n indicator bits set after a specified

number of consecutive clock edges. If differential input signals are applied, the input will also detect an LOS condition in case of a zero

differential input voltage.

The device supports LOS detect circuits, one for each input. The signal detect circuits compare the signals at the CLK_0 and CLK_1

inputs to the internal frequency-divided signals from the VCXO-PLL (Figure 2). The loss-of-signal fault condition is declared upon three or

more missing clock input edges. LOS requires configuration of the N_MON[4:0] frequency divider setting to individually match the input

frequencies CLK_n to the VCXO frequency: f_VCXO N_MON[4:0]  f_{CLK_n}. For instance, if one of the input frequencies is 25MHz and a

125MHz VCXO is used, set N_MON[4:0]  5. For configuration details see Table 11. Then, LOS is declared after three consecutive

missing clock edges. LOS is signaled through the ST_CLK_n (momentary) and LS_CLK_n (sticky, resettable) status bits. and can be

reported as an interrupt signal on the nINT output. The LOS circuit requires the jitter attenuation mode of the device (BYPV  0). LOS

does not detect frequency errors.

Figure 2. LOS Detect Circuit

f_{CLK_0}

CLK_0

nCLK_0

f_{CLK_1}

÷P_V

CLK_1

nCLK_1

Input Select

LOS

Detector 0

ST_CLK_0, LS_CLK_0

N_MON[4:0]

÷1, ÷2, ..., ÷40

f_VCXO

LOS

Detector 1

ST_CLK_1, LS_CLK_1

VCXO

Input Re-Validation

A clock input is declared valid and the corresponding LOS bit is reset after the clock input signal returned for user-configurable number of

consecutive input periods. This re-validation of the selected input clock is controlled by the CNTV setting (verification pulse counter).

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8V19N478 Datasheet

Clock Selection

The device supports five input selection modes: manual with and without holdover, short-term holdover, and two automatic switch modes.

Table 11. Clock Selection Settings

Mode

Flags

Name

Description

Application

Input selection follows user-configuration of the EXT_SEL pin or INT_SEL register bit as set by nEXT_INT with

holdover. Input selection is never changed by the internal state machine.

LOS on the primary reference clock:

Selected

Active reference stays selected, and the PLLs

may stall. The device will not go into holdover.

1

0^[a]

input

Manual

Holdover

Control

Manual change of the reference clock:

The device will go into holdover, and the

hold-off down-counter (CNTH) starts. The

device initiates a clock switch after expiration

of the hold-off counter. Duration of holdover is

set by CNTH  CNTR / f_VCXO. Holdover is

terminated even if the secondary clock input is

bad (LOS), (Manual Holdover Control

(nHO_EN = 0).

Startup and

external

selection

control with

holdover

0

X

LOS

status

(default)

LOS status

of selected

input

Selected

input^[c]

0^[b]

Input selection follows user-configuration of the EXT_SEL pin or INT_SEL register bit as set by nEXT_INT.

Input selection is never changed by the internal state machine.

LOS on the primary reference clock:

Selected

Active reference stays selected and the PLLs

may stall. Device will not go into holdover.

1

0

Manual

Control

input

1

0

External

selection

control

LOS

status

Manual change of the reference clock:

The device will not go into holdover and will

attempt to lock to the newly selected

reference.

Actual LOS

status of

selected

input

Selected

input

1

Input selection follows LOS status. A failing input clock will cause an LOS event for that clock input. If the

selected clock has an LOS event, the device will immediately initiate a clock fail-over switch.

LOS on the primary reference clock:

The device will switch to the secondary clock

without holdover. Input selection is

determined by a state machine and may differ

from the user’s clock selection.

Actual LOS

status of

selected

input

determined

by state

machine

Selected

input

determined

by state

machine

No valid clock scenario: If no valid input

1

Multiple

inputs with

qualified

clock

1

0

1

Automatic clocks exist, the device will not attempt to

switch, and will not enter the holdover state.

The PLL is not locked. Re-validation of all

LOS

status

input clocks will result in the PLL to attempt to

lock on that input clock (Revertive Switching).

signals

Manual change of the reference clock:

The device will switch to the newly selected

clock without holdover. If the newly selected

clock is not valid, the PLL may stall.

Actual LOS

status of

selected

input

Selected

input

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8V19N478 Datasheet

Table 11. Clock Selection Settings (Cont.)

Mode

Flags

Name

Description

Application

Input selection follows user-configuration of EXT_SEL pin or INT_SEL register bit as set by nEXT_INT.

Selection is never changed by the internal state machine (see Holdover).

LOS on the primary reference clock:

A failing reference clock will cause an LOS

0

Use if a

single

reference is

occasionally

interrupted

Short-term

Holdover

event. If the selected reference fails, the

device will enter holdover immediately.

Re-validation of the selected input clock is

controlled by the CNTV setting. A successful

re-validation will result in the PLL to re-lock on

that input clock.

LOS status

for duration

of LOS until

revalidation

1

0

LOS

status

Selected

input

For

holdover

duration

Input selection follows LOS status. A failing input clock will cause an LOS event for that clock input. If the

selected clock has an LOS event, the device will go into holdover and switches input clocks after the hold-off

counter expires.

LOS on the primary reference clock, or

Manual change of the reference clock:

The device will go into holdover and the

hold-off down-counter (CNTH) starts. The

device initiates a clock fail-over switch to a

valid secondary clock input after expiration of

the hold-off counter. Duration of holdover is

set by CNTH CNTR/ f_VCXO. The holdover is

terminated prior hold-off count-down if the

primary clock revalidates or is terminated by a

manual change of the reference clock. See

Automatic with Holdover (nHO_EN = 1,

Automatic

with

Holdover

0

Selected

input

1

Actual LOS

status of

selected

input

LOS

status

Multiple

inputs

determined

by state

machine

For

holdover

duration

nM/A[1:0] = 11), and Revertive Switching.

No valid clock scenario: The device remains

in holdover if the secondary input clock is

invalid.

[a] For the duration of an invalid input signal (LOS).

[b] For the duration of holdover.

[c] Delayed by holdover period.

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8V19N478 Datasheet

Holdover

In holdover state, the output frequency and phase is derived from an internal, digital value based on previous frequency and phase

information. Holdover characteristics are defined in Table 48.

Manual Holdover Control (nHO_EN  0)

This is the default switching mode of the device. The switch control is manual: The EXT_SEL pin or the INT_SEL bit as set by nEXT_INT

determines the selected reference clock input. If the selection is changed by the user, the device will enter holdover until the CNTH[7:0]

counter expires. Then, the new reference is selected (input switch). Application for this mode is startup and external selection control.

▪ ST_REF – Status of selected reference clock

▪ ST_CLK_n – Both will reflect the status of the corresponding input

▪ ST_SEL – The new selection

▪ nST_HOLD  0 for the duration of holdover

Automatic w ith Holdover (nHO_EN  1, nM/A[1:0]  11)

If an LOS event is detected on the active reference clock:

1. Holdover begins immediately

2. Corresponding ST_REF and LS_REF go low immediately

3. Hold-off countdown begins immediately

During this time, both input clocks continue to be monitored and their respective ST_CLK, LS_CLK flags are active. LOS events will be

indicated on ST_CLK, LS_CLK when they occur.

If the active reference clock resumes and is validated during the hold-off countdown:

1. Its ST_CLK status flag will return high and the LS_CLK is available to be cleared by an I²C write of 1 to that register bit

2. No transitions will occur of the active REF clock; ST_SEL does not change

3. Revertive bit has no effect during this time (whether 0 or 1)

When the hold-off countdown reaches zero:

If the active reference has resumed and has been validated during the countdown, it will maintain being the active reference clock:

1. ST_SEL does not change

2. ST_REF returns to 1

3. LS_REF can be cleared by an I²C write of 1 to that register

4. Holdover turns off and the VCXO-PLL attempts to lock to the active reference clock

If the active reference has not resumed, but the other clock input CLK_n is validated, then:

1. ST_SEL1:0 changes to the new active reference

2. ST_REF returns to 1

3. LS_REF can be cleared by an I²C write of 1 to that register

4. Holdover turns off

If there is no validated CLK:

1. ST_SEL does not change

2. ST_REF remains low

3. LS_REF cannot be cleared by an I²C write of 1 to that register

4. Holdover remains active

Revertive capability returns if REVS  1.

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8V19N478 Datasheet

Hold-off Counter

A configurable down-counter applicable to the Automatic with Holdover and Manual with Holdover selection modes. The purpose of this

counter is a deferred, user-configurable input switch. The counter expires when a zero-transition occurs; this triggers a new reference

clock selection. The counter is clocked by the frequency-divided VCXO-PLL signal. The CNTR setting determines the hold-off counter

frequency divider and the CNTH setting the start value of the hold-off counter. For instance, set CNTR to a value of 131072 to achieve

953.67Hz (or a period of 1.048ms at f_VCXO125MHz): the 8-bit CNTH counter is clocked by 953.67Hz and the user-configurable hold-off

period range is:

0ms (CNTR  0x00) to 267ms (CNTR  0xFF). After the counter expires, it reloads automatically from the CNTH I²C register. After the

LOS status bit (LS_CLK_n) for the corresponding input CLK_n has been cleared by the user, the input is enabled for generating a new

LOS event.

The CNTR counter is only clocked if the device is configured in the clock selection modes, Automatic with Holdover and the selected

reference clock experiences an LOS event, or in the Manual with Holdover mode with manual switching. Otherwise, the counter is

automatically disabled (not clocked).

Revertive Switching

Revertive switching is only applicable to the two automatic switch modes shown in Table 11. Revertive switching enabled: Re-validation

of any non-selected input clock(s) will cause a new input selection according to the user-preset input priorities (revertive switch). An input

switch is only done if the re-validated input has a higher priority than the currently selected reference clock. Revertive switching disabled:

Re-validation of a non-selected input clock has no impact on the clock selection. The default setting is revertive switching disabled.

VCXO-PLL Lock Detect (LOLV)

The VCXO-PLL lock detect circuit uses the signal phase difference at the phase detector as Loss-of-lock criteria. Loss-of-lock is reported

if the actual phase difference is larger than a configurable phase detector window set by the LOCK_TH[14:0] configuration bits. A

Loss-of-lock state is reported through the nST_LOLV and nLS_LOLV status bits (Table 21). The VCXO-PLL lock detect function requires

to set FVCV  0.

Table 12. ADR3 Selection Table

ADR3

Device Mode

Low

Default modes:

Outputs – disabled

Inputs – unused

Middle

High

Default frequency profile with 25MHz input

Default frequency profile with 20MHz input

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8V19N478 Datasheet

Table 13. Input Path Pin Configuration Table

SEL_BITS_MASTER(REG20,

D0)

X

L

X

0

M

0

1

X

ADR3

REFin

H

REF = 25MHZ

REF = 20MHZ

PV Divide

REG16[7:0], 17[6:0]

REF/ PV

160

156.25kHz

1000

156.25kHz

128

160

125kHz

1250

125kHz

128

REG16[7:0], 17[6:0]

REF/ PV

REF into PD

MV Divide

FB into PD

lock_th

REG18[7:0], 19[6:0]

FB/ MV

REG18[7:0], 19[6:0]

FB/ MV

REG21[7:0], 22[6:0]

REG25[5:0]

REG25[7]

0

REG21[7:0], 22[6:0]

REG25[5:0]

REG25[7]

0

PF

X

PF Doubler

REF into PD

MF

on

312.5MHz

8

312.5MHz

8

REG26[7:0], 27[0]

0

REG26[7:0], 27[0]

0

FB into PD

BYPV

312.5MHz

off

312.5MHz

off

REG23[0]

REG24[0]

REG28[7]

REG28[6]

REG28[4:0]

REG30[4:0]

REG32[7:3]

0

REG23[0]

REG24[0]

REG28[7]

REG28[6]

REG28[4:0]

REG30[4:0]

REG32[7:3]

0

SRC

on

Polarity

positive

off

positive

off

FVCV

CPV

750µA

5.8mA

8

750µA

5.8mA

8

CPF

N_MON

LOS Monitoring Frequency

MODE_BLOCK

nHO_EN

nEXT_INT

nMA[1:0]

CNTV

19.5MHz

on

19.5MHz

on

REG32[2]

REG32[1]

REG32[0]

REG33[3:2]

REG35[1:0]

REG32[2]

REG32[1]

REG32[0]

REG33[3:2]

REG35[1:0]

off

external

manual

2

external

manual

2

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8V19N478 Datasheet

Table 14. Output Frequency Pin Configuration Table

Output Bank A and C

ADR0

Output Type

Divide Ratio

FOUT (MHz)

Swing Level

Low

Middle

High

LVPECL

LVDS

20

16

125

750mV

500mV

750mV

Total outputs per

bank: 4, with 1 integer

divider

156.25

LVPECL

Output Bank B

ADR1

Output Type

Divide Ratio

FOUT (MHz)

Swing Level

Low

Middle

High

LVPECL

LVDS

20

16

125

750mV

500mV

750mV

Total of 4 outputs with

1 integer divider

156.25

LVPECL

Output Bank D

ADR2

Output Type

Divide Ratio

FOUT (MHz)

Swing Level

Total of 6 outputs with

1 fractional divider

Low

Middle

High

LVPECL

LVDS

20

16

125

750mV

500mV

750mV

156.25

LVPECL

Table 15. I²C Address Selection Table

I2C_A

Output Type

I2C_A[1]

I2C_A[0]

Low

Middle

High

Address 1

Address 2

Address 3

0

1

0

1

The 8V19N478 can be configured via pin or I2C. ADR3/2/1/0 provides a specific set of configuration options for input and output paths. In

addition, the initialization sequence of the device is controlled by the ADR3 pin and the synchronization of the outputs by transition from

Low to Middle or High.

Table 16. Initialization Sequence Control

Initialization

In Pin Mode, Triggered by:

init_clk

pb_cal

relock

OE

(Pin I2C_A3 = M or H) + IBM die powered up

Completion of init_clk sequence (above)

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8V19N478 Datasheet

The pin configuration is overridden by I2C programming of the register map. The I2C_A pin set the Address as shown in following table.

Table 17. I2C Address

1

I2C_A1

I2C_A0

R

W

I2C_A

D8, D9

DA, DB

DE, DF

1101

1

0

1

0

1

0

L

M

H

Address 1

Address 2

Address 3

The default values of the register map are Read back by the I²C in the Pin-Strap configuration mode.

FemtoClock NG Loss-of-lock (LOLF)

FemtoClock NG-PLL loss-of-lock is signaled through the nST_LOLF (momentary), and nLS_LOLF (sticky, resettable) status bits, and can

reported as hardware signal on the LOCK_V output as well as an interrupt signal on the nINT output.

Differential Outputs

Table 18. Output Features

[a]

Output

Style

Amplitude

Disable

Power Down

Termination

[b]

LVPECL

LVDS

50 to V_TT

350 – 850mV

4 steps

QCLK_y

Yes

100 differential

—

50 to V_TT

100 differential

—

LVPECL

LVDS

LVCMOS^[c]

350 – 850mV

4 steps

Yes

QCLK_V

1.8V

[a] Amplitudes are measured single-ended.

[b] For V_TT(Termination voltage) values (see Table 50).

[c] LVCMOS style: nQCLK_V and QCLK_V are complementary.

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8V19N478 Datasheet

Table 19. Individual Clock Output Settings

[b]

Output Power

Termination

State

Amplitude (mV)

1

0

Off

On

X

0

100 differential or no termination

100 differential (LVDS)

X

0

1

Off

Disable^[c]

X

XX

00

01

10

11

XX

00

01

10

11

X

Enable

350

500

700

850

X

1

50 to V_TT^[d](LVPECL)

0

1

Disable

Enable

350

500

700

850

[a] Power-down modes are available for the individual channels A – D and the outputs QCLK_y (A0 – D3).

[b] Output amplitudes of 700mV and 850mV require a 3.3V output supply (V_{DDO_V}). 350mV and 500mV output amplitudes support

_{DDO_V} 2.5V and 1.8V.

V

[c] Differential output is disabled in static low/high state.

[d] For V_TT(Termination voltage) values, see Table 50.

Output Phase-Delay

Output phase delay is supported in each channel. The selected VCO frequency sets the delay unit to 1/f_VCO

.

Table 20. Delay Circuit Settings

Delay Circuit

Unit

Steps

Range

1

--------------

f_VCO

Clock Phase 

256

0–102ns

CLK_x

f_VCO 2500MHz:

400ps

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8V19N478 Datasheet

Status Conditions and Interrupts

The 8V19N478 has an interrupt output to signal changes in status conditions. Settings for status conditions may be accessed in the

Status registers. The device has several conditions that can indicate faults and status changes in the operation of the device. These are

shown in Table 21 and can be monitored directly in the status registers. Status bits (named: ST_condition) are read-only and reflect the

momentary device status at the time of read-access. Several status bits are also copied into latched bit positions (named: LS_condition).

The latched version is controlled by the corresponding fault and status conditions and remains set (“sticky”) until reset by the user by

writing “1” to the status register bit. The reset of the status condition has only an effect if the corresponding fault condition is removed,

otherwise, the status bit will set again. Setting a status bit on several latched registers can be programmed to generate an interrupt signal

(nINT) via settings in the Interrupt Enable bits (named: IE_condition). A setting of “0” in any of these bits will mask the corresponding

latched status bits from affecting the interrupt status pin. Setting all IE bits to 0 has the effect of disabling interrupts from the device.

Table 21. Status Bit Functions

Status Bit

Function

Status if Bit is:

Interrupt

Enable Bit

Momentary

Latched

Description

CLK 0 input status

1

0

ST_CLK_0

ST_CLK_1

nST_LOLV

nST_LOLF

nST_HOLD

ST_VCOF

ST_SEL

LS_CLK_0

LS_CLK_1

nLS_LOLV

nLS_LOLF

nLS_HOLD

—

Active

LOS

IE_CLK_0

IE_CLK_1

IE_LOLV

IE_LOLF

IE_HOLD

—

CLK 1 input status

VCXO-PLL loss of lock

FemtoClock NG-PLL loss of lock

Holdover

Locked

Loss-of-lock

Locked

Not in holdover

Not completed

Device in holdover

Completed

FemtoClock NG VCO calibration

Clock input selection

—

0  CLK_0

1  CLK_1

Valid reference^[a]

Reference lost

—

ST_REF

LS_REF

PLL reference status

IE_REF

[a] Manual and short-term holdover mode: 0 indicates if the selected reference is lost, 1 if not lost.

Automatic mode: will transition to 0 while the input clock is lost and during input selection by priority.

Will transition to 1 once a new reference is selected.

Automatic with holdover mode: 0 indicates the reference is lost and still in holdover.

Interrupts are cleared by resetting the appropriate bit(s) in the latched register after the underlying fault condition has been resolved.

When all valid interrupt sources have been cleared in this manner, this will release the nINT output until the next unmasked fault.

Table 22. LOCK Function

Status Bit (PLL)

[a]

[b]

nLS_LOLV (VCXO-PLL)

nLS_LOLF (FemtoClock NG)

Status Reported on LOCK Output

Locked

Not locked

Locked

1

0

Not locked

[a] Hardware interrupts on nINT required to set the IE_LOLV, IE_LOLF bits to “enable interrupt”.

[b] SELSV1 controls the logic level 1.8V/3.3V of LOCK and nINT outputs.

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May 15, 2018

8V19N478 Datasheet

Serial Control Port

Serial Control Port Configuration Description

The 8V19N478 has a serial control port that can respond as a slave in an I²C compatible configuration at a base address of

11011[I2C_A1, I2C_A0]b, to allow access to any of the internal registers for device programming or examination of internal status. The

I2C_A[1:0] bits of the I²C interface address are set by the logic state of the three-level pin, I2C_A (see Table 17). If more than one

8V19N478 is connected to the same I²C bus, set I2C_A to a different state on each device to avoid address conflicts.

All registers are configured to have default values. For details, see the specifics for each register. Default values for registers are set after

reset by the configuration pins.

I²C Mode Operation

The I²C interface fully supports v1.2 of the I²C Specification for Normal and Fast mode operation. The interface acts as a slave device on

the I²C bus at 100kHz or 400kHz using a fixed base address of 11011[I2C_A1, I2C_A0]b.

The I²C interface accepts byte-oriented block write and block read operations (see Figure 3 and Figure 4). One address byte specifies

the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from

the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer.

During a write operation, data is moved into the registers byte by byte and before a STOP bit is received.

For full electrical I²C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors

have a size of 51k typical.

Figure 3. I²C Write Data (Master Transmit, Slave Receive) From Any Register Address

1 1 0 1 1 I2C_A1 I2C_A0

Slav e Device Address

0

nW

A7 to A0

Register Address

D7 to D0

(Register Address)

D7 to D0

(Register Address+1)

D7 to D0

(Register Address+n)

S

A

...

A

P

SDA

Write to slave to the specified register address A[7:0]. The slave auto-increments the register address and data is written sequentially.

S

Start (Master)

P

Stop (Master)

A

Acknowledge (Slave to Master)

Master transmit, Slave Receive

Slave transmit, Master Receive

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8V19N478 Datasheet

Figure 4. I²C Read Data (Slave Transmit, Master Receive) From Any Register Address

1 1 0 1 1 I2C_A1 I2C_A0

Sl av e Devic e Address

0

nW

A7 to A0

Register Address

1 1 0 1 1 ADR1 ADR0

Sl av e Devic e Address

1

R

D7 to D0

(Register Address)

D7 to D0

(Register Address+n)

S

A

Sr

A

...

A

P

SDA

Read from slave from the specified register address A[7:0]. Data is transmitted to the master after a change of the transfer direction with a repeated start. The

slave auto-increments the register address and transmits register data to the master sequentially.

S

P

A

Sr

Start (Master)

Repeated start (Master)

Stop (Master)

Acknowledge (Slave to Master)

Acknowledge (Master to Slave)

Not Acknowledge (Master to Slave)

Master transmit, Slave Receive

Slave transmit, Master Receive

Register Descriptions

This section contains all addressable registers, sorted by function, followed by a detailed description of each bit field for each register.

Several functional blocks with multiple instances in this device have individual registers controlling their settings, but since the registers

have an identical format and bit meaning, they are described only once, with an additional table to indicate their addresses and default

values. All writable register fields will come up with a default values as indicated in the Factory Defaults column unless altered by values

loaded from non-volatile storage during the initialization sequence.

Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of

the conditions they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are

Reserved. Reserved bit fields may be used for an internal debug test and debug functions.

Table 23. Configuration Registers

Register Address

Register Description

0x00

0x01

SRESET

I²C Address (I²C only)

Reserved

0x02–0x0F

0x10–0x11

0x12–0x13

0x14

PLL Frequency Divider: PV

PLL Frequency Divider: MV

SEL_BITS_MASTER

LOCK_TH

0x15–0x16

0x17

PLL Control: BYPV

0x18

PLL Control: SRC

0x19

PLL Frequency Divider: PF, FDF

PLL Frequency Divider: MF[7:0]

PLL Frequency Divider: MF[8]

PLL Control

0x1A

0x1B

0x1C–0x1E

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May 15, 2018

8V19N478 Datasheet

Table 23. Configuration Registers (Cont.)

Register Address

Register Description

0x1F

0x20–0x23

0x24–0x26

0x27

I/O Voltage Select

Input Selection

Channel A

Reserved

0x28–0x2B

0x2C–0x2E

0x2F

Output States QCLK_A0 – QCLK_A3

Channel B

Reserved

0x30–0x33

0x34–0x36

0x37

Output States QCLK_B0 – QCLK_B3

Channel C

Reserved

0x38–0x3B

0x3C–0x42

0x43

Output States QCLK_C0 – QCLK_C3

Channel D

Reserved

0x44–0x49

0x4A

Output States QCLK_D0 – QCLK_D5

Reserved

0x4B

QCLKV

0x4C

Interrupt Enable

Reserved

0x4D

0x4E–0x4F

0x50

Reserved

Status (Latched)

Status (Momentary)

Reserved

0x51

0x52

0x53

Reserved

0x54

Reserved

0x55–0x57

0x58

General Control

Channel Enable A–D, QCLKV

Reserved

0x59–0x5B

0x5C–0x5E

0x5F–0x60

0x61–0x62

0x63

Reserved

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8V19N478 Datasheet

Device Configuration Registers

Table 24. Device Configuration Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x00

Reserved

SRESET

0x01

0x1F

Reserved

I2C_A[6:0]

Reserved

SELSV

Table 25. Device Configuration Register Descriptions

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Soft Reset:

R/W

0

0  Normal operation.

SRESET

Value:

1  Register reset. The device loads the default values into the register 0x02-0xFF.

not reset

Auto-Clear

The content of the register addresses 0x00, 0x01 and the serial interface engine are

not reset.

I²C Device Address (I²C only):

This read-only register stores the binary I²C device address:

11011[I2C_A[1]][I2C_A[0]].

11011

I2C_A[6:0]

SELSV

R

[I2C_A1[1]]

[I2C_A0[0]]

Bits D1 and D0 are determined by the I2C_A pin. For I2C_A[1:0] values based on

I2C_A level, see Table 15.

Select

LOCK/nINT

voltage

Selects the voltage level of the LOCK and nINT outputs:

SELSV:

1

0  LOCK, nINT interface pins are 1.8V

1  LOCK, nINT interface pins are 3.3V (default)

level

Value: 3.3V

R/W

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8V19N478 Datasheet

PLL Frequency Divider Registers

Table 26. PLL Frequency Divider Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x10

PV[7:0]

PV[14:8]

MV[7:0]

0x11

0x12

0x13

Reserved

MV[14:8]

Reserved

SEL_BITS_

MASTER

0x14

Reserved

0x15

0x16

0x19

0x1A

0x1B

LOCK_TH[7:0]

LOCK_TH[14:8]

PF[5:0]

Reserved

FDF

Reserved

MF[7:0]

Reserved Reserved

Reserved

MF8

Table 27. PLL Frequency Divider Register Descriptions

Register Description

Field

Type

Default

(Binary)

Bit Field Name

Description

VCXO-PLL Input Frequency Pre-Divider:

000 0100

0000 0000

The value of the frequency divider (binary coding).

Range: ÷1 to ÷32767

PV[14:0]

R/W

Value: ÷1024

000 0100

VCXO-PLL Feedback-Divider:

0000 0000

The value of the frequency divider (binary coding).

Range: ÷1 to ÷32767

MV[14:0]

Value: ÷1024

0

Input Path Configuration Control:

0 = Input path settings determined by ADR3 control pin.

1 = Input path settings determined by register settings over I²C.

SEL_BITS_MASTER

For input path configurations see Table 13.

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8V19N478 Datasheet

Table 27. PLL Frequency Divider Register Descriptions

Register Description

Field

Type

Default

(Binary)

Bit Field Name

Description

PLL Lock Detect Phase Window Threshold:

The device reports VCXO-PLL lock when the phase difference between the internal

signals f_REFand f_{VCXO_REF}are lower than or equal to the phase difference set by

LOCK_TH[14:0] for more than 1000 f_{VCXO_DIV}clock cycles.

000 0000

1000 0000

LOCK_TH[14:0]

R/W

Requires M_V≥ 4. Set LOCK_TH[14:0] < M_V.

Value: 128

(f_REF f_CLK÷ P_Vis the internal output of the PV divider,

f_{VCXO_DIV} f_VCXO÷ M_Vis the internal output of the MV divider.)

FemtoClock NG Pre-Divider:

The value of the frequency divider (binary coding)

Range: ÷1 to ÷63

00 0001

PF[5:0]

Value: ÷1

00 0000: PF is bypassed

Frequency Doubler:

The input frequency of the FemtoClock NG PLL (2nd stage) is:

0  The output signal of the BYPV multiplexer, divided by the PF divider.

1  The output signal of the BYPV multiplexer, doubled in frequency.

Use this setting to improve phase noise. The PF divider has no effect if FDF  1.

0

FDF

R/W

Value:

f_VCXO÷ PF

FemtoClock NG Feedback-Divider:

The value of the frequency divider (binary coding).

Range: ÷8 to ÷511

0 0001 1000

Value: ÷24

MF[8:0]

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8V19N478 Datasheet

PLL Control Registers

Table 28. PLL Control Bit Field Locations

Bit Field Location

D4

Register Address

D7

D6

D5

D3

D2

D1

D0

0x17

Reserved

OSVEN

Reserved

BYPV

0x18

0x1C

0x1D

0x1E

Reserved

POLV

Reserved

FVCV

Reserved

CPV[4:0]

SRC

Reserved

OFFSET[4:0]

CPF[4:0]

Reserved

Table 29. PLL Control Register Descriptions

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

0

VCXO-PLL Bypass:

0  VCXO-PLL is enabled.

BYPV

R/W

VCXO-PLL 1  VCXO-PLL is disabled and bypassed.

enabled

0

FemtoClock NG PLL Bypass:

0  FemtoClock NG PLL is enabled.

SRC

R/W

PLL

enabled

1  FemtoClock NG PLL is disabled and bypassed. The VCXO-PLL output signal is

frequency divided by the channel dividers.

0

VCXO Polarity:

0  Positive polarity. Use for an external VCXO with a positive f(V_C) characteristics

1  Negative polarity. Use for an external VCXO with a negative f(V_C) characteristics

POLV

Value:

Positive

Polarity

VCXO-PLL Force VC Control Voltage:

1

0  Normal operation.

1  Forces the voltage at the LFV control pin (VCXO input) to V_{DD_V}/2. VCXO-PLL

unlocks and the VCXO is forced to its mid-point frequency. FVCV  1 is the default

setting at startup to center the VCXO frequency. FVCV should be cleared after startup to

enable the PLL to lock to the reference frequency.

FVCV

R/W

Value:

Value: LFV

 V_{DD_V}/2

VCXO-PLL Charge-Pump Current:

0 1111

Controls the charge-pump current I_CPVof the VCXO-PLL. Charge pump current is the

binary value of this register plus one multiplied by 50µA.

CPV[4:0]

I_CPV 50µA  (CPV[4:0] + 1)

Value:

0.8mA

CPV[4:0]  00000 sets ICPV to the min. current of 50µA. Maximum charge-pump

current is 1.6 mA. Default setting is 0.8mA: ((15 + 1)  50µA).

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8V19N478 Datasheet

Table 29. PLL Control Register Descriptions (Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

VCXO-PLL Offset Enable:

0  No offset.

OSVEN

R/W

0

1  Offset enabled. A static phase offset of OFFSET[4:0] is applied to the PFD of the

VCXO-PLL.

VCXO-PLL Static Phase Offset:

Controls the static phase detector offset of the VCXO-PLL. Phase offset is the binary

value of this register multiplied by 0.9 of the PFD input signal,

0 0000

(OFFSET [4:0]  f_PFD÷ 400). The maximum offset is 31  0.927.9

Setting OFFSET to 0.0 eliminates the thermal noise of an offset current. If the

VCXO-PLL input jitter period T_JITexceeds the average input period: set OFFSET to a

value larger than f_PFD T_JIT 400 to achieve a better charge-pump linearity and lower

in-band noise of the PLL.

OFFSET[4:0]

R/W

Value: 0

FemtoClock NG PLL Charge-Pump Current:

1 1000

Controls the charge-pump current I_CPFof the FemtoClock NG PLL. The charge-pump

current is the binary value of this register plus one multiplied by 200µA.

CPF[4:0]

I_CPF 200µA  (CPF[4:0] + 1)

Value:

1.4mA

CPV[4:0]  00000 sets I_CPFto the minimum current of 200µA. Maximum charge-pump

current is 6.4 mA. Default setting is 1.4 mA: ((6 + 1)  200µA).

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8V19N478 Datasheet

Input Selection Mode Registers

Table 30. Input Selection Mode Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x20

VCXO_DIV[4:0]

MODE_BLOCK

nHO_EN

Reserved

nEXT_INT

0x21

0x22

0x23

Reserved

REVS

nM/A[1:0]

INT_SEL

CNTH[7:0]

CNTR[1:0]

Reserved

CNTV[1]

CNTV[0]

Table 31. Input Selection Mode Registers

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Clock Frequency Divider for the input activity monitor:

The clock activity monitor compares the device input frequency (f_IN) to the frequency of

the VCXO divided by VCXO_DIV. For optimal operation of the activity monitor, the

frequency f_VCXO÷ VCXO_DIV should match the input frequency.

E.g. for f_IN 61.44MHz and f_VCXO 61.44MHz, set VCXO_DIV  ÷1.

For f_IN 25MHz and f_VCXO 125MHz, set FCXO_DIV  ÷5.

VCXO_DIV[4:0]

00000

VCXO_DIV[4:0]

R/W

0XX 00 

÷1

100 00  ÷2 101 00  ÷3 110 00  ÷4 111 00  ÷5

100 01  ÷4 101 01  ÷6 110 01  ÷8 111 01  ÷10

Value: ÷1

0XX 01 

÷2

100 10  ÷8 101 10 

110 10 

÷16

111 10  ÷20

111 11  ÷40

÷12

100 11 

0XX 10 

÷4

÷16

101 11 

110 11 

÷32

÷24

0XX 11 

÷8

Inactive Input Clock Block:

0

MODE_BLOCK

nHO_EN

R/W

0  Both input clock signals CLK0 and CLK1 are routed to the input clock multiplexer.

1  The input clock that is currently not active is gated off (blocked).

Value:

Not blocked

Manual Holdover Control:

1

0  Enter holdover on a manual input reference switch.

Value:

Using the EXT_SEL control pin or the INT_SEL control bit, as defined by nEXT_INT for

manual reference switching. nMA[1:0] has no meaning.

Enter

Holdover

Disabled

1  The device switching and holdover modes are controlled by nMA[1:0].

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8V19N478 Datasheet

Table 31. Input Selection Mode Registers (Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

0

Input Clock Selection:

0  The EXT_SEL pin (B3) controls the input clock selection.

nEXT_INT

R/W

Value:

1  The INT_SEL bit (register 0x21, D0) controls the input clock selection.

External

selection

Revertive Switching:

The revertive input switching setting is only applicable to the two automatic selection

modes shown in Table 11. If nM/A[1:0]  X0, the REVS setting has no meaning.

0

0  Disabled: Re-validation of the non-selected input clock has no impact on the clock

REVS

R/W

selection.

Value: Off

1  Enabled: Re-validation of the non-selected input clock will cause a new input

selection according to the pre-set input priorities (revertive switch).

Default setting is revertive switching turned off.

Reference Input Selection Mode:

In any of the manual selection modes (nM/A[1:0]  00 or 10), the VCXO-PLL reference

input is selected by INT_SEL. In any of the automatic selection modes, the VCXO-PLL

reference input is selected by an internal state machine according to the input LOS states

and the priorities in the input priority registers.

00

nM/A[1:0]

R/W

Value:

Manual

selection

00  Manual selection (no holdover)

01  Automatic selection (no holdover)

10  Short-term holdover

11  Automatic selection with holdover

VCXO-PLL Input Reference Selection:

0

Controls the selection of the VCXO-PLL reference input in internal (nEXT_INT  1), and

in manual selection mode (nHO_EN  1, nM/A[1:0]  00 or 10).

In external (nEXT_INT  0) and in automatic selection modes (nM/A[1:0]  X1), INT_SEL

has no meaning.

INT_SEL

R/W

Value:

CLK0

0  CLK_0 is the selected VCXO-PLL reference clock.

1  CLK_1 is the selected VCXO-PLL reference clock.

selected

Short-term Holdover: Hold-off counter period. The device initiates a clock fail-over switch

upon counter expiration (zero transition). The counters start to counts backwards after an

LOS event is detected. The hold-off counter period is determined by the binary number of

VCXO-PLL output pulses divided by CNTR[1:0]. With a VCXO frequency of 125MHz and

CNTR[1:0]  10, the counter has a period of

1000 0000

CNTH[7:0]

Value:

134ms

(1.048ms  binary setting). After each zero-transition, the counter automatically re-loads

to the setting in this register.

The default setting is 134ms (VCXO  125MHz: 1/125MHz  2¹⁷ 128).

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8V19N478 Datasheet

Table 31. Input Selection Mode Registers (Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Short-term Holdover Reference Divider

CNTR[1:0]

CNTH frequency (period; range)

125MHz VCXO

156.25MHz VCXO

10

00  f_VCXO÷ 2¹⁵

01  f_VCXO÷ 2¹⁶

10  f_VCXO÷ 2¹⁷

Revalidation Counter:

3814Hz

(0.262ms; 0ms – 66.8ms)

4768Hz

(0.209ms; 0ms – 53.4ms)

CNTR[1:0]

R/W

Value: 2¹⁷

1907Hz

(0.524ms; 0ms – 133ms)

2384Hz

(0.419ms; 0ms – 106.9ms)

953Hz

(1.048ms; 0ms – 267ms)

1192Hz

(0.838ms; 0ms – 213.9ms)

Controls the number of required consecutive, valid input reference pulses for clock

re-validation on CLK_n for the number of input periods. At an LOS event, the re-validation

counter loads this setting from the register and counts down by one with every valid,

consecutive input signal period. Missing input edges (for one input period) will cause this

counter to re-load its setting. An input is re-validated when the counter transitions to zero

and the corresponding LOS flag is reset.

10

CNTV[1:0]

R/W

Value: 32

00  2 (shortest possible)

01  16

10  32

11  64

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8V19N478 Datasheet

Channel Registers

The content of the channel registers set the channel state, the clock divider the clock phase delay and the power-down state.

Table 32. Channel Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x24: Channel A

0x2C: Channel B

0x34: Channel C

0x40: Channel D

N_A[7:0]

N_B[7:0]

N_C[7:0]

N_D[7:0]

0x25: Channel A

0x2D: Channel B

0x35: Channel C

0x41: Channel D

CLK_A[7:0]

CLK_B[7:0]

CLK_C[7:0]

CLK_D[7:0]

0x26: Channel A

0x2E: Channel B

0x36: Channel C

PD_A

PD_B

PD_C

SEL_ BITS_A

SEL_ BITS_B

SEL_BITS_C

Reserved

D_DIV_FRAC D_DIV_FRAC

0x42: Channel D

PD_D

CH_D_OUT SEL_BITS_D

[1]

[0]

0x3C: Channel D

0x3D: Channel D

0x3E: Channel D

N_D_FRAC[7:0]

N_D_FRAC[15:8]

N_D_FRAC[23:16]

0x3F: Channel D Reserved

Reserved

N_D_INT[3:0]

EN_QCLK_

V

EN_QCLK_

C

0x58

Reserved

EN_QCLK_A EN_QCLK_B

EN_QCLK_D

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8V19N478 Datasheet

Table 33. Channel Register Descriptions^[a]

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Output Frequency Divider N:

N_x[7:0] Divider Value

1000 0000

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0110

÷1

÷2

÷3

÷4

÷5

÷6

÷8

0100 0011

0100 0100

0100 0110

÷10

÷12

÷16

0100 1011

0100 1100

÷20

÷24

0100 0110

Value: ÷16

0101 0011

0100 1110

0101 0100

÷30

÷32

÷36

N_x[7:0]

R/W

0101 1011

0101 0110

÷40

÷48

0110 0011

÷50

0110 0100

0101 1110

÷60

÷64

0101 1111

0110 0110

0110 1110

0111 1011

÷72

÷80

÷96

÷100

0111 1100

0111 0110

÷120

÷128

0111 1110

÷160

Fractional Output Divider, Fractional Part:

0110 0000

0000 0000

Together with N_E_INT, forms the fractional output divider ND value.

N_FRAC







N_D_FRAC[23:0]

R/W

N_E= 2  N_INT+

---------------------



₂24

Value:

6,291,456

The default value is ND  2  (9 + 0.4371839761732)  18.8743679523.

Greatest ND fractional divider is 2  (14 + [2²⁴– 1] / 2²⁴) ≈ 29.99999988.

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8V19N478 Datasheet

Table 33. Channel Register Descriptions^[a](Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Fractional Output Divider, Integer Part:

See N_D_FRAC[23:0]

1001

N_D_INT[3:0]

R/W

Value: 9

Greatest ND fractional divider is 2  (14 + [2²⁴– 1] / 2²⁴) ≈ 29.99999988.

CLK_x Phase Delay:

CLK_x[7:0]

f_VCO 2500MHz:

CLK_x[7:0]

Delay in ps  CLK_x  400ps (256 steps)

CLK_x[7:0] Delay (f_VCO 2500MHz)

R/W

0000 0000

f_VCO 2500MHz

0000 0000

0000 0001

…

0ps

400ps

…

1111 1111

102ns

0

0  Channel x is powered up

1  Channel x is power down

PD_x

EN_x

R/W

Value:

Power-up

0

QCLK_x Channel Output Enable:

0  All outputs of channel x are disabled at the logic low state.

1  All outputs of channel x are enabled.

Value:

Disabled

0

QCLK_V Output Enable:

0  QCLK_V is disabled at the logic low state.

1  QCLK_V is enabled.

EN_QCLK_V

Value:

Disabled

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8V19N478 Datasheet

Table 33. Channel Register Descriptions^[a](Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Bank x Configuration Control:

0  Nx[5:0], PD_X, EN_X settings determined by ADRn control pin.

1  Nx[5:0], PD_X, EN_X settings determined by register settings over I²C.

SEL_BITS_x

R/W

0

Where:

n = 0 for Channels A and C

n = 1 for Channel B

n = 2 for Channel D

D_DIV_FRAC[1:0]:

Post-divider ratio for Bank D fractional divider:

00  ÷1

D_DIV_FRAC[1:0]

R/W

0

01  ÷2

10  ÷4

11  Reserved

CH_D_OUT:

Controls which the divider is used to provide output frequency for Bank D:

CH_D_OUT

0  Integer divider D (ND configures this)

1  Fractional mode (ND_FINT, ND_FRAC, and ND_DIVF configure this)

[a] x  A, B, C, D.

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8V19N478 Datasheet

Output Registers

The content of the output registers set the power-down state, the output style and amplitude.

Table 34. Output Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

A_A0[0]

A_A1[0]

A_A2[0]

A_A3[0]

0x28: QCLK_A0

0x29: QCLK_A1

0x2A: QCLK_A2

0x2B: QCLK_A3

PD_A0

PD_A1

PD_A2

PD_A3

STYLE_A0

STYLE_A1

STYLE_A2

STYLE_A3

A_A0[1]

A_A1[1]

A_A2[1]

A_A3[1]

Reserved

A_B0[0]

A_B1[0]

A_B2[0]

A_A3[0]

0x30: QCLK_B0

0x31: QCLK_B1

0x32: QCLK_B2

0x33: QCLK-B3

PD_B0

PD_B1

PD_B2

PD_B3

STYLE_B0

STYLE_B1

STYLE_B2

STYLE_A3

A_B0[1]

A_B1[1]

A_B2[1]

A_A3[1]

Reserved

A_C0[0]

A_C1[0]

A_C2[0]

A_C3[0]

0x38: QCLK_A0

0x39: QCLK_A1

0x3A: QCLK_A2

0x3B: QCLK_A3

PD_C0

PD_C1

PD_C2

PD_C3

STYLE_C0

STYLE_C1

STYLE_C2

STYLE_C3

A_C0[1]

A_C1[1]

A_C2[1]

A_C3[1]

0x44: QCLK_D0

0x45: QCLK_D1

0x46: QCLK_D2

0x47: QCLK_D3

0x48: QCLK_D4

0x49: QCLK_D5

PD_D0

PD_D1

PD_D2

PD_D3

PD_D4

PD_D5

STYLE_D0

STYLE_D1

STYLE_D2

STYLE_D3

STYLE_D4

STYLE_D5

A_D0[1]

A_D1[1]

A_D2[1]

A_D3[1]

A_D4[1]

A_D5[1]

A_D0[0]

A_D1[0]

A_D2[0]

A_D3[0]

A_D4[0]

A_D5[0]

Reserved

0x4B: QCLK_V

PD_V

STYLE__V1 STYLE__V0

A_V[1]

A_V[0]

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May 15, 2018

8V19N478 Datasheet

Table 35. Output Register Descriptions^[a]

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

0

0  Output QCLK_y is powered-up.

1  Output QCLK_y is power-down.

PD_y

R/W

Value:

Power-up

1

0  Output QCLK_V is powered-up.

1  Output QCLK_V is power-down.

PD_V

R/W

Value:

Power-dow

n

10

QCLK_y, QCLK_V Output Amplitude

Setting for STYLE  0 (LVDS)

Setting for STYLE  1 (LVPECL)

A_y[1:0]

A_V[1:0]

STYLE_y

R/W

Value:

700mV

A[1:0]  00: 350mV

A[1:0]  01: 500mV

A[1:0]  10: 700mV

A[1:0]  11: 850mV

Termination: 100 across

A[1:0]  00: 350mV

A[1:0]  01: 500mV

A[1:0]  10: 700mV

A[1:0]  11: 850mV

Termination: 50 to V_TT

10

Value:

700mV

[b]

1

QCLK_y Output Format:

0  Output is LVDS (Requires LVDS 100 output termination)

Value:

1  Output is LVPECL (Requires LVPECL 50 output termination of to the specified

LVPECL

recommended termination voltage).

QCLK_V Output Format:

01

00  Output is LVDS (Requires LVDS 100 output termination).

01  Output is LVPECL (Requires LVPECL 50 termination to V_TT^[b]).

STYLE_V[1:0]

R/W

Value:

LVPECL

1x  Both QCLK_V and nQCLK_V are single-ended LVCMOS 1.8V outputs, QCLK_V

and nQCLK_V are complementary (180º phase difference).

[a] y  A0,A1,A2,A3,B0,B1,B2,B3,C0,C1,C2,C3,D0,D1,D2,D3,D4,D5.

[b] For V_TT(Termination voltage) values (Table 50).

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8V19N478 Datasheet

Status Registers

Table 36. Status Register Bit Field Locations

Bit Field Location

D4

Register Address

D7

D6

D5

D3

D2

D1

IE_CLK_1

D0

0x4C

Reserved

IE_LOLF

IE_LOLV

IE_REF

IE_HOLD

IE_CLK_0

0x50

0x51

0x53

Reserved

ST_SEL

nLS_LOLF

nLS_LOLV

LS_REF

ST_REF

Reserved

nLS_HOLD LS_CLK_1

nST_HOLD ST_CLK_1

LS_CLK_0

ST_CLK_0

Reserved

nST_LOLF nST_LOLV

Reserved

ST_CAL

Reserved

Table 37. Status Register Descriptions^[a]

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Interrupt Enable for FemtoClock NG PLL Loss-of-lock:

0  Disabled: Setting nLS_LOLF will not cause an interrupt on nINT.

IE_LOLF

R/W

0

1  Enabled: Setting nLS_LOLF will assert the nINT output (nINT  0, interrupt).

Interrupt Enable for VCXO-PLL Loss-of-lock:

IE_LOLV

IE_CLK_n

IE_REF

R/W

0

0  Disabled: Setting nLS_LOLV will not cause an interrupt on nINT.

1  Enabled: Setting nLS_LOLV will assert the nINT output (nINT  0, interrupt).

Interrupt Enable for CLKn input Loss-of-signal:

0  Disabled: Setting LS_CLK_n will not cause an interrupt on nINT.

1  Enabled: Setting LS_CLK_n will assert the nINT output (nINT  0, interrupt).

Interrupt Enable for LS_REF:

0  Disabled: Any changes to LS_REF will not cause an interrupt on nINT.

1  Enabled: Any changes to LS_REF will assert the nINT output (nINT  0, interrupt).

Interrupt Enable for Holdover:

IE_HOLD

0  Disabled: Setting nLS_HOLD will not cause an interrupt on nINT.

1  Enabled: Setting nLS_HOLD will assert the nINT output (nINT  0, interrupt).

FemtoClock NG PLL Loss-of-lock (latched status of nST_LOLF):

Read 0  1 Loss-of-lock events detected after the last status latch clear.

Read 1  No Loss-of-lock detected after the last status latch clear.

Write 1  Clear status latch (clears pending nLS_LOLF interrupt).

nLS_LOLF

nLS_LOLV

R/W

—

VCXO-PLL Loss-of-lock (latched status of nST_LOLV):

Read 0  1 Loss-of-lock events detected after the last status latch clear.

Read 1  No Loss-of-lock detected after the last nLS_LOLV clear.

Write 1  Clear status latch (clears pending nLS_LOLV interrupt).

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8V19N478 Datasheet

Table 37. Status Register Descriptions^[a](Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Input CLK_n Status (latched status of ST_CLK_n):

Read 0  1 LOS events detected on CLK_n after the last LS_CLK_n clear.

Read 1  No loss-of-signal detected on CLK_n input after the last LS_CLK_n clear.

Write 1  Clear LS_CLK_n status latch (clears pending LS_CLK_n interrupts on nINT).

LS_CLK_n

R/W

—

Input Selection (momentary):

Reference input selection status of the state machine. In any input selection mode,

reflects the input selected by the state machine.

ST_SEL

R

0  CLK_0

1  CLK_1

FemtoClock NG PLL Loss-of-lock (momentary):

Read 0  1 Loss-of-lock events detected

Read 1  No Loss-of-lock detected

nST_LOLF

nST_LOLV

ST_CLK_n

LS_REF

R

—

A latched version of this status bit is available (nLS_LOLF).

VCXO-PLL Loss-of-lock (momentary):

Read 0  1 Loss-of-lock events detected

Read 1  No Loss-of-lock detected

A latched version of this status bits is available (nLS_LOLV).

Input CLK_n Status (momentary):

0  LOS detected on CLK_n.

R

1  No LOS detected, CLK_n input is active.

A latched version of this status bits are available (LS_CLK_n).

PLL Reference Status (latched status of ST_REF):

Read 0  Reference is lost since last reset of this status bit.

Read 1  Reference is valid since last reset of this status bit.

Write 1  Clear LS_REF status latch (clears pending LS_REF interrupts on nINT).

R/W

Holdover Status Indicator (latched status of ST_HOLD):

Read 0  VCXO-PLL has entered holdover state 1 times after reset of this status bit.

Read 1  VCXO-PLL is (or attempts to) lock(ed) to an input clock.

Write 1  Clear status latch (clears pending nLS_HOLD interrupt).

nLS_HOLD

FemtoClock NG PLL Calibration Status (momentary):

ST_VCOF

ST_REF

R

—

Read 0  FemtoClock NG PLL auto-calibration is completed.

Read 1  FemtoClock NG PLL calibration is active (not completed).

Input Reference Status.

0  No input reference present.

1  Input reference is present at the clock selected input clock.

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8V19N478 Datasheet

Table 37. Status Register Descriptions^[a](Cont.)

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Holdover Status Indicator (momentary):

0  VCXO-PLL in holdover state, not locked to any input clock.

1  VCXO-PLL is (or attempts to) lock(ed) to input clock.

A latched version of this status bit is available (nLS_HOLD).

nST_HOLD

R

—

FemtoClock NG PLL Calibration Status (momentary):

ST_CAL

R

Read 0  FemtoClock NG PLL auto-calibration is completed.

Read 1  FemtoClock NG PLL calibration is active (not completed).

[a] CLKn  CLK0, CLK1.

General Control Registers

Table 38. General Control Register Bit Field Locations

Bit Field Location

D4

Register Address

D7

D6

D5

D3

D2

D1

D0

0x55

INIT_CLK

0x56

0x57

RELOCK

PB_CAL

Table 39. General Control Register Descriptions

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

W only

Set INIT_CLK  1 to initialize divider functions. Required as part of the startup

procedure.

INIT_CLK

X

Auto-Clear

W only

Setting this bit to 1 will force the FemtoClock NG PLL to re-lock.

RELOCK

PB_CAL

Auto-Clear

Precision Bias Calibration:

Setting this bit to 1 will start the calibration of an internal precision bias current source.

The bias current is used as reference for outputs configured as LVDS, and as reference

for the charge-pump currents. This bit will auto-clear after the calibration completed. Set

as part of the startup procedure.

W only

X

Auto-Clear

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May 15, 2018

8V19N478 Datasheet

Electrical Characteristics

Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the

device. Functional operation of the 8V19N478 at absolute maximum ratings is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 40. Absolute Maximum Ratings

Item

Rating

Supply Voltage, V_{DD_V}and V_{DDO_V}

Inputs

3.6V

-0.5V to V_{DD_V}0.5V

-0.5V to V_{DDO_V}0.5V

Outputs, V_O(LVCMOS)

Outputs, I_O(LVPECL)

Continuous Current

Surge Current

50mA

100mA

Outputs, I_O(LVDS)

Continuous Current

Surge Current

50mA

100mA

Operating Junction Temperature, T_J

Storage Temperature, T_STG

ESD – Human Body Model^[a]

125C

-65C to 150C

2000V

ESD – Charged Device Model^[a]

500V

[a] According to JEDEC JS-001-2012/JESD22-C101.

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8V19N478 Datasheet

Pin Characteristics

Table 41. Input Characteristics, V_{DD_V} 3.3V ±5%, V_{DDO_V} (3.3V, 2.5V or 1.8V) ±5%, T_A= -40°C to +85°C

Symbol

Parameter

Test Conditions

OSC, nOSC

Minimum

Typical

Maximum

Units

Input Capacitance

2

4

pF

[a]

C_IN

Other inputs

R_PU

R_PD

Input Pull-Up Resistor

nCLK_0, nCLK_1

51

k

Input Pull-Down Resistor

CLK_0, nCLK_0, CLK_1, nCLK_1,

EXT_SEL, ADR1/MISO, I2C

R_OUT

LVCMOS Output Impedance nINT, LOCK

25^[b]

W

[a] Guaranteed by design.

[b] Design target specifications.

DC Characteristics

The device is configured to the maximum values of register settings, all outputs enabled in LVDS mode, and amplitude of 850mV.

Process variation is included for the maximum current consumption.

Table 42. Pow er Supply DC Characteristics, V_{DD_V} 3.3V ±5%, V_{DDO_V} (3.3V, 2.5V, or 1.8V) ±5%,

T_A= -40°C to +85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_{DD_V}

Core Supply Voltage

3.135

1.71

3.3

1.8, 2.5, 3.3

580

3.465

1024

V

V_{DDO_V}Output Supply Voltage

I_{DD_V}Power Supply Current

mA

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May 15, 2018

8V19N478 Datasheet

Table 43. Typical Pow er Supply DC Current Characteristics, V_{DD_V} 3.3V ±5%, V_{DDO_V} (3.3V, 2.5V, or

1.8V) ±5%, T_A= -40°C to +85°C^[a]

Test Case

[b]

[c]

Symbol

Supply Pin Current

V_{DDO_QCLKA _QCLKB}

1

2

3

4

5

6

Units

,

3.3

LVPECL

On

3.3

LVPECL

On

1.8

LVPECL

On

1.8

LVPECL

On

V

–

Style

LVDS

On

LVDS

On

QCLK_A[3:0],

QCLK_B[3:0]

–

State

–

Amplitude

700

850

700

500

350

mV

V

V_{DDO_QCLKC _QCLKD}

,

3.3

1.8

Style

LVDS

On

LVDS

On

LVPECL

On

LVPECL

On

LVDS

On

LVDS

On

–

QCLK_C[3:0],

QCLK_D[5:0]

–

State

–

Amplitude

700

850

700

500

350

mV

A

I_{DD_COA}Current through V_{DDO_QCLKA}pin

I_{DD_CA}Current through V_{DD_QCLKA}pin

I_{DD_COB}Current through V_{DDO_QCLKB}pin

I_{DD_CB}Current through V_{DD_QCLKB}pin

I_{DD_COC}Current through V_{DDO_QCLKC}pin

I_{DD_CC}Current through V_{DD_QCLKC}pin

I_{DD_COD}Current through V_{DDO_QCLKD}pin

0.088

0.039

0.088

0.034

0.088

0.039

0.132

0.044

0.009

0.013

0.077

0.060

0.014

0.056

0.006

0.787

2.596

0.109

0.039

0.109

0.034

0.109

0.039

0.164

0.044

0.009

0.013

0.081

0.060

0.014

0.056

0.006

0.887

2.928

0.135

0.037

0.131

0.038

0.135

0.036

0.188

0.045

0.009

0.013

0.080

0.060

0.014

0.055

0.006

0.982

3.242

2.165

0.123

0.037

0.118

0.038

0.122

0.036

0.170

0.045

0.009

0.013

0.080

0.060

0.014

0.055

0.006

0.927

3.058

2.051

0.104

0.037

0.099

0.038

0.139

0.036

0.196

0.045

0.009

0.013

0.080

0.060

0.014

0.055

0.006

0.931

2.267

2.025

0.090

0.037

0.087

0.038

0.119

0.036

0.167

0.045

0.009

0.013

0.080

0.060

0.014

0.055

0.006

0.857

2.132

1.881

A

I_{DD_CD}

I_{DD_SPI}

I_{DD_INP}

Current through V_{DD_QCLKD}pin

Current through V_{DD_I2C}pin

Current through V_{DD_INP}pin

A

I_{DD_LCV}Current through V_{DD_LCV}pin

I_{DD_LCF}Current through V_{DD_LCF}pin

I_{DD_CPV}Current through V_{DD_CPV}pin

I_{DD_CPF}Current through V_{DD_CPF}pin

I_{DD_OSC}Current through V_{DD_OSC}pin

I_{DD_TOT}Total Device Current Consumption

P_{TOT, SYS}Total System Power Consumption^[d]

A

W

P_TOT

Total Device Power Consumption

[a] Design target specifications.

[b] f_CLK(input)  40MHz, f_VCXO 156.25MHz, f_VCO 2500MHz, PV  160, MV  625, MF  8, FDF  1. Supply current is independent of the output

frequency configuration used for this table: QCLKA[3:0]  41.66MHz, QCLKB[3:0]  500MHz, QCLKC[3:0]  31.25MHz, QCLKD[5:0]  500MHz.

QCLK_y outputs terminated according to amplitude settings: LVPECL outputs terminated to V_TT

.

[c] f_CLK(input)  125MHz, f_VCXO 156.25MHz, f_VCO 2500MHz, PV  1024, MV  1280, MF  8, FDF  1. Supply current is independent of the

output frequency configuration used for this table: QCLKA[3:0]  125MHz, QCLKB[3:0]  156.25MHz, QCLKC[3:0]  250MHz,

QCLKD[5:0]  312.5MHz. QCLK_y outputs terminated according to amplitude settings: LVPECL outputs terminated to V_TT

.

[d] Includes total device power consumption and the power dissipated in external output termination components.

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8V19N478 Datasheet

Table 44. LVCMOS DC Characteristics, V_{DD_V} 3.3V ±5%, V_{DDO_V} (3.3V, 2.5V, or 1.8V) ±5%,

T_A= -40°C to +85°C^[a]

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Control inputs, (1.8V/JESD7A-8 logic, input hysteresis and 3.3V tolerance)

-0.3

V_I

V_T

V_T-

V_H

Input Voltage

V_{DD_V}

1.365

1.170

0.780

150

V

Positive-going Input Threshold Voltage

Negative-going Input Threshold Voltage

Hysteresis Voltage

0.660

0.495

0.165

V

V_T– V_T-

V

Input High Current

Input (PD)^[b]and

Input (PD/PU)^[c]

V_{DD_V} 3.3V, V_IN 3.3V

µA

I_IH

Input (PU)^[d]

Input (PD)^[b]

5

Input Low Current

V_{DD_V} 3.465V, V_IN 0V

-5

µA

Input (PU)^[d]and

Input (PD/PU)^[c]

-150

I_IL

Control outputs ADR1/MISO (when output), nINT, LOCK configured to 3.3V (SELSV0  0, SELSV1  0)

V_OH

V_OL

Output High Voltage ADR1/MISO (when

output), nINT,

Output Low Voltage

LOCK

I_OH -4mA

I_OL 4mA

2.0

V

0.55

Control outputs ADR1/MISO (when output), nINT, LOCK configured to 1.8V (SELSV0  1, SELSV1  1)

V_OH

V_OL

Output High Voltage

Output Low Voltage

I_OH -4mA

I_OL 4mA

1.35

1.8

V

0.45

Clock outputs QCLK_V, nQCLK_V configured to LVCMOS (STYLE_V[1:0]  1)

V_OH

V_OL

Output High Voltage

Output Low Voltage

I_OH -8mA

I_OL 8mA

1.35

1.8

V

0.45

[a] Design target specifications.

[b] EXT_SEL.

[c] I2C_A, ADR3, ADR2, ADR1, ADR0.

[d] SDAT, SCL.

Table 45. Differential Input DC Characteristics, V_{DD_V} 3.3V ±5%, V_{DDO_V} (3.3V, 2.5V, or 1.8V) ±5%,

T_A= -40°C to +85°C

Symbol

Parameter

Pull-down inputs^[a]

Test Conditions

Minimum

Typical

Maximum Units

V_{DD_V} V_IN 3.465V

150

µA

Input

High Current

I_IH

Pull-down/pull-up

inputs^[b]

Pull-down inputs^[a]

V_{DD_V} 3.465V, V_IN 0V

-150

µA

Input

Low Current

I_IL

Pull-down/pull-up

inputs^[b]

[a] Non-Inverting inputs: CLK_0, CLK_1, OSC.

[b] Inverting inputs: nCLK_0, nCLK_1, nOSC.

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8V19N478 Datasheet

Table 46. LVPECL DC Characteristics (QCLK_y, STYLE  1), V_{DD_V} 3.3V ±5%, V_{DDO_V} (3.3V, 2.5V, or

1.8V) ±5%, T_A= -40°C to +85°C^[a]

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_{DDO_V}- 1.034 V_{DDO_V}- 0.892 V_{DDO_V}- 0.750

V_{DDO_V}- 1.057 V_{DDO_V}- 0.912 V_{DDO_V}- 0.768

V_{DDO_V}- 1.092 V_{DDO_V}- 0.950 V_{DDO_V}- 0.808

V_{DDO_V}- 1.087 V_{DDO_V}- 0.960 V_{DDO_V}- 0.833

V_{DDO_V}- 1.413 V_{DDO_V}- 1.265 V_{DDO_V}- 1.117

V_{DDO_V}- 1.574 V_{DDO_V}- 1.420 V_{DDO_V}- 1.266

V_{DDO_V}- 1.782 V_{DDO_V}- 1.633 V_{DDO_V}- 1.485

V_{DDO_V}- 1.918 V_{DDO_V}- 1.778 V_{DDO_V}- 1.638

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

V

V_OH

Output High Voltage^[b][c]

V_OL

Output Low Voltage^[b][c]

[a] Design target specifications.

[b] Outputs terminated with 50 to V_TT. For termination voltage V_TTvalues (Table 50).

[c] 700mV and 850mV amplitude settings are only available at V_{DDO_V}≥ 2.5V.

Table 47. LVDS DC Characteristics (QCLK_y, STYLE = 0), V_{DD_V}= 3.3V ± 5%, V_{DDO_V}= (3.3V, 2.5V, or

1.8V) ±5%, T_A= -40°C to +85°C^[a]

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_{DDO_V}- 1.034 V_{DDO_V}- 0.947 V_{DDO_V}- 0.862

V_{DDO_V}- 1.133 V_{DDO_V}- 1.045 V_{DDO_V}- 0.961

V_{DDO_V}- 1.229 V_{DDO_V}- 1.142 V_{DDO_V}- 1.056

V_{DDO_V}- 1.316 V_{DDO_V}- 1.226 V_{DDO_V}- 1.138

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

V

V_OS

Offset Voltage^[b][c]

V

25

50

V_OS

V_OSMagnitude Change

mV

[a] Design target specifications.

[b] V_OSchanges with V_DD

[c] 700mV and 850mV amplitude settings are only available at V_{DDO_V}≥ 2.5V.

.

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8V19N478 Datasheet

AC Characteristics

Table 48. AC Characteristics, V_{DD_V}= 3.3V ±5%, V_{DDO_V}= (3.3V, 2.5V, or 1.8V) ±5%,

T_A= -40°C to +85°C^[a][b]

Symbol

Parameter

Input Frequency

Test Conditions

Minimum

Typical

Maximum

Units

f_IN

CLK_n

0.008

10

250

MHz

f_VCXO

VCXO Frequency

156.25

Phase-Frequency Detector

Frequency

FemtoClock NG

f_{PFD, F}

f_VCO

VCO Frequency Range

2400

1200

600

300

240

150

120

80

2500

1250

625

MHz

QCLK_y, N  1

QCLK_y, N  2

QCLK_y, N  4

QCLK_y, N  8

QCLK_y, N  10

QCLK_y, N  16

QCLK_y, N  20

Integer

Divider

312.5

250

Output

f_OUT

Frequency

156.25

125

Fractional QCLK_D, ND range: 29.99 to 8.33

Divider

300

Integer output divider N[A:C]

0

ppb

f_OUT

Output Frequency Accuracy

Fractional output divider ND,

10

f_OUT 156.25MHz

Input Voltage

Amplitude^[c]

CLK_n

0.15

0.3

1.2

2.4

V

V_IN

Differential

V_{DIFF_IN}Input Voltage

Amplitude^{[c] [d]}

Common Mode Input Voltage

Output Duty Cycle

1.0

45

V_{DD_V}– (V_{IN /}

V

V_CMR

odc

)

2

QCLK_y

50

55

%

Output Rise/Fall Time,

Differential

QCLK_y (LVPECL), 20% to 80%

QCLK_y (LVDS), 20% to 80%

LVCMOS outputs, 20%-80%

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

200

300

1.2

ps

t_R/ t_F

ps

Output Rise/Fall Time

ns

351

477

388

528

mV

LVPECL

Output Voltage Swing,

Peak-to-peak, 156.25MHz

645

711

770

850

[e]

V_O(PP)

702

776

LVPECL

954

1055

1422

1700

Differential Output Voltage

Swing, Peak-to-peak,

156.25MHz

1290

1540

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May 15, 2018

8V19N478 Datasheet

Table 48. AC Characteristics, V_{DD_V}= 3.3V ±5%, V_{DDO_V}= (3.3V, 2.5V, or 1.8V) ±5%,

T_A= -40°C to +85°C^[a][b](Cont.)

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

350mV amplitude setting

500mV amplitude setting

700mV amplitude setting

850mV amplitude setting

QCLK_y (same N divider)

265

362

340

465

mV

ps

LVDS

Output Voltage Swing,

Peak-to-peak, 156.25MHz

611

676

746

818

[f]

V_OD

530

680

LVDS

724

929

Differential Output Voltage

Swing, Peak-to-peak,

156.25MHz

1222

1492

1351

1635

60

50

Output Skew^{[g] [h]}

All delays set to 0

tsk(o)

QCLK_y (any N divider, incident rising

edge)

ps

LOS State Detected

(measured in input reference

periods)

f_IN125MHz

f_IN125MHz

2

3

T_IN

ms

t_{D, LOS}

PLL re-lock time after a short-term

holdover scenario. Measured from LOS

to both PLLs lock-detect asserted;

hold-off timer  200,

VCXO-PLL bandwidth  30Hz, 100Hz

initial frequency error <200ppm

300

30Hz -

30.2

t_{D, LOCK}PLL Lock Detect

100Hz -

22.6

Refer to PLL lock detect t_D,LOCK

.

30Hz -

0.049

20

ns

Reference point: final value of clock

output phase after all phase transitions

settled.

PLL Lock Residual Time

Error

t_{D, RES}

100Hz -

0.191

Max. frequency deviation during a

holdover duration of 200ms and after the

clock re-validate event

30Hz -

1.57

±5.0

ppm

f_HOLDHoldover Accuracy

100Hz -

3.34

[a] Design target specifications.

[b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been

reached under these conditions.

[c] V_ILshould not be less than -0.3V and V_IHshould not be greater than V_{DD_V}

[d] Common Mode Input Voltage is defined as the cross-point voltage.

.

[e] LVPECL outputs terminated with 50 to V_{DDO_V}– 1.6V (350mV amplitude setting), V_{DDO_V}– 1.75V (500mV amplitude setting),

V_{DDO_V}– 1.95V (700mV amplitude setting), V_{DDO_V}– 2.1V (850mV amplitude setting).

[f] LVDS outputs terminated 100 across terminals.

[g] This parameter is defined in accordance with JEDEC standard 65.

[h] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

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8V19N478 Datasheet

Table 49. Clock Phase Noise Characteristics (f_VCXO156.25MHz), V_{DD_V}3.3V ±5%,

[a][b][c]

V_{DDO_V} (3.3V, 2.5V, or 1.8V) ±5%, T_A= -40°C to +85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Clock RMS

Phase Jitter

(Random)

156.25MHz Integration Range: 12kHz – 20MHz

65

58

fs

tjit(Ø)

250MHz

500MHz

Integration Range: 12kHz – 20MHz

 (10)

Clock

10Hz offset (determined by VCXO)

100Hz offset (determined by VCXO)

1kHz offset from carrier

-66.8

-85.7

dBc/Hz

N

Single-side

Band Phase

Noise

 (100)

N

 (1k)

-116.3

-133

-110

-120

N

(integer divider)

 (10k)

10kHz offset from carrier

N

 (100k)

100kHz offset from carrier

1MHz offset from carrier

-137.6

-145.4

-157.5

N

 (1M)

-142

-150

N

10MHz offset from carrier and

noise floor

 (10M)

N

 (10)

Clock

250MHz

10Hz offset (determined by VCXO)

100Hz offset (determined by VCXO)

1kHz offset from carrier

-73.8

-91.4

dBc/Hz

N

Single-side

Band Phase

Noise

 (100)

N

 (1k)

-122.0

-138.9

-143.8

-151.3

-160.9

N

(integer divider)

 (10k)

10kHz offset from carrier

-130

-135

-150

-155

N

 (100k)

100kHz offset from carrier

1MHz offset from carrier

N

 (1M)

N

10MHz offset from carrier and

noise floor

 (10M)

N

 (10)

Clock

156.25MHz 10Hz offset (determined by VCXO)

100Hz offset (determined by VCXO)

1kHz offset from carrier

-77.8

-95.8

dBc/Hz

N

Single-side

Band Phase

Noise

 (100)

N

 (1k)

-126.9

-142.9

-148

N

(integer divider)

 (10k)

10kHz offset from carrier

N

 (100k)

100kHz offset from carrier

N

 (1M)

1MHz offset from carrier

-155.3

-162.8

N

10MHz offset from carrier and

noise floor

 (10M)

N

 (10)

Clock

125MHz

10Hz offset (determined by VCXO)

100Hz offset (determined by VCXO)

1kHz offset from carrier

-80.8

-97.9

dBc/Hz

N

Single-side

Band Phase

Noise

 (100)

N

 (1k)

-128.5

-144.7

-149.9

-156.8

-162.2

-120

-130

-135

-150

-155

N

 (10k)

10kHz offset from carrier

N

 (100k)

100kHz offset from carrier

1MHz offset from carrier

N

 (1M)

N

10MHz offset from carrier and

noise floor

 (10M)

N

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May 15, 2018

8V19N478 Datasheet

[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted

in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been

reached under these conditions.

[b] Phase noise specifications are applicable for all outputs active, Nx not equal.

[c] VCXO characteristics: 156.25MHz and phase noise -67.9dBc/Hz at 10Hz, -97.9dBc/Hz at 100Hz, -121.9dBc/Hz at 1kHz, -141.9dBc/Hz at 10kHz,

-152.9dBc/Hz at 100kHz.

Clock Phase Noise Characteristics

VCXO characteristics: 156.25MHz and phase noise -67.9dBc/Hz at 10Hz, -97.9dBc/Hz at 100Hz, -121.9dBc/Hz at 1kHz, -141.9dBc/Hz at

10kHz, -152.9dBc/Hz at 100kHz.

▪ Input reference frequency: 20MHz

▪ VCXO-PLL bandwidth: 30Hz

▪ VCXO-PLL charge pump current: 0.75mA

▪ FemtoClock-NG PLL bandwidth: 342kHz

▪ V_{DD_V} 3.3V, T_A 25°C

Figure 5. 312.5MHz Output Phase Noise

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8V19N478 Datasheet

Figure 6. 125MHz Output Phase Noise

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May 15, 2018

8V19N478 Datasheet

Figure 7. 156.25MHz Output Phase Noise

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May 15, 2018

8V19N478 Datasheet

Figure 8. 250MHz Output Phase Noise

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8V19N478 Datasheet

Figure 9. 500MHz Output Phase Noise

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8V19N478 Datasheet

Applications Information

VCXO-PLL Loop Filter

Each of the two PLLs uses a loop filter with external components. The value of the external components depends on the desired loop

bandwidth for each PLL, the input clock frequency, and in the case of the VCXO-PLL on the external VCXO component. For the

VCXO-PLL (first PLL stage), a 2nd or 3rd order loop filter may be used. The loop filter of the VCXO-PLL is connected to the device

through the LFV charge-pump input. The filter output is connected to the control voltage input of the external VCXO. The FemtoClock NG

PLL (second PLL stage) may use a 2nd order loop filter. The LFF output of the device connects to filter input and LFFR to the filter output.

Typical loop filters are shown in Figure 10 (2nd order) in Figure 11 (3rd order) and are discussed below. Step by step calculations to

determine the value of the loop filter components values are shown.

Figure 10. Second-Order Loop Filter

VCXO

LFV Output

Control Input

(charge pump)

C_Z

C_P

R_Z

Step-by-step Calculation

Step 1: Determine the desired loop bandwidth f_C. f_Cmust satisfy the following condition:

f

PD

---------- » 20

f

C

Where f_PDis the input frequency of the VCXO-PLL phase detector frequency.

Step 2: Calculate R_Zby:

2    f  M

C

V

R

= ---------------------------------------------------

Z

I

 K

CP

VCXO

Where I_CPis the VCXO-PLL charge-pump current and K_VCXOis the gain of the VCXO component (consult the datasheet of the external

VCXO for its gain parameter). M_Vis the effective feedback divider:

f

VCXO

M

=

------------------------

V

f

PD

f

_VCXOis the frequency of the external VCXO component.

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8V19N478 Datasheet

Step 3: Calculate C_Zby:

f

C

 =

------

f

Z



C

Z

=

--------------------------------------------

2    f  R

C

Z

α is ratio between the loop bandwidth and the filter zero. f_Zis the filter zero. α should be greater than 3.

Step 4: Calculate C_Pby:

C

Z

  

C

=

--------------

P

f

P

 =

------

f

C

f_Pis the pole and β is ratio between the pole and the loop bandwidth. β should be greater than 3.

Step 5: Verify that the phase margin PM is greater than 50°.

b – 1

PM = atan

--------------------

2 

b

C

Z

C

P

b =

+ 1

--------

Example calculation: The Block Diagram shows a 2nd order loop filter for the VCXO-PLL. In this example, the VCXO-PLL reference

frequency is 122.88MHz, and an external VCXO component of 122.88MHz is used. The desired VCXO-PLL loop bandwidth f_Cis 40Hz. To

achieve the desired loop bandwidth with small size loop filter components, set the PLL frequency pre-divider P_V, and the PLL feedback

divider M_Vto 1024. According to the step 1 instruction, f_PDis 120kHz. This satisfies the condition f_PD/f_C>> 20. R_Zis calculated 32.2k.

The VCXO gain K_VCXOused for the device reference circuit is 10kHz/V. The charge-pump current of the VCXO-PLL is configurable from

50µA to 1200µA. The charge-pump current is programmed to I_CP 800uA. For α  8, C_Zis calculated to be 0.99µF. C_Zgreater than this

value assures α > 12. For example, the actual chosen value is the standard capacitor value of 1µF. For β  5, C_Pis calculated 24.7nF.

The standard capacitor value of C_P 27ps ensures β > 7.

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8V19N478 Datasheet

Figure 11. Third-Order Loop Filter

VCXO

LFV Output

Control Input

(charge pump)

R_P2

C_P2

C_Z

C_P

R_Z

Figure 11 shows a third-order loop filter. The filter is equivalent to the 2nd order filter in Figure 12 with the addition components R_P2and

C

_P2. The additional components R_P2and C_P2should be calculated as shown:

R

 C

Z

P

C

=

-------------------------

P2

R

 

P2

R

 1.5  R

P2

Z

 is the ratio between the 1^stpole and the 2^ndpole.  should be greater than 3.

Example calculation for the 3^rdorder loop filter shown in Figure 11: Equivalent to the 2nd order loop filter calculation, R_Z 33k, C_Z

1µF, and C_P 27nF. R_P2should be in the range of 0.5·R_Z< R_P2< 2.5·R_Z, for instance 51k With   4, C_P2is 4.37nF (select 4.7µF).

FemtoClock NG PLL Loop Filter

Figure 12 shows a 2nd order loop filter for the FemtoClock NG PLL. This loop filter is equivalent to Figure 10 and uses the loop filter

components R_ZF(R_Z), C_ZF(C_Z), and C_PZ(C_P). The VCO frequency of the FemtoClock NG PLL is 2500MHz.

Figure 12. 2nd Order Loop Filer for FemtoClock NG PLL

LFFR

C_ZF

C_PF

R_ZF

LFF

Example calculation for the 2nd order loop filter shown in Figure 12: the FemtoClock NG receives its reference frequency from the

VCXO output. With the P_Fpre-divider set to 1, the phase detector frequency is also 122.88MHz. The PLL feedback divider must be set to

M_F 24 in order to locate the VCO frequencies in its center range. A target PLL loop bandwidth f_Cis 80kHz satisfies the condition in step

1. The gain of the internal VCO is 30MHz/V and the charge-pump current I_CPis set to 3.6mA. Using the formula for R_Zin step 2, R_ZFis

calculated 103 (chose the standard value of 100; using the formula for C_Zin step 3, C_ZFis calculated 88nF for α  4. A capacitor

larger than 88nF should be used for C_ZFto assure that the α is greater than 4, for instance the standard component capacitor value

100nF.

With β  6, C_PZis calculated to be 3.6nF as shown in step 4. A capacitor less than 3.6nF should be used for C_PZto assure that β remains

greater than 6, for instance the standard capacitor value of 1nF is selected for C_PZ.The selected 2nd order loop filter components are

R

_ZF 100C_ZF 100nF and C_PZ 1nF.

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8V19N478 Datasheet

Output Termination

LVPECL-style Outputs

Differential outputs configured to LVPECL-style are an open-emitter type, and require a termination with a DC current path to GND. This

section displays parallel and thevenin termination, Y-termination and source termination for various output supply (V_{DDO_V}), and

amplitude settings. V_TTis the termination voltage.

Figure 13. LVPECL Parallel Termination 1

VDD_v

Zo = 50

+

-

R2

50

R1

50

LVPECL Driv er

High Impedance Input

N o Built- in T er mination

VTT

Table 50. Termination Voltage V_TT(Figure 13)^[a]

LVPECL Amplitude (mV)

V (V)

TT

350

500

700

850

V_{DDO_V}– 1.60

V_{DDO_V}– 1.75

V

_{DDO_V}– 1.95

_{DDO_V}– 2.10

[a] Output power supplies supporting 3.3V, 2.5V and 1.8V are V_{DDO_QCLKA}, V_{DDO_QCLKB}, V_{DDO_QCLKC}and

V_{DDO_QCLKD}

.

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8V19N478 Datasheet

Figure 14. LVPECL Parallel Termination 2

VD D_v

VDD_v

R1

R3

+

-

Zo = 50

R2

R4

LVPECL Driv er

High Impedance Input

N o Built-in Termination

Table 51. Termination Resistor Values (Figure 14)

[a]

V

(V)

LVPECL Amplitude (mV)

R1, R3 ()

R2, R4 ()

DDO_V

350

500

700

850

350

500

700

850

350

500

97.1

106.5

122

103.1

94.3

84.6

78.6

78.1

71.4

64.1

59.5

56.3

50

3.3

137.5

138.8

166.7

227.3

312.5

450

2.5

1.8

–

[a] Output power supplies supporting 3.3V, 2.5V, and 1.8V are V_{DDO_QCLKA}, V_{DDO_QCLKB}, V_{DDO_QCLKC}and V_{DDO_QCLKD}

.

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8V19N478 Datasheet

Figure 15. LVPECL Y-Termination

VDD_v

Zo = 50

+

-

R2

50

R1

50

LVPECL Driv er

High Impedance Input

N o Built-in Termination

C1

0. 1uF(opt ional)

R3

Table 52. Termination Resistor Values (Figure 15)

[a]

V

(V)

LVPECL Amplitude (mV)

R3 ()

DDO_V

3.3

350, 500, 700, 850

350, 500

50

18

0

2.5

1.8

[a] Output power supplies supporting 3.3V, 2.5V, and 1.8V are V_{DDO_QCLKA}, V_{DDO_QCLKB}, V_{DDO_QCLKC}and V_{DDO_QCLKD}

.

Figure 16. LVPECL Source Termination

VDD_v

LVPECL Driv er

Zo = 50

+

-

R3

100

R2

R1

High Impedance Input

No Built-in Termination

Table 53. Termination Resistor Values (Figure 16)

[a]

V

(V)

LVPECL Amplitude (mV)

R1, R2 ()

DDO_V

3.3

350, 500, 700, 850

350

100 – 200

80 – 150

50 – 100

2.5

1.8

[a] Output power supplies supporting 3.3V, 2.5V, and 1.8V are V_{DDO_QCLKA}, V_{DDO_QCLKB}, V_{DDO_QCLKC}and V_{DDO_QCLKD}

.

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8V19N478 Datasheet

LVDS-Style Outputs

LVDS style outputs support fully differential terminations. LVDS does not require board level pull-down resistors for DC termination.

Figure 17 and Figure 18 show typical termination examples with DC coupling for the LVDS style driver. In these examples, the receiver is

high input impedance without built-in termination. LVDS-style with a differential termination is preferred for best common-mode rejection

and lowest device power consumption.

Figure 17. LVDS Termination

VCC=3.3V

Zo = 50

+

-

R1

100

LVDS Style Driver

High Impedance Input

No Built-in Termination

Figure 18. LVDS Termination (Alternative)

VDD_v

Zo = 50

+

-

R2

50

R1

50

LVDS St yle Driver

High Impedance Input

N o Built- in T er mination

C1

0. 1uF (opt ional )

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8V19N478 Datasheet

Power Supply Filtering

Please refer to the document 8V19N470 Hardware Design Guide for comprehensive information about power supply and isolation, loop

filter design for VCXO and VCO, schematics, input and output interfaces/terminations and an example schematics. This document shows

a recommended power supply filter schematic in which the device is operated at V_{DD_V}= 3.3V (the output supply voltages of V_{DDO_V}

=

3.3V, 2.5V, and 1.8V are supported). This example focuses on power supply connections and is not configuration specific. Refer to the

pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application.

As with any high-speed analog circuitry, the power supply pins are vulnerable to the board supply or device generated noise. This device

requires an external voltage regulator for the V_{DD_V}pins for isolation of board supply noise. This regulator (example component:

PS7A8300RGT) is indicated in the schematic by the power supply, VREG_3.3V. Consult the voltage regulator specification for details for

the required performance. To achieve optimum jitter performance, power supply isolation is required to minimize device generated noise.

The V_{DD_LCF}terminal requires the cleanest power supply. The device provides separate power supplies to isolate any high switching

noise from coupling into the internal PLLs and into other outputs as shown. In order to achieve the best possible filtering, it is

recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If

space is limited, the 0.1µF and 0.01µF capacitors in each power pin filter should be placed on the device side. The other components

can be on the opposite side of the PCB. To set configuration pins, pull-up and pull-down resistors can all be placed on the PCB side,

opposite the device side, to free up device side area if necessary.

Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The

filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component

values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage

stability suggests adding bulk capacitance in the local area of all devices.

Thermal Characteristics

Table 54. Thermal Characteristics for the 100-FPBGA Package^[a]

Multi-Layer PCB, JEDEC Standard Test Board

[b]

Symbol

Thermal Parameter

Junction-to-ambient

Condition

Value

Unit

0m/s air flow

1m/s air flow

2m/s air flow

3m/s air flow

4m/s air flow

5m/s air flow

24.06

20.89

19.07

18.05

17.46

17.03

8.54

°C/W



JA





Junction-to-case

JC

JB

Junction-to-board^[c]

Junction-to-board^[d]

6.43

4.15

[a] Standard JEDEC 2S2P multilayer PCB.

[b] Estimated thermal values.

[c] Thermal model where the majority (>90%) of the heat dissipated in the component is conducted through the package bottom (balls).

T_Bis measured on or near the component lead.

[d] Thermal model where the heat dissipated to the ambient from all directions. T_Bis measured on or near the component lead.

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May 15, 2018

8V19N478 Datasheet

Temperature Considerations

The device supports applications in a natural convection environment as long as the junction temperature does not exceed the specified

junction temperature T_J. In applications where the heat dissipates through the PCB, _JBis the correct metric to calculate the junction

temperature. The following calculation uses the junction-to-board thermal characterization parameter _JBto calculate the junction

temperature (T_J). Care must be taken to not exceed the maximum allowed junction temperature T_Jof 125 °C.

The junction temperature T_Jis calculated using the following equation: T = T + P

 

TOT JB

J

B

where:

▪ T_Jis the junction temperature at steady state conditions in °C.

▪ T_Bis the board temperature at steady state condition in °C, measured on or near the component lead.

▪ _JBis the thermal characterization parameter to report the difference between T_Jand T_B.

▪ P_TOTis the total device power dissipation.

Maximum power dissipation scenario: With the maximum allowed junction temperature and the maximum device power consumption and

at the maximum supply voltage of 3.3V + 5%, the maximum supported board temperature can be determined. In the device configuration

for the maximum power consumption, IDD_V is 1.024A. In this configuration, all outputs are active and configured to LVDS, the output

amplitude is set to 850mV and outputs use a 100 Ohm termination:

▪ Total system power dissipation (incl. termination resistor power): PTOT = VDD_V, MAX · IDD_V, MAX = 3.465V · 1.024A = 3.548W

In this scenario and with the Theta_JB thermal model, the maximum supported board temperature is as follows:

TB, MAX = TJ_MAX - Theta_JB · PTOT

TB, MAX = 125°C - 6.43°C/W · 3.548W = 102.2°C

Table 55. Typical Power Consumption

Device

Theta JB Thermal model

[a]

[b]

IDD_TOT

A

PTOT

W

T

J

B, MAX

Test Case

C

1b

2b

3c

4c

5c

6c

0.787

0.887

0.982

0.927

0.931

0.857

2.596

2.928

2.165

2.051

2.025

1.881

101.7

103.8

98.9

98.2

98.0

97.1

108.3

106.2

111.1

111.8

112.0

112.9

[a] Junction temperature at board temperature T_B= 85°C

[b] Maximum board temperature for junction temperature < 125°C: T_{B, MAX}= T_{J, MAX}- _JBx P_TOT

.

Package Outline Draw ings

The package outline drawings are appended at the end of this document and are accessible from the link below. The package information

is the most current data available.

www.idt.com/document/psc/bdbdg100-package-outline-110-mm-sq-body-10-mm-pitch-cabga

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May 15, 2018

8V19N478 Datasheet

Marking Diagram

1. Line 1 and Line 2 is the part number.

2. “#” denotes stepping.

3. “YYWW” denotes: “YY” is the last two digits of the year, and “WW” is a work week number

that the part was assembled.

4. “$” denotes the mark code.

Ordering Information

Part/Order Number

Marking

Package

Shipping Packaging

Temperature

8V19N478BDGI

8V19N478BDGI8

IDT8V19N478BDGI

IDT8V19N478BDG

11  11  1 mm 100-FPBGA

Tray

-40°C to +85°C

Tape and Reel

Glossary

Abbreviation

Description

Index n

Index x

Index y

V_{DD_v}

Denominates an clock input. Range: 0 to 1.

Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D.

Denominates a QCLK output and associated configuration bits. Range: A0, A1, A2, B0, B1, B2, C0, C1, D0, D1.

Denominates core voltage supply pins. Range: V_{DD_QCLKA}, V_{DD_QCLKB}, V_{DD_QCLKC}, V_{DD_QCLKD}, V_{DD_I2C}, V_{DD_INP}

,

V_{DD_LCV}, V_{DD_LCF}, V_{DD_CPV}, V_{DD_CPF}and V_{DD_OSC}

.

V_{DDO_v}

Denominates output voltage supply pins. Range: V_{DDO_QCLKA}, V_{DDO_QCLKB}, V_{DDO_QCLKC}and V_{DDO_QCLKD}

.

status_condition

Status conditions are: LOLV (Loss of VCXO-PLL lock), LOLF (Loss of FemtoClock NG-PLL lock) and LOS (Loss of

input signal).

[...]

Index brackets describe a group associated with a logical function or a bank of outputs.

List of discrete values.

{…}

Suffix V

Suffix F

Denominates a function associated with the VCXO-PLL.

Denominates a function associated with the 2nd stage PLL (FemtoClock NG).

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8V19N478 Datasheet

Revision History

Revision Date

Description of Change

Added Figure 5 (312.5MHz Output Phase Noise)

Initial release.

May 15, 2018

May 2, 2018

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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,

without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability

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Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

68

May 15, 2018


型号：	8V19N478BDGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FemtoClock NG Jit ter At tenuator and Clock Synthesizer
文件：	总70页 (文件大小：1217K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V19N478BDGI [IDT]

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