8OSK270GILFT [IDT]
Clock Generator;
| 型号： | 8OSK270GILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总8页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATASHEET
27 MHZ FIXED AND SPREAD CLOCK GENERATOR
ICS8OSK270
Description
Features
• 14.31818 MHz crystal or clock input
The ICS8OSK270 is a low cost integrated clock
synthesizer solution replacing crystals and crystal
oscillators.
• The 27 MHz_Fixed clock output is non-spread with
<10 ppm synthesis error
The ICS8OSK270 generates a very accurate 27.00
MHz fixed clock output, and a 27.00 MHz spread
spectrum clock output from a 14.31818 MHz reference
clock or crystal input.
• 27 MHz_SS clock output with selectable spread
spectrum for EMI reduction
• Output duty cycle 45/55% (worst case)
• Advanced, low-power CMOS process
• Industrial temperature range (-40 to 85°C)
• Packaged in 8-pin MSOP (3.00 mm body)
• RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
Block Diagram
VDD
14.318 MHz
crystal or clock
input
2
S0
X1/ICLK
Crystal
27M_Fixed
Oscillator/
Clock Buffer
PLL
X2
27M_SS
External capacitors are
required with a crystal input
GND
IDT™ / ICS™ 27 MHZ FIXED AND SPREAD CLOCK GENERATOR
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Pin Assignment
8
7
6
5
VDD
S0
1
2
3
4
VDD
GND
X1/ I CLK
X2
27M_SS
27M_FI XED
Spread Spectrum Percentage Selection Table
S0
27M_SS Down
Spread
0
1
-0.5%
-1.5%
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
S0
Input
Spread Spectrum percentage select 0. See table above.Internal
Pull down resistor.
2
3
VDD
Power Connect to +3.3 V.
Input Crystal connection. Connect to14.31818 MHz crystal or clock
input.
Output Crystal connection. Connect to14.31818 MHz crystal.
X1/ICLK
4
X2
5
6
7
8
27M_FIXED Output 27 MHz fixed clock output at 3.3 V.
27M_SS
GND
Output 27 MHz spread spectrum clock output at 3.3 V.
Power Connect to ground.
VDD
Power Connect to +3.3 V.
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External Components
Decoupling Capacitor
PCB Layout Recommendations
As with any high-performance mixed-signal IC, the
ICS8OSK270 must be isolated from system power
supply noise to perform optimally.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ωresistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
Crystal Load Capacitors
3) To minimize EMI, the 33Ωseries termination resistor
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS8OSK270. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
The value (in pF) of these crystal caps should equal (C
L
-6 pF)*2. In this equation, C = crystal load capacitance
L
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2 = 20].
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS8OSK270. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs
-0.5 V to 7 V
-0.5 V to VDD+0.5 V
-0.5 V to 2.5V+0.5 V
-65 to +150° C
125°C
All Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
ESD (HBM)
260°C
2000V min.
3
MSL (Moisture Sensitivity Level)
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
° C
Ambient Operating Temperature
-40
Power Supply Voltage (measured in respect to GND)
+3.135
+3.465
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temp -40° C to +85° C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
Max.
Units
3.135
3.465
40
V
mA
V
IDD
30
No load
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
V
2
IH
V
0.8
0.4
V
IL
V
I
I
= -25 mA
= +25 mA
2.4
V
OH
OH
V
V
OL
OL
Load Capacitance,
X1 and X2
C
No internal load
capacitance
5
pF
L
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40° C to +85°C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
14.31818
Input Frequency
f
MHz
ns
IN
Output Rise Time
Output Fall Time
t
20% to 80%, Note 1
80% to 20%, Note 1
VO=VDD/2
0.7
0.7
1.0
2.2
2.2
OR
t
1.0
ns
OF
Output Impedance
Output Clock Duty Cycle
Frequency Synthesis Error
Short Term Jitter
R
20
Ω
O
VDD/2, Note 1
45
50
55
10
%
27M_FIXED
ppm
ps
Cycle-to-Cycle
100
700
1
200
800
3
Long Term Jitter
27M_FIXED, n=1000
ps
Power-up Time
t
ms
From minimum VDD to
outputs stable
PU
Note 1: Measured with a 15 pF load.
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Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches*
Min Max
8
Symbol
A
A1
A2
b
--
1.10
0.15
0.97
0.38
0.23
--
0.043
0.006
0.038
0.015
0.009
0
0
0.79
0.22
0.08
0.031
0.008
0.003
E1
E
INDEX
AREA
C
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 Basic
0.118 BASIC
0.193 BASIC
0.118 BASIC
0.0256 Basic
E
E1
e
1
2
L
0.40
0.80
0.016
0.032
D
α
0°
8°
0°
8°
aaa
-
0.10
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
Ordering Information
Part / Order Number
8OSK270GILF
Marking
Shipping Packaging
Tubes
Package
8-pin MSOP
8-pin MSOP
Temperature
-40 to +85° C
-40 to +85° C
TBD
8OSK270GILFT
Tape and Reel
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
IDT™ / ICS™ 27 MHZ FIXED AND SPREAD CLOCK GENERATOR
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Revision History
Rev. Originator
Date
Description of Change
A
B
J.Sarma
J.Sarma
03/02/06 Released from Proposal to Preliminary; added TSSOP package information.
03/08/06 Corrected the part number. The 8MSOP package part is the ICS8OSK270AGILF and the
8TSSOP package part is the ICS8OSK270GILF.
C
J.Sarma
05/04/06 Deleted the TSSOP package availability–8MSOP package only.
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+65 6 887 5505
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