89HPES4T4ZABCG [IDT]
4-Lane 4-Port PCI Express Switch; 4巷4端口PCI Express交换
| 型号： | 89HPES4T4ZABCG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 4-Lane 4-Port PCI Express Switch |
| 文件： | 总23页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
89HPES4T4
Data Sheet
Advance Information*
4-Lane 4-Port
PCI Express® Switch
®
◆
Highly Integrated Solution
– Requires no external components
Device Overview
The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates four 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
◆
◆
◆
Features
◆
High Performance PCI Express Switch
– Four 2.5 Gbps PCI Express lanes
– Four switch ports
– x1 Upstream port
– Three x1 Downstream ports
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Low latency cut-through switch architecture
– Support for Max payload sizes up to 256 bytes
– One virtual channel
– Supports PCI Power Management Interface specification (PCI-
– Eight traffic classes
PM 1.2)
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Unused SerDes are disabled.
◆
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
– Automatic lane reversal on all ports
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Legacy Support
◆
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– PCI compatible INTx emulation
– Bus locking
Block Diagram
4-Port Switch Core / 4 PCI Express Lanes
Port
Frame Buffer
Route Table
Arbitration
Scheduler
Transaction Layer
Transaction Layer
Data Link Layer
Mux / Demux
Transaction Layer
Data Link Layer
Mux / Demux
Transaction Layer
Data Link Layer
Mux / Demux
Data Link Layer
Mux / Demux
Phy
Phy
Phy
Phy
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
SerDes
SerDes
SerDes
SerDes
(Port 2)
(Port 4)
(Port 0)
(Port 3)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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September 7, 2007
© 2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
IDT 89HPES4T4 Data Sheet
◆
5 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Each pin has a selectable alternate function
◆
Packaged in a 13mm x 13mm 144-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES4T4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low
latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 1.1.
The PES4T4 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
tion layers in compliance with PCI Express Base specification Revision 1.1. The PES4T4 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.
Processor
Processor
Memory
North
Bridge
South
Bridge
x1
PES4T4
x1
x1
x1
GE
LOM
1394
GE
LOM
Figure 2 I/O Expansion Application
SMBus Interface
The PES4T4 contains an SMBus master interface. This master interface allows the default configuration register values of the PES4T4 to be over-
ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O
expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin.
Hot-Plug Interface
The PES4T4 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES4T4 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES4T4. In response to an I/O expander interrupt, the PES4T4 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
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IDT 89HPES4T4 Data Sheet
General Purpose Input/Output
The PES4T4 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alter-
nate functions may be enabled via software or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES4T4. Some of the functions listed may be multiplexed onto the same pin. The
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PE0RP[0]
PE0RN[0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0.
PE0TP[0]
PE0TN[0]
O
I
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 0.
PE2RP[0]
PE2RN[0]
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PE2TP[0]
PE2TN[0]
O
I
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
PE3RP[0]
PE3RN[0]
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PE3TP[0]
PE3TN[0]
O
I
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PE4RP[0]
PE4RN[0]
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PE4TP[0]
PE4TN[0]
O
I
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
PEREFCLKP
PEREFCLKN
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes.
Table 1 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 SMBus Interface Pins
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IDT 89HPES4T4 Data Sheet
Signal
Type
Name/Description
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[7]
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
I/O
I/O
I/O
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
Table 3 General Purpose I/O Pins
Signal
Type
Name/Description
APWRDISN
I
Auxiliary Power Disable Input. When this pin is active, it disables the
device from using auxiliary power supply.
CCLKDS
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
CCLKUS
PERSTN
I
I
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
Fundamental Reset. Assertion of this signal resets all logic inside the
PES4T4 and initiates a PCI Express fundamental reset.
Table 4 System Pins (Part 1 of 2)
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IDT 89HPES4T4 Data Sheet
Signal
Type
Name/Description
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES4T4 executes the reset procedure and remains in a reset
state with the Master SMBus active. This allows software to read and write
registers internal to the device before normal device operation begins. The
device exits the reset state when the RSTHALT bit is cleared in the
PA_SWCTL register by the SMBus master.
SWMODE[2:0]
WAKEN
I
Switch Mode. These configuration pins determine the PES4T4 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
I/O
Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through WAKEDIR bit setting in
the WAKEUPCNTL register.
Table 4 System Pins (Part 2 of 2)
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 5 Test Pins
Signal
Type
Name/Description
VDDCORE
I
I
I
Core VDD. Power supply for core logic.
I/O VDD. LVTTL I/O buffer power supply.
V
DDI/O
DDPE
V
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
VSS
I
I
PCI Express Termination Power.
Ground.
Table 6 Power and Ground Pins
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IDT 89HPES4T4 Data Sheet
Pin Characteristics
Note: Some input pads of the PES4T4 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
I/O
Internal
Resistor
Function
Pin Name
PE0RN[0]
Type
Buffer
Notes
Type
PCI Express Inter-
face
I
CML
Serial Link
PE0RP[0]
PE0TN[0]
PE0TP[0]
PE2RN[0]
PE2RP[0]
PE2TN[0]
PE2TP[0]
PE3RN[0]
PE3RP[0]
PE3TN[0]
PE3TP[0]
PE4RN[0]
PE4RP[0]
PE4TN[0]
PE4TP[0]
PEREFCLKN
PEREFCLKP
MSMBCLK
MSMBDAT
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
LVPECL/
CML
Diff. Clock
Input
Refer toTable 8
I
SMBus
I/O
I/O
I/O
I
LVTTL
STI1
STI
General Purpose I/O GPIO[9,7,2:0]
LVTTL
LVTTL
High Drive
Input
pull-up
pull-down
pull-up
System Pins
APWRDISN
CCLKDS
I
CCLKUS
I
pull-up
PERSTN
I
RSTHALT
SWMODE[2:0]
WAKEN
I
pull-down
pull-down
open-drain
pull-up
I
I/O
I
EJTAG / JTAG
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
LVTTL
STI
STI
I
pull-up
O
I
STI
STI
pull-up
pull-up
I
Table 7 Pin Characteristics
1.
Schmitt Trigger Input (STI).
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IDT 89HPES4T4 Data Sheet
Logic Diagram — PES4T4
PCI Express
Switch
SerDes Output
Port 0
PEREFCLKP
Reference
Clocks
PE0TP[0]
PE0TN[0]
PEREFCLKN
PCI Express
PE0RP[0]
Switch
SerDes Input
PCI Express
Switch
SerDes Output
Port 2
PE2TP[0]
PE2TN[0]
PE0RN[0]
Port 0
PCI Express
PE2RP[0]
Switch
SerDes Input
PE2RN[0]
PCI Express
Switch
SerDes Output
Port 2
PE3TP[0]
PE3TN[0]
Port 3
PCI Express
PE3RP[0]
Switch
SerDes Input
PE3RN[0]
Port 3
PCI Express
Switch
SerDes Output
Port 4
PE4TP[0]
PE4TN[0]
PES4T4
PCI Express
Switch
PE4RP[0]
SerDes Input
Port 4
5
PE4RN[0]
General Purpose
I/O
GPIO[9,7,2:0]
JTAG_TCK
JTAG_TDI
Master
SMBus Interface
MSMBCLK
MSMBDAT
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
CCLKDS
CCLKUS
RSTHALT
System
Pins
V
V
V
V
CORE
DD
I/O
DD
PERSTN
SWMODE[2:0]
WAKEN
PE
DD
3
APE
DD
Power/Ground
V
V
SS
APWRDISN
PE
TT
Figure 3 PES4T4 Logic Diagram
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IDT 89HPES4T4 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
Parameter
Description
Min
Typical
Max
Unit
PEREFCLK
RefclkFREQ
Input reference clock frequency range
Duty cycle of input clock
100
40
1251
60
MHz
%
2
RefclkDC
50
TR, TF
VSW
Rise/Fall time of input clocks
Differential input voltage swing4
Input clock jitter (cycle-to-cycle)
0.2*RCUI
1.6
RCUI3
0.6
V
Tjitter
125
ps
Table 8 Input Clock Requirements
1.
The input clock frequency is 100 MHz.
2.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
AC coupling required.
3.
4.
AC Timing Characteristics
Parameter
Description
Min
Typical
Max
Units
PCIe Transmit
TTX-RISE, TTX-FALL Rise / Fall time of TxP, TxN outputs
80
1101
400.12
0.252
ps
ps
UI
UI
UI
UI
Unit Interval
399.88
400
TTX-MAX-JITTER
TTX-EYE
Transmitter Total Jitter (peak-to-peak)
Minimum Tx Eye Width (1 - TTX-MAX-JITTER
)
0.75
TTX-EYE-MEDIAN-to- Maximum time between the jitter median and maximum
0.15
deviation from the median
MAX-JITTER
LTLAT-10
Transmitter data latency (for n=10)
Transmitter data latency (for n=20)
Transmitter data skew between any 2 lanes
9
9
11
11
bits
bits
ps
LTLAT-20
TTX-SKEW
500
4
1300
6
TTX-IDLE-SET-TO-
Maximum time to transition to a valid electrical idle after
sending an Electrical Idle ordered set
ns
IDLE
TEIExit
Time to exit Electrical Idle (L0s) state into L0
12
30
16
80
ns
ns
TBTEn
Time from asserting Beacon TxEn to beacon being trans-
mitted on the lane
TRxDetectEn
TRxDetect
Pulse width of RxDetectEn input
9.8
10
1
10.2
2
ns
ns
RxDetectEn falling edge to RxDetect delay
PCIe Receive
LRLAT-10
Recover data latency for n=10
Recover data latency for n=20
28
49
29
60
bits
bits
LRLAT-20
Table 9 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES4T4 Data Sheet
Parameter
Description
Min
Typical
Max
Units
TRX-SKEW
TBDDly
Receiver data skew between any 2 lanes
Beacon-Activity on channel to detection of Beacon3
20
200
20
ns
µs
ns
TRX-IDLE_ENTER
Delay from detection of Electrical Idle condition on the
channel to assertion of TxIdleDetect output
10
5
TRX-IDLE_EXIT
Delay from detection of L0s to L0 transition to de-asser-
tion of TxIdleDetect output
10
ns
TRX-MAX-JITTER
TRX-EYE
Receiver total jitter tolerance
Minimum Receiver Eye Width
0.65
UI
UI
UI
0.35
TRX-EYE-MEDIAN-to- Maximum time between jitter median and max deviation
0.325
from median
MAX JITTER
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
As measured between 20% and 80% points. Will depend on package characteristics.
1.
2.
3.
Measured using PCI Express Compliance Pattern.
This is a function of beacon frequency.
Timing
Reference
Signal
GPIO
Symbol
Min Max Unit
Diagram
Edge
Reference
GPIO[9,7,2:0]1
Tpw_13b2
None
50
—
ns
See Figure 4.
Table 10 GPIO AC Timing Characteristics
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
1.
2.
The values for this symbol were determined by calculation, not by testing.
EXTCLK
Tdo_13a
Tdo_13a
GPIO (synchronous output)
GPIO (asynchronous input)
Tpw_13b
Figure 4 GPIO AC Timing Waveform
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IDT 89HPES4T4 Data Sheet
Timing
Diagram
Reference
Reference
Edge
Signal
Symbol
Min
Max
Unit
JTAG
JTAG_TCK
Tper_16a
none
25.0
10.0
50.0
25.0
ns
ns
See Figure 5.
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
Tsu_16b
Thld_16b
Tdo_16c
Tdz_16c2
Tpw_16d2
JTAG_TCK rising
JTAG_TCK falling
none
2.4
1.0
—
—
—
ns
ns
ns
ns
ns
JTAG_TDO
11.3
11.3
—
—
JTAG_TRST_N
25.0
Table 11 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
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IDT 89HPES4T4 Data Sheet
Recommended Operating Supply Voltages
Symbol
Parameter
Internal logic supply
Minimum
Typical
Maximum
Unit
VDDCORE
0.9
3.135
0.9
1.0
3.3
1.0
1.0
1.5
1.1
3.465
1.1
V
V
V
V
V
V
DDI/O
DDPE
I/O supply except for SerDes LVPECL/CML
PCI Express Digital Power
V
VDDAPE
VTTPE
PCI Express Analog Power
0.9
1.1
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.575
VSS
Common ground
0
0
0
V
Table 12 PES4T4 Operating Voltages
Power-Up/Power-Down Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES4T4, the power-up sequence must be as follows:
1.
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. TTPE — 1.5V
VDDI/O — 3.3V
V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels.
The power-down sequence must be in the reverse order of the power-up sequence.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Table 13 PES4T4 Operating Temperatures
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IDT 89HPES4T4 Data Sheet
Power Consumption
Parameter
Typ. Max. Unit
Conditions
Tambient = 25oC
IDDI/O
tbd
tbd
mA
Max. values use the maximum volt-
ages listed in Table 12. Typical val-
ues use the typical voltages listed
in that table.
IDDCore
Normal mode
Standby mode1
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
—
mA
mA
mA
mA
mA
W
IDDPE,
tbd
tbd
tbd
tbd
—
IDD APE
ITTPE
Power
Dissipation
Normal mode
Standby mode1
W
Table 14 PES4T4 Power Consumption
1.
All ports in D1 state.
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IDT 89HPES4T4 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 12.
Note: See Table 7, Pin Characteristics, for a complete I/O listing.
I/O Type Parameter
Description
Min1
Typ1
Max1 Unit
Conditions
Serial Link
PCIe Transmit
VTX-DIFFp-p
Differential peak-to-peak output voltage
800
-3
1200
-4
mV
dB
V
VTX-DE-RATIO De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
-0.1
1
3.7
20
VTX-CM-ACP
RMS AC peak common mode output volt-
age
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
25
mV
mV
active-idle-delta
VTX-CM-DC-line- Abs delta of DC common mode voltage
between D+ and D-
delta
VTX-Idle-DiffP
Electrical idle diff peak output
20
mV
mV
dB
dB
Ω
VTX-RCV-Detect Voltage change during receiver detection
600
RLTX-DIFF
RLTX-CM
ZTX-DEFF-DC
ZOSE
Transmitter Differential Return loss
Transmitter Common Mode Return loss
DC Differential TX impedance
12
6
80
40
505
100
50
120
60
Single ended TX Impedance
Ω
Transmitter Eye TX Eye Height (De-emphasized bits)
Diagram
650
mV
Transmitter Eye TX Eye Height (Transition bits)
Diagram
800
175
950
mV
PCIe Receive
VRX-DIFFp-p
VRX-CM-AC
Differential input voltage (peak-to-peak)
1200
150
mV
mV
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
RLRX-CM
Receiver Differential Return Loss
Receiver Common Mode Return Loss
Differential input impedance (DC)
15
6
dB
dB
Ω
ZRX-DIFF-DC
80
100
50
120
60
ZRX-COMM-DC Single-ended input impedance
40
Ω
ZRX-COMM-HIGH- Powered down input common mode
200k
350k
Ω
impedance (DC)
Z-DC
VRX-IDLE-DET- Electrical idle detect threshold
65
175
mV
pF
DIFFp-p
PCIe REFCLK
CIN
Input Capacitance
1.5
—
Table 15 DC Electrical Characteristics (Part 1 of 2)
13 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
I/O Type Parameter
Description
Min1
Typ1
Max1 Unit
Conditions
Other I/Os
LOW Drive
Output
IOL
IOH
IOL
IOH
VIL
VIH
—
—
2.5
-5.5
12.0
-20.0
—
—
—
mA
mA
mA
mA
V
VOL = 0.4v
VOH = 1.5V
VOL = 0.4v
VOH = 1.5V
—
High Drive
Output
—
—
—
—
Schmitt Trig-
ger Input
(STI)
-0.3
2.0
0.8
—
VDDI/O
+ 0.5
V
—
Input
VIL
VIH
-0.3
2.0
—
—
0.8
V
V
—
—
VDDI/O
+ 0.5
Capacitance
Leakage
CIN
—
—
—
—
—
—
8.5
pF
μA
μA
—
Inputs
+ 10
+ 10
VDDI/O (max)
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Table 15 DC Electrical Characteristics (Part 2 of 2)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
1.
14 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Package Pinout — 144-BGA Signal Pinout for PES4T4
The following table lists the pin numbers and signal names for the PES4T4 device.
Pin
Function
Alt Pin
Function
VDDCORE
Alt Pin
Function
VDDCORE
VDDI/O
DDI/O
Alt Pin
Function
Alt
A1
VSS
DDI/O
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
F9
J7
J8
J9
VSS
A2
V
VSS
F10
F11
F12
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
VDDCORE
VSS
A3
APWRDISN
VTTPE
JTAG_TDO
MSMBCLK
VDDCORE
VSS
V
A4
GPIO_01
VSS
1
1
1
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
VSS
A5
VTTPE
VDDI/O
GPIO_09
VSS
A6
PE0TP00
JTAG_TRST_N
VSS
1
A7
V
DDPE
PE0RP00
DDI/O
VSS
A8
VSS
VDDCORE
VSS
VDDCORE
VDDI/O
VDDCORE
VDDPE
VSS
A9
V
VDDCORE
VSS
A10
A11
A12
B1
SWMODE_0
SWMODE_1
VSS
VDDCORE
VSS
VSS
VSS
VDDCORE
VSS
V
DDCORE
PERSTN
RSTHALT
JTAG_TDI
MSMBDAT
VDDI/O
VDDPE
VSS
B2
WAKEN
CCLKUS
VDDPE
VDDCORE
B3
VSS
VDDCORE
VDDI/O
VSS
B4
E2
GPIO_02
PEREFCLKP
VDDI/O
VDDAPE
VSS
B5
V
DDPE
PE0TN00
DDPE
E3
B6
E4
V
DDCORE
H2
VSS
B7
V
E5
VSS
H3
PE2RN00
VSS
B8
PE0RN00
CCLKDS
SWMODE_2
VSS
E6
V
DDCORE
H4
L2
B9
E7
VSS
H5
VSS
L3
PE2TP00
VSS
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
E8
VSS
H6
VSS
L4
E9
VSS
H7
VDDCORE
VSS
L5
PE3TN00
VDDAPE
PE3RN00
VTTPE
PE4RP00
VSS
VSS
E10
E11
E12
F1
VDDCORE
VSS
H8
L6
JTAG_TMS
VSS
H9
VSS
L7
GPIO_00
JTAG_TCK
VDDI/O
VDDCORE
VSS
1
H10
H11
H12
J1
VDDCORE
VSS
L8
VSS
L9
V
V
V
DDCORE
DDAPE
DDAPE
F2
GPIO_07
PEREFCLKN
VSS
L10
L11
L12
M1
M2
M3
M4
F3
PE4TN00
VDDCORE
PE2RP00
VSS
F4
J2
VSS
F5
VDDCORE
VSS
J3
VSS
V
DDCORE
F6
J4
VSS
VDDCORE
VSS
F7
VDDCORE
VSS
J5
VSS
PE2TN00
VTTPE
F8
J6
VDDCORE
Table 16 PES4T4 144-pin Signal Pin-Out (Part 1 of 2)
15 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Pin
Function
PE3TP00
VSS
Alt Pin
Function
PE3RP00
VDDAPE
Alt Pin
Function
PE4RN00
VSS
Alt Pin
Function
PE4TP00
VSS
Alt
M5
M6
M7
M8
M9
M11
M12
M10
Table 16 PES4T4 144-pin Signal Pin-Out (Part 2 of 2)
Alternate Signal Functions
Pin
GPIO
Alternate
E12
F12
G12
H12
J12
GPIO_00
GPIO_01
GPIO_02
GPIO_07
GPIO_09
P2RSTN
P4RSTN
IOEXPINTN0
GPEN
P3RSTN
Table 17 PES4T4 Alternate Signal Functions
Power Pins
VDDCore
VDDCore
VDDI/O
VDDPE
VDDAPE
VTTPE
B1
C4
C8
C9
C11
D3
D7
E4
E6
E10
F3
F9
G4
G6
G8
G10
H7
H10
J6
A2
A9
A7
B4
B5
B7
K5
K7
C5
C6
H3
L6
A4
A5
L8
E3
F2
M4
F10
F11
H2
M8
J11
K3
J8
K2
K10
K4
F5
K9
F7
L12
Table 18 PES4T4 Power Pins
16 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Ground Pins
Vss
Vss
Vss
Vss
A1
A12
B11
B12
C2
D10
E5
E7
E8
E9
E11
F4
G11
H4
H5
H6
H8
H9
H11
J2
K1
K6
K8
K11
K12
L2
C3
C7
L4
C10
C12
D4
F6
L10
M2
M6
M10
M12
F8
J3
G1
G3
G5
G7
G9
J4
D5
J5
D6
J7
D8
J9
D9
J10
Table 19 PES4T4 Ground Pins
Signals Listed Alphabetically
Signal Name I/O Type
Location
Signal Category
APWRDISN
CCLKDS
I
I
A3
B9
System
CCLKUS
I
B3
GPIO_00
I/O
I/O
I/O
I/O
I/O
I
E12
F12
G12
H12
J12
F1
General Purpose Input/Output
GPIO_01
GPIO_02
GPIO_07
GPIO_09
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG-TMS
JTAG-TRST_N
MSMBCLK
MSMBDAT
JTAG
I
E1
I
D1
O
I
C1
G2
D2
I/O
I/O
SMBus
E2
Table 20 89PES4T4 Alphabetical Signal List (Part 1 of 2)
17 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Signal Name I/O Type
Location
Signal Category
PE0RN00
I
I
B8
A8
PCI Express
PE0RP00
PE0TN00
PE0TP00
PE2RN00
PE2RP00
PE2TN00
PE2TP00
PE3RN00
PE3RP00
PE3TN00
PE3TP00
PE4RN00
PE4RP00
PE4TN00
PE4TP00
PEREFCLKN
PEREFCLKP
PERSTN
O
O
I
B6
A6
L1
I
M1
M3
L3
O
O
I
L7
I
M7
L5
O
O
I
M5
M9
L9
I
O
O
I
L11
M11
J1
I
H1
I
D11
D12
A10
A11
B10
B2
System
System
RSTHALT
SWMODE_0
SWMODE_1
SWMODE_2
WAKEN
I
I
I
I
I/O
VDDCORE,
See Table 18 for a listing of power pins.
VDDAPE, VDDI/O,
VDDPE, VTTPE
VSS
See Table 19 for a listing of ground pins.
Table 20 89PES4T4 Alphabetical Signal List (Part 2 of 2)
18 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
PES4T4 Pinout — Top View
1
2
3
4
5
6
7
8
9
10
11
12
A
A
X
X
B
C
D
B
C
D
E
F
E
F
G
H
J
G
H
J
K
L
K
L
X
M
M
X
4
1
2
3
5
6
7
8
9
10
11
12
VDDCore (Power)
VDDI/O (Power)
Signals
VTTPE (Power)
VDDPE (Power)
VDDAPE (Power)
Vss (Ground)
x
19 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
PES4T4 Package Drawing — 144-Pin BC144/BCG144
20 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
PES4T4 Package Drawing — Page Two
21 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Revision History
August 16, 2007: Initial publication of advanced data sheet.
September 7, 2007: Added Power-Up/Power Down Sequence.
22 of 23
September 7, 2007
IDT 89HPES4T4 Data Sheet
Ordering Information
Legend
A = Alpha Character
N = Numeric Character
A
AAA
A
NNAN
AA
AA
NN
Product
Family
Operating
Voltage
Device
Family
Temp Range
Package
Product
Detail
Device
Revision
Commercial Temperature
(0°C to +70°C Ambient)
Blank
BC144 144-ball CABGA
BC
BCG144 144-ball CABGA, Green
BCG
ZA revision
ZA
4-lane, 4-port
4T4
PCI Express Switch
PES
H
1.0V +/- 0.1V Core Voltage
Serial Switching Product
89
Valid Combinations
89HPES4T4ZABC
89HPES4T4ZABCG
144-pin BC144 package, Commercial Temperature
144-pin Green BC144 package, Commercial Temperature
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23 of 23
September 7, 2007
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