87946AYI [IDT]
Low Skew Clock Driver, 87946 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | 87946AYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 87946 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总9页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷1, ÷2
LVCMOS CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87946I is a low skew, ÷1, ÷2 LVCMOS
• 10 single ended LVCMOS outputs, 7Ω typical output
,&6
Clock Generator and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87946I has two select-
able single ended clock inputs. The single ended
impedance
HiPerClockS™
• Selectable CLK0 and CLK1 LVCMOS clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
clock inputs accept LVCMOS or LVTTL input levels. The low
impedance LVCMOS outputs are designed to drive 50Ω series
or parallel terminated transmission lines. The effective fanout
can be increased from 10 to 20 by utilizing the ability of the
outputs to drive two series terminated lines.
• Maximum input/output frequency: 150MHz
• Output skew: 350ps (maximum)
• 3.3V input, 3.3V outputs
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC946
The ICS87946I is characterized at 3.3V core/3.3V output. Guar-
anteed output and part-to-part skew characteristics make the
ICS87946I ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
0
1
CLK0
0
1
÷1
÷2
QA0:QA2
QB0:QB2
QC0:QC3
CLK1
32 31 30 29 28 27 26 25
CLK_SEL
VDD
DIV_SELA
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
0
1
CLK0
CLK1
ICS87946I
DIV_SELB
DIV_SELA
DIV_SELB
DIV_SELC
0
1
GND
DIV_SELC
MR/nOE
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
87946AYI
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REV. B OCTOBER 22, 2002
1
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷1, ÷2
LVCMOS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
1
CLK_SEL
Input
2
VDD
Power
Input
Positive supply pins.
3, 4
CLK0, CLK1
Pullup
LVCMOS / LVTTL clock inputs.
Controls frequency division for Bank A outputs.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank C outputs.
LVCMOS / LVTTL interface levels.
5
6
7
DIV_SELA
DIV_SELB
DIV_SELC
Input
Input
Input
Pulldown
Pulldown
Pulldown
8, 11, 15,
20, 24, 27,
31
GND
VDDC
Power
Power supply ground.
9, 13, 17
Power
Output
Power
Positive supply pins for Bank C outputs.
10, 12,
14, 16
QC0, QC1,
QC2, QC3
Bank C outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
18, 22
VDDB
Positive supply pins for Bank B outputs.
Bank B outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
19, 21, 23 QB2, QB1, QB0 Output
25, 29
VDDA
Power
Positive supply pins for Bank A outputs.
26, 28,
30
Bank A outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
QA2, QA1, QA0 Output
Master reset and output enable When LOW, output drivers are
32
MR/nOE
Input
Pulldown enabled. When HIGH, output drivers are in HiZ and dividers are
reset. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
Power Dissipation Capacitance (per output);
NOTE 1
CPD
VDD, VDDx = 3.6V
25
7
pF
ROUT
Output Impedance
Ω
NOTE 1: VDDx denotes VDDA, VDDB, VDDC
.
TABLE 3. FUNCTION TABLE
Inputs
Outputs
QB0:QB2
Hi Z
MR/nOE
DIV_SELA
DIV_SELB
DIV_SELC
QA0:QA2
Hi Z
QC0:QC3
1
0
0
0
0
0
0
X
0
X
X
X
0
X
X
X
X
X
0
Hi Z
Active
Active
Active
Active
fIN/1
fIN/1
Active
Active
fIN/1
1
fIN/2
X
X
X
X
Active
Active
Active
Active
1
fIN/2
X
X
Active
Active
1
fIN/2
87946AYI
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REV. B OCTOBER 22, 2002
2
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷1, ÷2
LVCMOS CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, VDD
-0.5V to VDD + 0.5 V
-0.5V to VDDx + 0.5V
Outputs, VDDx
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
3.0
3.0
3.3
3.3
3.6
3.6
85
V
V
VDDx
IDD
mA
NOTE 1: VDDx denotes VDDA, VDDB, VDDC
.
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDX = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
2
VDD + 0.3
V
V
VIH
VIL
IIH
Input High Voltage
CLK0, CLK1
2
VDD + 0.3
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
-0.3
-0.3
0.8
V
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
1.3
V
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
VDD = V = 3.6V
120
5
µA
µA
µA
IN
CLK0, CLK1
VDD = V = 3.6V
IN
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
VDD = 3.6V, V = 0V
-5
IN
IIL
CLK0, CLK1
V
DD = 3.6V, V = 0V
-120
2.5
µA
V
IN
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
0.4
V
87946AYI
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REV. B OCTOBER 22, 2002
3
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷1, ÷2
LVCMOS CLOCK GENERATOR
TABLE 5. AC CHARACTERISTICS, VDD = VDDX = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Input Frequency
150
2
MHz
ns
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
12.0
11.5
tpHL
2
ns
tsk(o)
Output Skew; NOTE 2, 6
350
350
450
4.5
1.0
1.0
11
ps
ps
ps
ns
ns
ns
ns
ns
f
MAX < 100MHz
Multiple Frequency Skew;
NOTE 3, 6
tsk(w)
fMAX > 100MHz
tsk(pp)
Part-to-Part Skew; NOTE 4, 6
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
tR
0.8V to 2.0V
0.8V to 2.0V
0.1
0.1
tF
tEN
tDIS
11
NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 3: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE: VDDx denotes VDDA, VDDB, VDDC
.
87946AYI
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REV. B OCTOBER 22, 2002
4
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷1, ÷2
LVCMOS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VDD, VDDx = 1.65V±0.15V
VDD
2
SCOPE
x
Qx
Qy
Qx
LVCMOS
VDD
2
x
tsk(o)
GND = -1.65V±0.15V
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
2.0V
2.0V
x
PART 1
Qx
VSWING
0.8V
2
0.8V
Clock Outputs
VDD
2
t
t
PART 2
Qy
x
F
R
tsk(pp)
OUTPUT RISE/FALL TIME
PART-TO-PART SKEW
VDD
CLK0,
CLK1
2
VDD
x
2
QAx, QBx,
QCx, QDx
t
PD
Propagation Delay
87946AYI
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REV. B OCTOBER 22, 2002
5
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷1, ÷2
LVCMOS CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87946I is: 1204
87946AYI
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REV. B OCTOBER 22, 2002
6
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷1, ÷2
LVCMOS CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
87946AYI
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REV. B OCTOBER 22, 2002
7
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷1, ÷2
LVCMOS CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87946AYI
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS87946AYI
ICS87946AYI
ICS87946AYIT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
87946AYI
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REV. B OCTOBER 22, 2002
8
ICS87946I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷1, ÷2
LVCMOS CLOCK GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
1
2
6
In Features section added Max. Input/Output Frequency bullet.
Revised MR/nOE description.
A
T1
T5
08/14/02
10/22/02
Revised Output Rise & Fall Time Diagram.
AC Characteristics table - changed
(CLK0, CLK1)) tpLH from 6.0ns max. to 12.0ns max., deleted typical value.
B
4
(CLK0, CLK1)) tpHL from 6.0ns max. to 11.5ns max. , deleted typical value.
87946AYI
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REV. B OCTOBER 22, 2002
9
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