8547AY [IDT]
Clock Driver;
| 型号： | 8547AY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总12页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8547
Integrated
Circuit
Systems, Incꢀ
H
EX, LOW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-LVDS CLOCK
BUFFERS
G
ENERAL
D
ESCRIPTION
F
EATURES
The ICS8547 is a Hex low skew, high perfor- • 12 LVDS outputs
mance 1-to-2 Differential-to-LVDS Clock Buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. Utilizing
Low Voltage Differential Signaling (LVDS) the
,&6
• Selectable CLKx, nCLKx inputs
HiPerClockS™
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
ICS8547 provides a low power, low noise, point-to-point solu-
tion for distributing clock signals over controlled impedances
of 100Ω. The ICS8547 has six selectable clock inputs. The
CLKx, nCLKx pairs can accept any differential input levels
and translates them to 3.3V LVDS output levels.
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS
Guaranteed output and part-to-part skew specifications make
the ICS8547 ideal for those applications demanding well
defined performance and repeatability.
with resistor bias on nCLKx input
• Output skew: 250ps (maximum)
• Bank skew: 15ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.8ns (maximum)
• 3.3V operating supply
• 0°C to 85°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK
DIAGRAM
P
IN
ASSIGNMENT
Q0A
nQ0A
CLK0
nCLK0
Q0B
nQ0B
48 47 46 45 44 43 42 41 40 39 38 37
Q4A
nQ4A
nQ4B
Q4B
1
36
Q2A
Q1A
nQ1A
2
35
34
33
32
31
30
29
28
27
26
25
nQ2A
nQ2B
Q2B
CLK1
nCLK1
3
Q1B
nQ1B
4
nCLK4
CLK4
CLK5
nCLK5
Q5B
5
nCLK2
CLK2
CLK1
nCLK1
Q1B
Q2A
6
nQ2A
CLK2
nCLK2
ICS8547
7
Q2B
nQ2B
8
9
nQ5B
nQ5A
Q5A
10
11
12
nQ1B
nQ1A
Q1A
Q3A
nQ3A
CLK3
nCLK3
Q3B
nQ3B
13 14 15 16 17 18 19 20 21 22 23 24
Q4A
nQ4A
CLK4
nCLK4
Q4B
nQ4B
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Q5A
nQ5A
CLK5
nCLK5
Top View
Q5B
nQ5B
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REV. A FEBRUARY 4, 2003
1
ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q4A, nQ4A
nQ4B, Q4B
nCLK4
Type
Description
1, 2
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
3, 4
5
Pullup
6
CLK4
Input
Pulldown Non-inverting differential clock input.
Pulldown Non-inverting differential clock input.
7
8
CLK5
Input
nCLK5
Input
Pullup
Inverting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
9, 10
Q5B, nQ5B
nQ5A, Q5A
VDDO
Output
Output
Power
Power
Power
Input
11, 12
13, 24, 37, 48
14, 23, 38, 47
15, 22, 39, 46
16
GND
Power supply ground.
VDD
Core supply pins.
CLK0
Pulldown Non-inverting differential clock input.
17
nCLK0
Input
Pullup
Inverting differential clock input.
18, 19
20, 21
25, 26
27, 28
29
Q0A, nQ0A
nQ0B, Q0B
Q1A, nQ1A
nQ1B, Q1B
nCLK1
Output
Output
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
Pullup
30
CLK1
Input
Pulldown Non-inverting differential clock input.
Pulldown Non-inverting differential clock input.
31
CLK2
Input
32
nCLK2
Input
Pullup
Inverting differential clock input.
33, 34
35, 36
40, 41
42, 43
44
Q2B, nQ2B
nQ2A, Q2A
Q3B, nQ3B
nQ3A, Q3A
nCLK3
Output
Output
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
Pullup
45
CLK3
Input
Pulldown Non-inverting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
RPULLUP
51
51
1
RPULLDOWN Input Pulldown Resistor
CPD Capacitance Power Dissipation
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
nQ0A:nQ5A,
Input to Output Mode
Polarity
Q0A:Q5A,
Q0B:Q5B
CLKx
nCLKx
nQ5B:nQ5B
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
LOW
0
Biased; NOTE 1
HIGH
1
Biased; NOTE 1
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.465
3.465
22
V
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
V
mA
mA
IDDO
18
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Input High Current
Test Conditions
Minimum
Typical Maximum Units
CLKx
V
IN = VDD = 3.465V
VIN = VDD = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
IIH
nCLKx
CLKx
V
-5
IIL
Input Low Current
nCLKx
VDD = 3.465V, VIN = 0V
-150
0.15
0.5
VPP
Peak-to-Peak Voltage
1.3
VCMR
Common Mode Voltage Range
VDD - 0.85
V
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
175
275
375
50
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.0
-1
1.3
1.6
50
∆ VOS
IOFF
VOS Magnitude Change
Power Off Leakage
mV
µA
mA
mA
+1
IOSD
Differential Output Short Circuit Current
Output Short Circuit Current
-5.5
-12
IOS/IOSB
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
1.8
250
15
MHz
ns
ps
ps
ps
ps
%
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew; NOTE 3, 5
IJ 500MHz
1.2
1.5
tsk(o)
tsk(b)
tsk(pp)
tR / tF
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
500
550
55
20% to 80%
IJ 300MHz
250
45
50
odc
Output Duty Cycle
300MHz < IJ 500MHz
40
60
%
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured from at the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V
nCLKx
CLKx
SCOPE
Qx
VPP
VCMR
Cross Points
3.3V±5%
POWER SUPPLY
+
LVDS
Float GND
-
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQx
Qx
PART 1
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
QxA,
nQxA
80%
80%
QxA,
nQxA
VOD
20%
20%
QxB,
Clock Outputs
nQxB
t
t
R
F
QxB,
nQxB
tsk(b)
BANK SKEW
OUTPUT RISE/FALL TIME
nQxA, nQxB
nCLKx
CLKx
QxA, QxB
Pulse Width
tPERIOD
nQxA, nQxB
tPW
odc =
QxA, QxB
tPERIOD
tPD
odc & tPERIOD
PROPAGATION DELAY
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
VDD
VDD
➤
out
out
out
➤
LVDS
DC Input
100
V
OD/∆ VOD
DC Input
LVDS
➤
out
VOS/∆ VOS
➤
VOD / DVOD SETUP
VOS / DVOS SETUP
VDD
VDD
out
out
out
IOS
DC Input
IOSD
LVDS
DC Input
LVDS
IOSB
out
IOS SETUP
IOSD SETUP
LVDS
VDD
IOFF
IOFF SETUP
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REV. A FEBRUARY 4, 2003
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
R2
1K
0.1uF
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver com-
and other differential signals. Both VSWING and VOH must meet the ponent to confirm the driver termination requirements. For ex-
VPP and VCMR input requirements. Figures 2 to 5 show interface ample in Figure 2, the input termination applies for ICS
examples for the HiPerClockS CLK/nCLK input driven by the most HiPerClockS LVHSTLdrivers. If you are using an LVHSTLdriver
common driver types. The input interfaces suggested here are from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 2. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
R3
R4
Zo = 50 Ohm
Zo = 50 Ohm
125
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
nCLK
nCLK
HiPerClockS
Input
HiPerClockS
Input
LVPECL
R1
84
R2
84
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A FEBRUARY 4, 2003
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
LVDS DRIVER TERMINATION
Figure 6 shows typical termination for LVDS driver in character-
istic impedance of 100Ω differential (50Ω single) transmission
line environment. For buffer with multiple LDVS driver, it is rec-
ommended to terminate the unused outputs.
3.3V
3.3V
Zo = 50
LVDS_Driver
+
R1
100
-
Zo = 50
FIGURE 6. TYPICAL LVDS DRIVER TERMINATION
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8547 is: 1117
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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REV. A FEBRUARY 4, 2003
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ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Integrated
Circuit
Systems, Incꢀ
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8547AY
Marking
ICS8547AY
ICS8547AY
Package
48 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 85°C
0°C to 85°C
ICS8547AYT
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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12
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