853S54I-01 [IDT]
Dual 2:1, 1:2 Differential-to-LVPECL/ ECL Multiplexer;
| 型号： | 853S54I-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual 2:1, 1:2 Differential-to-LVPECL/ ECL Multiplexer |
| 文件： | 总20页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 2:1, 1:2 Differential-to-LVPECL/
ECL Multiplexer
853S54I-01
Datasheet
General Description
Features
The 853S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device
may be useful for multiplexing multi-rate Ethernet PHYs which
have 100Mbit and 1000Mbit transmit/receive pairs onto an optical
SFP module which has a single transmit/receive pair. A 3RD mode
allows loop back testing and allows the output of a PHY transmit
pair to be routed to the PHY input pair. For examples, please refer
to the Application Block diagrams on pages 2-3 of the data sheet.
• Dual 2:1, 1:2 MUX
• Three LVPECL output pairs
• Three differential clock inputs can accept: LVPECL, LVDS, CML
• Loopback test mode available
• Maximum output frequency: 2.5GHz
• Propagation delay: 550ps (maximum)
• Part-to-part skew: 275ps (maximum)
The 853S54I-01 is optimized for applications requiring very high
performance and has a maximum operating frequency in 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
• Additive phase jitter, RMS: 27fs (typical)
• LVPECL mode operating voltage supply range:
V
CC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
CC = 0V, VEE = -3.465V to -2.375V
V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
SELB
16 15 14 13
1
2
3
12
QA0
nQA0
QA1
INA0
Pulldown
11
10
nINA0
INA1
INA0
Pullup/Pulldown
nINA0
nQA1
4
nINA1
9
5
6
7
8
Pulldown
INB
LOOP 0
0
Pullup/Pulldown
nINB
QA0
nQA0
853S54I-01
1
16-Lead VFQFN
0
QB
3mm x 3mm x 0.925mm
package body
K Package
Pulldown
INA1
nQB
1
Pullup/Pulldown
nINA1
Top View
LOOP 1
QA1
nQA1
SELA
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853S54I-01 Datasheet
Table 1. Pin Descriptions
Number
1, 2
Name
QA0, nQA0
QA1, nQA1
INB
Type
Description
Output
Output
Input
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
3, 4
5
Pulldown Non-inverting LVPECL/ECL differential clock input.
Pullup/
Pulldown
6
nINB
Input
Inverting LVPECL differential clock input. VCC/2 default when left floating.
7
8
SELB
VEE
Input
Pulldown Select pin for QB output. See Table 3. LVCMOS/LVTTL interface levels.
Negative supply pin.
Power
Pullup/
9
nINA1
INA1
Input
Input
Input
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
10
11
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
nINA0
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
12
13
INA0
VCC
Input
Power
Input
Pulldown Non-inverting differential clock input.
Power supply pin.
14
SELA
Pulldown Select pin for QAx outputs. See Table 3. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL/ECL interface levels.
15, 16
nQB, QB
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
37.5
Maximum
Units
k
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
37.5
k
Function Tables
Table 3. Control Input Function Table
Control Inputs
SELA
SELB
Mode
0
1
0
1
0
0
1
1
LOOP 0 selected
LOOP 1 selected
Loopback mode: LOOP 0
Loopback mode: LOOP 1
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853S54I-01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
4.6V (LVPECL mode, VEE = 0V)
-4.6V (ECL mode, VCC = 0V)
-0.5V to VCC + 0.5V
0.5V to VEE – 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Operating Temperature Range, TA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
Package Thermal Impedance, JA, (Junction-to-Ambient)
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = 2.375V TO 3.465V, V = 0V OR V = 0V, V = -3.465V TO -2.375V,
CC
EE
CC
EE
T = -40°C to 85°C
A
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
Maximum
3.465
2.625
45
Units
V
3.3
2.5
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V = 2.375V TO 3.465V, V = 0V OR V = 0V, V = -3.465V TO
CC
EE
CC
EE
-2.375V,
T = 40°C to 85°C
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VCC = 3.465V
VCC = 2.625V
2.2
1.7
0
VCC + 0.3
VCC + 0.3
0.8
VIH
Input High Voltage
Input Low Voltage
V
V
CC = 3.465V
CC = 2.625V
V
VIL
V
0
0.7
V
IIH
IIL
Input High Current
Input Low Current
SELA, SELB
SELA, SELB
VCC = VIN = 3.465V or 2.625V
VCC = 2.625V, VIN = 0V
150
µA
µA
-150
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853S54I-01 Datasheet
Table 4C. LVPECL DC Characteristics, V = 3.3V, V = 0V, T = -40°C to 85°C
CC
EE
A
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Min
Max
-0.87
Min
-1.07
Max
-0.8
Min
-1.01
Max
-0.8
Units
Output
V
-1.02
V
V
V
V
V
V
-1.00
V
V
V
V
V
-0.9
V
V
CC
CC
CC
CC
CC
CC
CC
CC
V
V
V
V
High Voltage;
NOTE 1
V
V
-1.125
-1.895
V
OH
OL
CC
5
5
5
5
80
5
7
85
Output
Low Voltage;
NOTE 1
V
-1.75
-1.87
-1.6
V
-1.7
-1.6
CC
7
CC
CC
CC
CC
-1.62
-1.78
-1.86
CC
V
mV
V
CC
CC
CC
5
5
85
65
Peak-to-Peak
Input Voltage;
NOTE 2
150
1.2
800
1200
150
800
1200
150
800
1200
PP
Common Mode
Input Voltage;
NOTE 1
V
1.2
V
1.2
V
CC
CMR
CC
CC
INAx,
Input
INB
nINA,
nINB
I
I
High
Current
150
150
150
µA
IH
INAx,
INB
-10
-10
-10
µA
µA
Input
Low
Current
IL
nINA,
nINB
-150
-150
-150
NOTE: Input and output parameters vary 1:1 with VCC. VCC can vary +0.165V to -0.925V.
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single-ended applications, the maximum input voltage for INAx, nINAx and INB, nINB is VCC + 0.3V.
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853S54I-01 Datasheet
Table 4D. ECL DC Characteristics, V = -3.465V to -2.375V, V = 0V, T = -40°C to 85°C
EE
CC
A
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Min
Typ
Max
Min
Max
Min
Max
Units
Output
V
V
V
V
High Voltage;
NOTE 1
-1.125
-1.025
-0.0875
-1.075
-1.005
-1.78
800
-0.880
-1.015
-0.97
-1.765
800
-0.885
V
OH
OL
Output
Low Voltage;
NOTE 1
-1.895
150
-1.755
800
-1.62
1200
-1.875
150
-1.685
1200
-1.86
150
-1.67
1200
V
mV
V
Peak-to-Peak
Input Voltage;
NOTE 2
PP
Common Mode
Input Voltage;
NOTE 1
V
+
EE
V
V
+ 1.2
V
V
+ 1.2
V
CC
CMR
CC
EE
CC
EE
1.2
INAx,
INB
nINA,
nINB
Input
High
Current
I
I
150
150
150
µA
IH
INAx,
INB
-10
-10
-10
µA
µA
Input
Low
Current
IL
nINA,
nINB
-150
-150
-150
NOTE: Input and output parameters vary 1:1 with VCC.
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single-ended applications, the maximum input voltage for INAx, nINAx and INB, nINB is VCC + 0.3V.
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853S54I-01 Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics, V = 2.375V TO 3.465V, V = 0V, T = -40°C to 85°C
CC
EE
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
2.5
Units
GHz
ps
fOUT
Output Frequency
INAx to QB
INB to QAx
INAx to QAx
225
200
250
525
tPD
Propagation Delay; NOTE 1
475
ps
550
ps
tsk(pp)
tjit
Part-to-Part Skew; NOTE 2, 3
275
ps
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
ƒ = 622.08MHz,
12kHz – 20MHz
27
61
fs
tR / tF
Output Rise/Fall Time
20% to 80%
50
325
ps
ƒ = 622.08MHz;
Input Peak-to-Peak = 800mV
MUX_ISOLATION MUX Isolation; NOTE 4
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at 1.3GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same
frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See MUX Isolation Diagram in Parameter Measurement Information section.
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853S54I-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 27fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
have issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Rohde & Schwarz SMA100A Signal Generator 9kHz – 6GHz as
external input to Agilent 8133A 3GHz Pulse Generator.
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853S54I-01 Datasheet
Parameter Measurement Information
2V
V
CC
SCOPE
nINA[0:1], nINB
INA[0:1], nINB
V
Qx
CC
VPP
VCMR
Cross Points
nQx
V
EE
VEE
-0.375V to -1.465V
LVPECL Output Load AC Test Circuit
Differential Input Level
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
A1
Part 1
nQx
Qx
MUX_ISOL = A0 – A1
Part 2
nQy
MUX selects static input
Qy
tsk(pp)
ƒ
Frequency
(fundamental)
Part-to-Part Skew
MUX Isolation
nINA[0:1],
nINB
nQA[0:1],
nQB
INA[0:1],
INB
nQA[0:1],
nQB
QA[0:1],
QB
QA[0:1],
QB
tPD
Output Rise/Fall Time
Propagation Delay
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853S54I-01 Datasheet
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept
single ended levels. The reference voltage VREF = VCC/2 is
generated by the bias resistors R1 and R2. The bypass capacitor
(C1) is used to help filter noise on the DC bias. This bias circuit
should be located as close to the input pin as possible. The ratio of
R1 and R2 might need to be adjusted to position the VREF in the
center of the input voltage swing. For example, if the input clock
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted
to set VREF at 1.25V. The values below are for when both the single
ended swing and VCC are at the same voltage. This configuration
requires that the sum of the output impedance of the driver (Ro)
and the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
IN/nIN Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
INx and nINx can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from INx to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
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853S54I-01 Datasheet
3.3V Differential Clock Input Interface
The IN /nIN accepts LVPECL, CML, LVDS and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the IN
/nIN input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
R1
50
R2
50
Zo = 50Ω
Zo = 50Ω
IN
IN
R1
100
nIN
Zo = 50Ω
LVPECL
nIN
LVPECL
Differential
Inputs
Differential
Inputs
CML Built-In Pullup
CML
Figure 2A. IN/nIN Input
Figure 2B. IN/nIN Input
Driven by an Open Collector CML Driver
Driven by a Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
R1
125
R3
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
R1
100
nIN
nIN
LVPECL
Differential
Input
Zo = 50Ω
LVPECL
Differential
Inputs
LVPECL
LVDS
R2
84
R4
84
Figure 2C. IN/nIN Input
Driven by a 3.3V LVPECL Driver
Figure 2D. IN/nIN Input Driven by
a 3.3V LVDS Driver
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853S54I-01 Datasheet
2.5V Differential Clock Input Interface
The IN /nIN accepts LVPECL, CML, LVDS and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 3A to 3D show interface examples for the IN
/nIN input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
2.5V
2.5V
3.3V
3.3V
Zo = 50Ω
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
R1
100Ω
nIN
Zo = 50Ω
LVPECL
nIN
LVPECL
Differential
Inputs
Differential
Inputs
CML Built-In Pullup
CML
Figure 3A. IN/nIN Input
Figure 3B. IN/nIN Input
Driven by an Open Collector CML Driver
Driven by a Built-In Pullup CML Driver
3.3V
2.5V
2.5V
3.3V
R1
125Ω
R3
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
R1
100Ω
nIN
nIN
LVPECL
Differential
Input
Zo = 50Ω
LVPECL
Differential
Inputs
LVPECL
LVDS
R2
84Ω
R4
84Ω
Figure 3C. IN/nIN Input
Figure 3D. IN/nIN Input Driven by
a 3.3V LVDS Driver
Driven by a 3.3V LVPECL Driver
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853S54I-01 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically
Enhance Leadframe Base Package, Amkor Technology.
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
SOLDER
PIN
SOLDER
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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853S54I-01 Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECLcompatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
3.3V
R3
R4
125
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
R2
84
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
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853S54I-01 Datasheet
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50 to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to
ground level. The R3 in Figure 6B can be eliminated and the
termination is shown in Figure 6C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
R3
250Ω
50Ω
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
2.5V LVPECL Driver
R2
R4
62.5Ω
62.5Ω
R3
18Ω
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
Figure 6C. 2.5V LVPECL Driver Termination Example
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853S54I-01 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 853S54I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 853S54I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 45mA = 155.925mW
Power (outputs)MAX = 30.75mW/Loaded Output pair
If all outputs are loaded, the total power is 3 * 30.75mW = 92.25mW
Total Power_MAX (3.8V, with all outputs switching) = 155.925mW + 92.25mW = 248.175mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.248W * 74.7°C/W = 103.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 6. Thermal Resistance JA for 16 Lead VFQFN Forced Convection
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
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853S54I-01 Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
VCC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.885V
(VCC_MAX – VOH_MAX) = 0.885V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V
(VCC_MAX – VOL_MAX) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.885V)/50] * 0.885V = 19.73mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.67V)/50] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.75mW
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853S54I-01 Datasheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
Transistor Count
The transistor count for 853S54I-01 is: 304
This device is pin and function compatible and a suggested replacement for 853S54I-01.
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853S54I-01 Datasheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
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853S54I-01 Datasheet
Package Outline - K Suffix for 16 Lead VFQFN, continued
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853S54I-01 Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
853S54AKI-01LF
853S54AKI-01LFT
Marking
Package
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
3A01
3A01
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
Tape & Reel
Revision History Sheet
Date
Description of Change
Page 2, Table 3. Control Input Function Table update.
March 2, 2017
Pages 18-19. Updated ICS package drawing to IDT package drawing.
Updated datasheet format.
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