85311AMLFT [IDT]
Low Skew, 1-to-2 , Different ial-to-2 .5V, 3.3V LVPECL/ ECL Fanout Buffer;型号: | 85311AMLFT |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Low Skew, 1-to-2 , Different ial-to-2 .5V, 3.3V LVPECL/ ECL Fanout Buffer 驱动 光电二极管 逻辑集成电路 |
文件: | 总16页 (文件大小:315K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Low Skew , 1-to-2, Differential-to-2.5V, 3.3V
LVPECL/ ECL Fanout Buffer
85311
Datasheet
General Description
Features
The 85311 is a low skew, high performance 1-to-2 Differential-to-
2.5V/3.3V ECL/LVPECL Fanout Buffer and a member of the high
performance clock solutions from IDT. The CLK, nCLK pair can
accept most standard differential input levels. The 85311 is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and part-to-part skew characteristics make the
85311 ideal for those clock distribution applications demanding well
defined performance and repeatability.
• Two differential 2.5V/3.3V LVPECL / ECL outputs
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 1GHz
• Translates any single ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
• Output skew: 15ps (maximum)
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 1.4ns (maximum)
• Additive phase jitter, RMS: 0.14ps (typical), 3.3V
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
Q0
nQ0
Q0
nQ0
Q1
VCC
1
2
3
4
8
7
6
5
Pulldown
Pullup
CLK
CLK
nCLK
VEE
nCLK
Q1
nQ1
nQ1
85311
8-Lead SOIC
3.90mm x 4.903mm x 1.37mm package body
M Package
Top View
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85311 Datasheet
Pin Descriptions and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6
nCLK
CLK
Pullup
Pulldown
Inverting differential clock input.
Non-inverting differential clock input.
Positive supply pin.
7
Input
8
VCC
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
k
RPULLDOWN Input Pulldown Resistor
k
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85311 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Storage Temperature, TSTG
-65C to 150C
Package Thermal Impedance, JA
103C/W (0 lfpm)
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.625
25
Units
V
Positive Supply Voltage
Power Supply Current
2.375
2.5
V
IEE
mA
Table 3B. Differential DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
nCLK
CLK
VCC = VIN = 3.465V or 2.625V
VCC = VIN = 3.465V or 2.625V
VCC = 3.465V or 2.625V, VIN = 0V
5
IIH Input High Current
150
µA
nCLK
CLK
-150
-5
µA
IIL
Input Low Current
V
CC = 3.465V or 2.625V, VIN = 0V
µA
Peak-to-Peak Input Voltage;
NOTE 1
VPP
0.15
1.3
V
V
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC – 0.85
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Table 3C. LVPECL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
VCC – 1.4
VCC – 2.0
0.65
Typical
Maximum Units
VOH
Output High Current; NOTE 1
VCC – 0.9
VCC – 1.7
1.0
V
V
V
VOL
Output Low Current; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE1: Outputs terminated with 50 to VCC – 2V.
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85311 Datasheet
AC Electrical Characteristics
Table 4A. AC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ns
1
Propagation Delay; NOTE 1
ƒ 1GHz
0.9
1.4
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
156.25MHz, Integration Range
(12kHz – 20MHz)
tjit
0.14
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
15
100
700
52
ps
ps
ps
%
20% to 80% @ 50MHz
300
48
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
All parameters are measured 500MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ns
1
Propagation Delay; NOTE 1
ƒ 1GHz
0.9
1.4
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
156.25MHz, Integration Range
(12kHz – 20MHz)
tjit
0.135
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
15
100
700
52
ps
ps
ps
%
20% to 80% @ 50MHz
300
48
See Table 5A for NOTES.
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85311 Datasheet
Additive Phase Jitter (3.3V)
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.14ps (typical)
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
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85311 Datasheet
Parameter Measurement Information
2V
2V
SCOPE
SCOPE
VCC
Qx
VCC
Qx
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit
2.5V Core/ 2.5V LVPECL Output Load AC Test Circuit
V
CC
nQx
Qx
nCLK
nQy
Qy
V
V
Cross Points
PP
CMR
CLK
V
EE
Differential Input Level
Output Skew
Part 1
nQx
nCLK
CLK
Qx
Part 2
nQy
nQ[0:1]
Qy
Q[0:1]
tPD
tsk(pp)
Part-to-Part Skew
Propagation Delay
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85311 Datasheet
Parameter Measurement Information, continued
nQ[0:1]
Q[0:1]
nQ[0:1]
Q[0:1]
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
Applications Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
VCC
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
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85311 Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example, in Figure
2A, the input termination applies for IDT’s open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
LVHSTL
IDT
LVHSTL Driver
Input
R1
50Ω
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
3.3V
3.3V
2.5V
3.3V
2.5V
R3
120Ω
R4
120Ω
*R3
*R4
CLK
Zo = 60Ω
Zo = 60Ω
CLK
nCLK
Differential
Input
nCLK
HCSL
Differential
Input
SSTL
R1
120Ω
R2
120Ω
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
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85311 Datasheet
Recommendations for Unused Output Pins
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
3.3V
R3
125
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
R2
84
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
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85311 Datasheet
Termination for 2.5V LVPECL Outputs
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 4B can be eliminated and the termination is
shown in Figure 4C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
250Ω
R3
250Ω
+
50Ω
50Ω
50Ω
+
–
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R4
62.5Ω
R3
18Ω
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 4C. 2.5V LVPECL Driver Termination Example
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85311 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 85311.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 85311 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.3V, with all outputs switching) = 86.6mW + 60mW = 146.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 103°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.147W * 103°C/W = 85.14°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5. Thermal Resistance JA for 8 Lead SOIC, Forced Convection
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
103°C/W
94°C/W
89°C/W
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85311 Datasheet
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
VCC - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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85311 Datasheet
Reliability Information
Table 6. JA vs. Air Flow Table for a 8 Lead SOIC
JA by Velocity
Linear Feet per Minute
0
200
500
89°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
103°C/W
94°C/W
Transistor Count
The transistor count for 85311 is: 225
Package Outline and Package Dimensions
Package Outline - M Suffix for 8 Lead SOIC
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
A1
B
C
D
E
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
e
1.27 Basic
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
Reference Document: JEDEC Publication 95, MS-012
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85311 Datasheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
85311AMLF
Marking
Package
Shipping Packaging
Tube
Temperature
0C to 70C
0C to 70C
85311ALF
85311ALF
“Lead-Free” 8 Lead SOIC
“Lead-Free” 8 Lead SOIC
85311AMLFT
Tape & Reel
©2016 Integrated Device Technology, Inc.
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85311 Datasheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
8
5
Added Termination for LVPECL Outputs section.
5/30/02
3.3V Output Load Test Circuit Diagram - corrected VEE equation to read
-1.3V 0.165V from 0.135V.
Updated Output Rise/Fall Time Diagram.
A
B
9/23/02
7
1
2
Add Lead-Free bullet in Features section.
T2
T8
Pin Characteristics table - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings, updated Outputs rating.
Combined 3.3V & 2.5V Power tables and Differential DC Characteristics tables.
Updated Parameter Measurement Information.
3
3
5
6/17/04
6
Updated Single Ended Signal Driving Differential Input diagram.
Added Termination for 2.5V LVPECL Output section.
Added Differential Clock Input Interface section.
7
8
13
Ordering Information table - added Lead Free part number.
7
13
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - corrected Lead-Free marking and added
Lead-Free Note.
B
C
T8
T3
7/28/05
4/11/07
3
LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCCO
0.9V; and VSWING max. from 0.9V to 1.0V.
Power Considerations - corrected power dissipation to reflect VOH max in Table 3C.
-
9 - 10
4
T4A - T4B
Added 2.5V AC Characteristics Table. Added Additive Phase Jitter spec to both AC
Tables.
Added Additive Phase Jitter plot.
D
D
10/22/08
7/8/15
5
8
Updated Differential Input Clock Interface section.
T8
14
Ordering Information - removed leaded devices.
Updated data sheet format.
11
Power Considerations - updated Junction Temperature section and corrected Table
5, Thermal Resistance Table.
T6
T8
13
14
Corrected table.
E
2/16/16
Ordering Information Table - deleted table note.
Deleted HiperClockS reference throughout the datasheet.
Updated datasheet header/footer.
©2016 Integrated Device Technology, Inc.
15
Revision E, February 18, 2016
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2015 Integrated Device Technology, Inc. All rights reserved.
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