85310I-11 [IDT]
Low Skew, 1-to-10 Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer;
| 型号： | 85310I-11 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-10 Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer |
| 文件： | 总18页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-10 Differential-to-3.3V,
2.5V LVPECL/ECL Fanout Buffer
85310I-11
DATA SHEET
General Description
Features
The 85310I-11 is a low skew, high performance 1-to-10
• Ten differential 2.5V, 3.3V LVPECL/ECL output pair
• Two selectable differential input pairs
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer. The CLKx,
nCLKx pairs can accept most standard differential input levels. The
85310I-11 is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
• Differential CLKx, nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
characteristics make the 85310I-11 ideal for those clock distribution
applications demanding well defined performance and repeatability.
• Translates any single ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
• Output skew: 30ps (typical)
• Part-to-part skew: 140ps (typical)
• Propagation delay: 2ns (typical)
• Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
Pin Assignment
Block Diagram
Q0
Pulldown
Pullup
nQ0
CLK0
nCLK0
0
1
Q1
32 31 30 29 28 27 26 25
Pulldown
Pullup
nQ1
CLK1
nCLK1
1
2
3
4
5
6
7
8
VCC
Q3
24
23
22
21
20
Q2
CLK_SEL
CLK0
nQ3
Q4
nQ2
Q3
Pulldown
CLK_SEL
CLK_EN
nQ4
Q5
nCLK0
nQ3
CLK_EN
Q4
nQ4
CLK1
nCLK1
VEE
nQ5
Q6
19
18
17
Pullup
D
Q5
Q
nQ5
LE
nQ6
Q6
9
10 11 12 13 14 15 16
nQ6
Q7
nQ7
85310I-11
Q8
nQ8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q9
nQ9
Y Package
Top View
85310I-11 Rev F 7/8/15
1
©2015 Integrated Device Technology, Inc.
85310I-11 DATA SHEET
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VCC
Power
Input
Positive supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
2
CLK_SEL
Pulldown
3
4
CLK0
Input
Input
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
nCLK0
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
5
CLK_EN
Input
Pullup
6
CLK1
Input
Pulldown
Pullup
Non-inverting differential clock input.
7
8
nCLK1
VEE
Input
Inverting differential clock input.
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Negative supply pin.
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VCCO
Output supply pins.
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
k
RPULLDOWN Input Pulldown Resistor
k
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
2
Rev F 7/8/15
85310I-11 DATA SHEET
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
CLK_EN
Selected Source
CLK0, nCLK0
CLK1, nCLK1
Q[0:9]
nQ[0:9]
Disabled; HIGH
Enabled
0
1
Disabled; LOW
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 input as described in Table 3B.
Enabled
Disabled
nCLK[0:1]
CLK[0:1]
CLK_EN
nQ[0:9]
Q[0:9]
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK0 or CLK1
nCLK0 or nCLK1
Q[0:9]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ[0:9]
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
0
1
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Applications Information, Wiring the Differential Input to Accept Single-ended Levels.
Rev F 7/8/15
3
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
47.9C/W (0 lfpm)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
Units
V
VCC
VCCO
IEE
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
2.375
3.3
3.8
V
120
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Input High Voltage
Input Low Voltage
2
VCC + 0.3
VIL
-0.3
0.8
5
V
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
CC = VIN = 3.8V
CC = VIN = 3.8V
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
V
150
V
CC = 3.8V, VIN = 0V
-150
-5
IIL
VCC = 3.8V, VIN = 0V
Table 4C. DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
CC = VIN = 3.8V
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK[0:1],
nCLK[0:1]
CLK[0:1]
nCLK[0:1]
V
150
5
IIH
Input High Current
VCC = VIN = 3.8V
VCC = 3.8V, VIN = 0V
VCC = 3.8V, VIN = 0V
-5
-150
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Range; NOTE 1, 2
VEE + 0.5
VCC – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
4
Rev F 7/8/15
85310I-11 DATA SHEET
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO – 2.0
0.6
Typical
Maximum
VCCO – 0.9
VCCO – 1.7
1.0
Units
VOH
Output High Voltage; NOTE 1
V
V
V
VOL
Output Low Voltage; NOTE 1
Vswing
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO – 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
700
Units
MHz
ns
Output Frequency
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Skew; NOTE 3, 4
2
2.5
tsk(pp)
tsk(o)
140
30
340
ps
55
ps
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter section
tjit
<0.13
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
47
700
53
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
Rev F 7/8/15
5
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
6
Rev F 7/8/15
85310I-11 DATA SHEET
Parameter Measurement Information
2V
V
CC
SCOPE
nCLK[0:1]
CLK[0:1]
Qx
VCC,
VCCO
V
V
Cross Points
PP
CMR
nQx
V
EE
VEE
-0.375V to -1.8V
LVPECL Output Load AC Test Circuit
Differential Input Level
Part 1
nQx
nQx
Qx
Qx
nQy
Qy
Part 2
nQy
Qy
tsk(pp)
Part-to-Part Skew
Output Skew
nCLK[0:1]
CLK[0:1]
nQ[0:9]
Q[0:9]
nQ[0:9]
Q[0:9]
tPD
Output Rise/Fall Time
Propagation Delay
Rev F 7/8/15
7
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Parameter Measurement Information
nQ[0:9]
Q[0:9]
Output Duty Cycle/Pulse Width/Period
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
8
Rev F 7/8/15
85310I-11 DATA SHEET
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
LVHSTL
IDT
LVHSTL Driver
Input
R1
50Ω
R2
50Ω
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
120Ω
R4
120Ω
Zo = 60Ω
Zo = 60Ω
*R3
*R4
CLK
CLK
nCLK
nCLK
Differential
Input
SSTL
Differential
Input
HCSL
R1
120Ω
R2
120Ω
Figure 3F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Rev F 7/8/15
9
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Recommendations for Unused Input Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVPECL Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVCMOS Control Pins
The control pins have an internal pullup and pulldown; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
3.3V
R3
125
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
R2
84
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
10
Rev F 7/8/15
85310I-11 DATA SHEET
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
250Ω
R3
250Ω
+
50Ω
50Ω
50Ω
+
–
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R4
62.5Ω
R3
18Ω
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 5C. 2.5V LVPECL Driver Termination Example
Rev F 7/8/15
11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS5311I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS5311I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30mW = 300mW
Total Power_MAX (3.8V, with all outputs switching) = 456mW + 300mW = 756mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.756W * 42.1°C/W = 116.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 32 Lead LQFP, Forced Convection
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
12
Rev F 7/8/15
85310I-11 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
Rev F 7/8/15
13
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead LQFP
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for 85310I-11 is: 1034
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
14
Rev F 7/8/15
85310I-11 DATA SHEET
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 8. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBA
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
A2
1.40
0.37
b
c
D & E
D1 & E1
D2 & E2
e
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
L
0.45
0°
0.75
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
Rev F 7/8/15
15
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
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85310I-11 DATA SHEET
Ordering Information
Table 9. Ordering Information
Part/Order Number
85310AYI-11LF
Marking
Package
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
ICS5310AI11L
ICS5310AI11L
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
85310AYI-11LFT
Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
16
Rev F 7/8/15
85310I-11 DATA SHEET
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T5
5
AC Characteristics table - tPD row, revised value from 2.25ns Max. to
2.5ns Max.
B
4/29/02
5/29/02
B
9
5
Added Termination for LVPECL Outputs.
Added LVPECL DC Characteristics table.
T4D
T4A
C
D
7/25/02
Changed part number from ICS85310-11 to 85310I-11 in title and all subsequent areas
throughout the datasheet.
4
7
Power Supply table - increased max. value for IEE to 120mA from 30mA max.
Power Considerations have re-adjusted to the increased IEE value.
10/23/02
1
2
5
6
Features Section - added Additive Phase Jitter bullet and Lead-Free bullet.
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
AC Characteristics Table - added Additive Phase Jitter spec.
Added Additive Phase Jitter Section.
T2
T5
E
F
7/7/05
9
10
Added Termination for 2.5V LVPECL Outputs.
Added Differential Clock Input Interface.
15
T9
Ordering Information Table - added Lead-Free Part Number and Note.
T4D
5
LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to
VCCO - 0.9V; and VSWING max. from 0.85V to 1.0V.
4/11/07
11 - 12
Power Considerations - corrected power dissipation to reflect VOH max in Table 4D.
T4C
T5
4
5
Differential DC Characteristics Table -updated NOTES.
AC Characteristics Table - added thermal note.
Updated Wiring the Differential Input to Accept Single-ended Levels section.
Updated Figure 4A & 4B.
8
F
F
6/9/10
7/8/15
10
16
T9
T9
Ordering Information Table - corrected lead-free marking.
Converted datasheet format.
16
Ordering Information - removed leaded devices.
Updated data sheet format.
Rev F 7/8/15
17
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
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