843201-375 [IDT]
FemtoClock® Crystal-to-LVPECL 375MHz Frequency Margining Synthesizer;
| 型号： | 843201-375 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock® Crystal-to-LVPECL 375MHz Frequency Margining Synthesizer |
| 文件： | 总19页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock® Crystal-to-LVPECL 375MHz
Frequency Margining Synthesizer
843201-375
DATASHEET
GENERAL DESCRIPTION
FEATURES
• One 375MHz nominal LVPECL output
The 843201-375 is a low phase-noise frequency margining
synthesizer. In the default mode, the device nominally generates a
375MHz LVPECL output clock signal from a 25MHz crystal input.
There is also a frequency margining mode available where the
device can be configured, using control pins, to vary the output
frequency up or down from nominal by 5%. The 843201-375 is
provided in a 16-pin TSSOP package.
• Crystal oscillator interface designed for 25MHz, 18pF parallel
resonant crystal
• Output frequency can be varied 5% from nominal
• VCO range: 700MHz - 800MHz
• RMS phase jitter @ 375MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.72ps (typical) @ 3.3V
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Functional replacement part 8T49N241-dddNLGI
PIN ASSIGNMENT
BLOCK DIAGRAM
Pulldown
VCC
MODE
nc
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
nPLL_SEL
nQ
VCCO
VCC
0
1
0
XTAL_IN
XTAL_OUT
MARGIN
VEE
VEE
25MHz
XTAL_IN
MR
Q
Predivider
Phase
Detector
VCO
nPLL_SEL
nc
÷2
÷2
1
OSC
700 - 800MHz
nQ
nc
XTAL_OUT
843201-375
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
÷30
(÷57, ÷63)
G Package
Top View
Pulldown
Pulldown
Pulldown
MODE
MARGIN
MR
843201-375 REVISION A 8/21/15
1
©2015 Integrated Device Technology, Inc.
843201-375 DATA SHEET
FUNCTIONAL DESCRIPTION
The 843201-375 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A 25MHz fundamental crystal is used as the input to the on chip
oscillator. In regular mode, the 25MHz crystal frequency is applied
directly to the phase detector. In frequency margining mode, the
25MHz crystal frequency is divided by 2 and a 12.5MHz reference
frequency is applied to the phase detector. The VCO of the PLL
operates over a range of 700MHz to 800MHz. The output of the M
divider is also applied to the phase detector. The default mode for
the 843201-375 is a nominal 375MHz output. The nominal output
frequency can be changed by placing the device into the margining
mode using the mode pin and using the margin pin to change the M
feedback divider.Frequency margining mode operation occurs when
the MODE input is HIGH.The phase detector and the M divider force
theVCO output frequency to be M times the reference frequency by
adjusting theVCO control voltage.The output of theVCO is scaled by
an output divider prior to being sent to the LVPECL output buffer.The
divider provides a 50% output duty cycle.The relationship between
the crystal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing back
from frequency margining mode to nominal mode, the device will
return to the default nominal configuration described above.
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
Reference
Frequency (MHz)
Feedback
Divider
MODE
MARGIN XTAL (MHz)
Pre-Divider (P)
VCO (MHz)
% Change
1
0
1
0
X
1
25
25
25
2
none
2
12.5
57
30
63
712.5
750
-5.0
Nom. Mode
5.0
25
12.5
787.5
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
2
REVISION A 8/21/15
843201-375 DATA SHEET
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Power
Description
1, 13
V
Positive supply pins.
CC
MODE pin. LOW = default mode. HIGH = frequency margining mode.
LVCMOS/LVTTL interface levels.
2
MODE
nc
Input
Unused
Input
Pulldown
Pulldown
3, 8, 9
4, 5
No connect.
XTAL_IN, XTAL_
OUT
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Sets the frequency margin to 5% in frequency margining mode.
See Table 1. LVCMOS/LVTTL interface levels.
6
Margin
Input
7, 12
V
Power
Negative supply pins.
EE
PLL select pin. When HIGH, PLL is bypassed and input is fed directly to
10
nPLL_SEL
Input
Pulldown the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inverted output nQ
to go high. When logic LOW, the internal dividers and the output is en-
11
MR
Input
Pulldown
abled. LVCMOS/LVTTL interface levels.
14
V
Power
Output
Output supply pin.
CCO
15, 16
nQ, Q
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
C
Input Capacitance
Input Pulldown Resistor
4
pF
IN
R
51
kΩ
PULLDOWN
TABLE 4. MODE CONTROL INPUT FUNCTION TABLE
Input
Condition
Q, nQ
MODE
0
1
Default Mode
Frequency Margining Mode
REVISION A 8/21/15
3
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
CC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to V + 0.5V
I
CC
Outputs, I
O
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
99.9°C/W (0 lfpm)
JA
Storage Temperature, T
-65°C to 150°C
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, V = V
= 3.3V 5%, TA = 0°C TO 70°C
CCO
CC
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
V
V
I
Positive Supply Voltage
3.465
3.465
108
96
V
CC
Output Supply Voltage
Power Supply Current
Power Supply Current
Output Supply Current
3.135
3.3
V
CCO
mA
mA
mA
EE
I
I
CC
12
CCO
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, V = 3.3V 5%,V
= 2.5V 5%, TA = 0°C TO 70°C
CCO
CC
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
Maximum Units
V
V
I
Positive Supply Voltage
3.3
3.465
2.625
108
96
V
CC
Output Supply Voltage
Power Supply Current
Power Supply Current
Output Supply Current
2.375
2.5
V
CCO
mA
mA
mA
EE
I
I
CC
12
CCO
TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, V = V
= 2.5V 5%, TA = 0°C TO 70°C
CCO
CC
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
V
V
I
Positive Supply Voltage
2.625
2.625
101
95
V
CC
Output Supply Voltage
Power Supply Current
Power Supply Current
Output Supply Current
2.375
2.5
V
CCO
mA
mA
mA
EE
I
I
CC
6
CCO
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
4
REVISION A 8/21/15
843201-375 DATA SHEET
TABLE 5D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
V
V
V
V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
2
V
V
+ 0.3
+ 0.3
V
V
V
V
CC
CC
CC
CC
CC
V
V
I
Input High Voltage
IH
1.7
-0.3
-0.3
CC
0.8
Input Low Voltage
IL
0.7
Input
High Current
MARGIN, MODE,
nPLL_SEL, MR
V
= V = 3.465
CC or 2.625V
IN
150
µA
µA
IH
Input
Low Current
MARGIN, MODE,
nPLL_SEL, MR
V
= 3.465V or 2.625V,
CC
I
-5
IL
V = 0V
IN
TABLE 5E. LVPECL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Output High Voltage; NOTE 1
Minimum Typical Maximum Units
V
V
V
- 1.4
- 2.0
V
V
- 0.9
V
V
V
OH
CCO
CCO
V
Output Low Voltage; NOTE 1
- 1.7
OL
CCO
CCO
V
Peak-to-Peak Output Voltage Swing
0.6
1.0
SWING
NOTE 1: Outputs terminated with 50Ω to V - 2V.
CCO
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
300
µW
NOTE: Characterized using an 18pF parallel resonant crystal.
NOTE: It is not recommended to overdrive the crystal input with an external clock.
REVISION A 8/21/15
5
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
TABLE 7A. AC CHARACTERISTICS, V = V
= 3.3V 5%, TA = 0°C TO 70°C
CCO
CC
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
f
Output Frequency
375
MHz
OUT
RMS Phase Jitter (Random);
NOTE 1
375MHz,
Integration Range: 12kHz - 20MHz
tjit(F)
t / t
0.72
ps
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
550
51
ps
%
R
F
odc
49
NOTE 1: Refer to Phase Noise Plot.
TABLE 7B. AC CHARACTERISTICS, V = 3.3V 5%,V
= 2.5V 5%, TA = 0°C TO 70°C
CCO
CC
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
f
Output Frequency
375
MHz
OUT
RMS Phase Jitter (Random);
NOTE 1
375MHz,
Integration Range: 12kHz - 20MHz
tjit(F)
t / t
0.72
ps
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
550
51
ps
%
R
F
odc
49
NOTE 1: Refer to Phase Noise Plot.
TABLE 7C. AC CHARACTERISTICS, V = V
= 2.5V 5%, TA = 0°C TO 70°C
CC
CCO
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
f
Output Frequency
375
MHz
OUT
RMS Phase Jitter (Random);
NOTE 1
375MHz,
Integration Range: 12kHz - 20MHz
tjit(F)
t / t
0.88
ps
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
550
51
ps
%
R
F
odc
49
NOTE 1: Refer to Phase Noise Plot.
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
6
REVISION A 8/21/15
843201-375 DATA SHEET
TYPICAL PHASE NOISE AT 375MHZ @ 3.3V/3.3V
0
-10
-20
-30
SONET Filter
-40
375MHz
-50
-60
-70
RMS Phase Noise Jitter
12kHz to 20MHz = 0.72ps (typical)
Raw Phase Noise Data
-80
-90
-100
-110
-120
-130
-140
-150
-160
Phase Noise Result by adding a
SONET Filter to raw data
-170
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 375MHZ @ 3.3V/2.5V
0
-10
-20
-30
-40
SONET Filter
375MHz
-50
RMS Phase Noise Jitter
-60
12kHz to 20MHz = 0.72ps (typical)
-70
Raw Phase Noise Data
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding a
SONET Filter to raw data
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
REVISION A 8/21/15
7
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
TYPICAL PHASE NOISE AT 375MHZ @ 2.5V/2.5V
0
-10
-20
-30
-40
SONET Filter
375MHz
-50
RMS Phase Noise Jitter
-60
12kHz to 20MHz = 0.88ps (typical)
-70
Raw Phase Noise Data
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding a
SONET Filter to raw data
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
8
REVISION A 8/21/15
843201-375 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
REVISION A 8/21/15
9
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The 843201-375 has been characterized with 18pF
Figure 1 below were determined using a 25MHz, 18pF parallel
parallel resonant crystals. The capacitor values shown in
resonant crystal and were chosen to minimize the ppm error.
FIGURE 1. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
10
REVISION A 8/21/15
843201-375 DATA SHEET
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
transmission lines.Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock com-
ponent process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
REVISION A 8/21/15
11
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
TERMINATION FOR 2.5V LVPECL OUTPUT
very close to ground level. The R3 in Figure 3B can be
eliminated and the termination is shown in Figure 3C.
Figure 3A and Figure 3B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to
terminating 50Ω to V - 2V. For V = 2.5V, the V - 2V is
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
250
R3
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driver
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
12
REVISION A 8/21/15
843201-375 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843201-375.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843201-375 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
•
Power (core) = V
* I
= 3.465V * 108mA = 374.2mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
Total Power
(3.465V) = 374.2mW + 30mW = 404.2mW
_MAX
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + T
A
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
= Ambient Temperature
T
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow
and a multi-layer board, the appropriate value is 99.9°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.404W * 99.9°C/W = 110°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 8. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
35.6°C/W
500
93.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
99.9°C/W
REVISION A 8/21/15
13
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate power dissipation due to loading, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
)
(VCCO_MAX - VOH_MAX = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
)
(VCCO_MAX - VOL_MAX = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX /R ] * (VCCO_MAX - VOH_MAX) =
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX /R ] * (VCCO_MAX - VOL_MAX) =
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
14
REVISION A 8/21/15
843201-375 DATA SHEET
RELIABILITY INFORMATION
TABLE 9. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θJA by Velocity (Linear Feet per Minute)
0
200
35.6°C/W
500
93.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
99.9°C/W
TRANSISTOR COUNT
The transistor count for 843201-375 is: 2433
REVISION A 8/21/15
15
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
16
REVISION A 8/21/15
843201-375 DATA SHEET
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
843201AG-375LF
843201AG-375LFT
201A375L
201A375L
16 Lead “Lead-Free” TSSOP
16 Lead “Lead-Free” TSSOP
0°C to 70°C
0°C to 70°C
tape & reel
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION A 8/21/15
17
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
REVISION HISTORY SHEET
Description of Change
Deleted HiPerClockS references.
Rev
Table
Page
1
Date
5
Crystal Characteristics Table - added note.
Deleted application note, LVCMOS to XTAL Interface.
Deleted quantity from tape and reel.
Ordering information - removed leaded devices.
Updated data sheet format.
A
T6
T9
4/26/13
11
17
17
T11
A
A
5/27/15
Product Discontinuation Notice - Last time buy expires August 14, 2016
PDN CQ-15-04
8/21/15
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
18
REVISION A 8/21/15
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800-345-7015 or +408-284-8200
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www.IDT.com
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相关型号：
843201AG-375LF
Clock Generator, 375MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
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