840001AKI-34LF [IDT]
Femtoclocks Crystal-to-LVCMOS/LVTTL Frequency Synthesizer;
| 型号： | 840001AKI-34LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Femtoclocks Crystal-to-LVCMOS/LVTTL Frequency Synthesizer |
| 文件： | 总15页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Femtoclocks™ Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
840001I-34
Data Sheet
General Description
Features
The 840001I-34 is a two output LVCMOS/LVTTL Synthesizer. One
output is the LVCMOS/LVTTL main synthesized clock output (Q)
and one output is a three-state LVCMOS/LVTTL reference clock
(REF_OUT) output at the frequency of the crystal oscillator. The
device can accept crystals from 15.3125MHz to 42.67MHz and
can synthesize outputs from 81.67MHz to 213.33MHz. The
840001I-34 is packaged in a 3mm x 3mm 16-pin VFQFN, making
it ideal for use on space constrained boards.
• Two LVCMOS/LVTTL outputs, 22 typical output impedance
One main clock output (Q)
One three-state reference clock output (REF_OUT)
• Crystal oscillator interface can accept crystals from
15.3125MHz to 42.67MHz, 18pF parallel resonant crystal
• Q output frequency range: 81.67MHz to 213.33MHz
• RMS phase jitter @106.25, (637kHz – 10MHz): 0.38ps (typical)
• VCO range: 490MHz to 640MHz
• Full 3.3V and 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Common Application Configuration Table
Inputs
Output Frequency
Crystal (MHz)
M Divider
VCO (MHz)
N Divider
(MHz)
Application
Serial Attached (SCSI),
PCI Express, Processor Clock
40
15
600
6
100 (default)
26.5625
40
24
15
24
25
25
25
32
637.5
600
6
4
3
5
4
3
4
106.25
150
Fibre Channel
Serial ATA (SATA), Processor Clock
Fibre Channel 2
Ethernet
26.5625
25
637.5
625
212.5
125
25
625
156.25
187.5
155.52
10 Gigabit Ethernet
12 Gigabit Ethernet
SONET
22.5
562.5
622.08
19.44
Block Diagram
(Pullup)
OE
Pin Assignment
REF_OUT
N-Div
XTAL_IN
OSC
VCO
00 = ÷3
01 = ÷4
10 = ÷5
Phase
Detector
Q
490MHz - 640MHz
16 15 14 13
XTAL_OUT
1
2
3
OE
XTAL_IN
XTAL_OUT
M0
12
11
10
Q
11 = ÷6 (default)
VDDO
GND
VDD
M-Div
11 = ÷15 (default)
10 = ÷24
4
9
5
6
7
8
01 = ÷25
00 = ÷32
(Pullup)
M1
840001-34
(Pullup)
M0
16 Lead VFQFN
(Pullup)
N1
3mm x 3mm x 0.925 package body
K Package
(Pullup)
N0
Top View
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
Output enable pin. When HIGH, REF_OUT output is enabled. When LOW,
forces REF_OUT to Hi-Z state. See Table 3A. LVCMOS/LVTTL interface levels.
1
OE
Input
Input
Pullup
2,
3
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
4, 5
M0, M1
nc
Input
Pullup
Pullup
M divider inputs. LVCMOS/LVTTL interface levels. See Table 3B.
No connect.
6, 14, 15
Unused
Determines output divider value as defined in Table 3C.
LVCMOS/LVTTL interface levels.
7, 8
No, N1
Input
9
VDD
GND
VDDO
Power
Power
Power
Core supply pin.
10
11
Power supply ground.
Output supply pin.
Single-ended clock output. 22 typical output impedance.
LVCMOS/LVTTL interface levels.
12
Q
Output
Single-ended three-state reference clock output. 22 typical output impedance.
LVCMOS/LVTTL interface levels.
13
16
REF_OUT
VDDA
Output
Power
Analog supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
8
pF
pF
pF
k
V
DD, VDDO = 3.465V
CPD
Power Dissipation Capacitance
Input Pullup Resistor
VDD, VDDO = 2.625V
6
RPULLUP
ROUT
51
22
26
VDD, VDDO = 3.3V 5%
14
16
30
36
Output Impedance
VDD, VDDO = 2.5V 5%
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Table 3A. Control Input Function Table
Control Input
Output
REF_OUT
Hi-Z
OE
0
1
Active (default)
Table 3B. M Divider Function Table
Control Inputs
M1
0
M0
0
Feedback Divider Ratio
÷32
÷25
0
1
1
0
÷24
1
1
÷15 (default)
Table 3C. N Divider Function Table
Control Inputs
N1
0
N0
0
Output Divider Ratio
÷3
÷4
0
1
1
0
÷5
1
1
÷6 (default)
©2016 Integrated Device Technology, Inc
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840001I-34 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
76.1C/W (0 mps)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.12
3.135
3.3
V
3.3
3.465
100
V
mA
mA
mA
IDDA
IDDO
12
35
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
VDD
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.12
2.375
3.3
V
2.5
2.625
90
V
mA
mA
mA
IDDA
IDDO
12
25
©2016 Integrated Device Technology, Inc
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840001I-34 Data Sheet
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
Input Low Voltage
VDD = 2.5V
0.7
Input High
Current
OE, M0, M1,
N0, N1
IIH
IIL
VDD = VIN = 3.465V or 2.625V
5
µA
µA
Input Low
Current
OE, M0, M1,
N0, N1
VDD = VIN = 3.465V or 2.625V
VDDO = 3.3V 5%
-150
2.6
1.8
V
V
Output High Voltage;
NOTE 1
VOH
VDDO = 2.5V 5%
Output Low Voltage; NOTE
1
VOL
VDDO = 3.3V 5% or 2.5V 5%
0.5
V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit
diagrams.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
15.3125
42.67
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: It is not recommended to overdrive the crystal input with an external clock.
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = -40°C to 85°
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
81.67
213.33
MHz
100MHz, Integration Range:
637kHz – 10MHz
0.54
0.38
ps
ps
RMS Phase Jitter,
Random; NOTE 1
tjit(Ø)
106.25MHz, Integration Range:
637kHz – 10MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Q, N = 3
200
40
700
60
ps
%
%
%
Q, N 3
48
52
REF_OUT
48
52
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions
NOTE 1: Please refer to Phase Noise Plot.
Table 6B. AC Characteristics, VDD = VDDO = 2.5V 5%, TA = -40°C to 85°
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
81.67
213.33
MHz
100MHz, Integration Range:
637kHz – 10MHz
0.54
0.38
ps
ps
RMS Phase Jitter,
Random; NOTE 1
tjit(Ø)
106.25MHz, Integration Range:
637kHz – 10MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Q, N = 3
300
35
800
65
ps
%
%
%
Q, N 3
40
60
REF_OUT
45
55
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions
NOTE 1: Please refer to Phase Noise Plot.
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Typical Phase Noise at 100MHz (3.3V)
Filter
100MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.54ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
a filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 106.25MHz (3.3V)
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.38ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
Fibre Channel filter to raw data
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Parameter Measurement Information
1.25V 5%
1.65V 5%
1.65V 5%
1.25V 5%
SCOPE
V
V
SCOPE
V
DD,
DD,
V
DDO
DDO
V
V
DDA
Qx
Qx
DDA
GND
GND
-1.65V 5%
-1.25V 5%
3.3V LVCMOS Output Load AC Test Circuit
2.5V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
VDDO
Q,
2
REF_OUT
tPW
Phase Noise Mask
tPERIOD
tPW
x 100%
odc =
Offset Frequency
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
80%
tF
80%
tR
20%
20%
Q, REF_OUT
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Application Information
Power Supply Filtering Technique
To achieve optimum jitter performance, power supply isolation is
required. The ICS40001I-34 provides separate power supplies to
isolate any high switching noise from the outputs to the internal
PLL. VDD, VDDA, and VDDO should be individually connected to the
power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic
VDD pin and also shows that VDDA requires that an additional 10
resistor along with a 10F bypass capacitor be connected to the
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
VDDA pin.
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Output
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1k
resistor can be used.
All unused LVCMOS output can be left floating. There should be
no trace attached.
Crystal Input Interface
The 840001I-34 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
XTAL_IN
C1
33pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
33pF
Figure 2. Crystal Input Interface
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering
process which may result in voids in solder between the exposed
pad/slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the
Application Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
incorporated on the Printed Circuit Board (PCB) within the
footprint of the package corresponding to the exposed metal pad
or exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask,
should be at least the same size/shape as the exposed pad/slug
area on the package to maximize the thermal/electrical
performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges
of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
application specific and dependent upon the package power
SOLDER
PIN
SOLDER
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
JA at 0 Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
76.1°C/W
66.5
59.7
Transistor Count
The transistor count for 840001I-34 is: 2805
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
(Ref.)
ND& NE
Even
Seating Plane
(ND-1)x e
(R ef.)
A1
Index Area
L
A3
E2
e
2
N
N
(Typ.)
If ND & NE
are Even
1
Anvil
Singulation
or
Sawn
Singulation
2
(NE -1)x e
(Re f.)
E2
2
Top View
D
b
e
Thermal
Base
A
(Ref.)
ND &NE
Odd
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Table 8. Package Dimensions
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol
Minimum
16
Maximum
N
A
0.80
1.00
0.05
A1
0
A3
0.25 Ref.
0.18
b
ND & NE
D & E
D2 & E2
e
0.30
4
3.00 Basic
1.00
1.80
0.50
0.50 Basic
0.30
L
Reference Document: JEDEC Publication 95, MO-220
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
840001AKI-34LF
840001AKI-34LFT
Marking
AI4L
AI4L
Package
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
Revision History Sheet
Rev
Table
Page Description of Change
Date
11
13
14
Updated VFQFN EPAD Thermal Release Path section.
A
Updated Package Drawing.
10/27/08
9
Ordering Information Table - corrected Temperature column.
1
5
Deleted HiPerClockS references.
T5
T9
Crystal Characteristics Table - added note.
A
A
10/16/12
1/15/16
9
Deleted application note, LVCMOS to XTAL Interface.
Deleted quantity from tape and reel. Deleted Lead-Free note.
13
Removed ICS from the part number where needed.
Updated data sheet header and footer.
©2016 Integrated Device Technology, Inc
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Revision A January 15, 2016
840001I-34 Data Sheet
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Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
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and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
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