概述
数据手册8312I_15 概述
Low Skew, 1-to-12 LVCMOS/LVTTL Fanout Buffer
8312I_15 数据手册
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PDF下载Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
8312I
Datasheet
General Description
Features
The 8312I is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312I single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
• Twelve LVCMOS/LVTTL outputs
• CLK input supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Output skew: 160ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
The 8312I is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312I ideal for
high performance, single ended applications that also require a
limited output voltage.
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
Pullup
CLK_EN
D
32 31 30 29 28 27 26 25
Q
1
2
3
4
5
6
7
8
GND
Q4
24
23
22
21
20
LE
VDD
VDDO
Q5
CLK_EN
12
Pulldown
Q[0:11]
CLK
OE
GND
Q6
CLK
GND
OE
VDD
VDDO
Q7
19
18
17
Pullup
GND
GND
9
10 11 12 13 14 15 16
8312I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
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December 14, 2015
8312I Datasheet
Table 1. Pin Descriptions
Number
Name
GND
VDD
Type
Description
1, 5, 8, 12, 16,
17, 21, 25, 29
Power
Power
Input
Input
Input
Power supply ground.
2, 7
Positive supply pins.
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
3
CLK_EN
CLK
Pullup
4
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q[0:11].
LVCMOS / LVTTL interface levels.
6
OE
Pullup
9, 11, 13, 15,
18, 20, 22, 24,
26, 28, 30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Power
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins.
10, 14, 19, 23,
27, 31
VDDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
k
k
pF
pF
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
VDDO = 3.465V
VDDO = 2.625V
19
18
16
Power Dissipation Capacitance
(per output); NOTE 1
CPD
VDDO = 2.V
VDDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ
VDDO = 1.8V 0.2V
7
7
ROUT
Output Impedance
10
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8312I Datasheet
Function Tables
Table 3A. Output Enable and Clock Enable Function Table
Inputs
Outputs
Q [0:11]
OE
0
CLK_EN
X
0
1
Hi-Z
1
LOW
1
Follows CLK input
Table 3B. Output Enable and Clock Enable Function Table
Inputs
Outputs
Q [0:11]
LOW
OE
1
CLK_EN
CLK
1
1
0
1
1
HIGH
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8312I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
47.9C/W (0 lfpm)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
10
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
V
mA
mA
IDDO
10
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
10
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
mA
mA
IDDO
10
Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
1.6
Typical
1.8
Maximum
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
2.0
2.0
10
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
V
mA
mA
IDDO
10
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8312I Datasheet
Table 4D. Power Supply DC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
3.465
2.625
10
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
mA
mA
IDDO
10
Table 4E. Power Supply DC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.0
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
V
10
mA
mA
IDDO
10
Table 4F. Power Supply DC Characteristics, VDD = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.0
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
V
10
mA
mA
IDDO
10
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8312I Datasheet
Table 4G. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol Parameter Test Conditions
DD = 3.465V
VDD = 2.625V
DD = 2.0V
VDD = 3.465V
DD = 2.625V
Minimum
2
Typical
Maximum
VDD + 0.3
VDD + 0.3
VDD + 0.3
1.3
Units
V
V
V
V
V
V
V
VIH
Input High Voltage
1.7
V
0.65*VDD
-0.3
VIL
Input Low Voltage
V
-0.3
0.7
VDD = 2.0V
-0.3
0.35*VDD
VDD = VIN = 3.465V or
2.625V or 2.0V
CLK
150
5
µA
µA
µA
µA
Input
High Current
IIH
VDD = VIN = 3.465V or
2.625V or 2.0V
OE, CLK_EN
CLK
V
DD = 3.465V or 2.625V or 2.0V,
-5
VIN = 0V
Input
Low Current
IIL
VDD = 3.465V or 2.625V or 2.0V,
VIN = 0V
OE, CLK_EN
-150
VDDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ;
2.6
1.8
V
V
V
V
V
V
V
V
V
V
VOH
Output High Voltage; NOTE 1
V
DDO = 2.5V 5ꢀ; IOH = -1mA
2
VDDO = 1.8V 0.2V
VDD – 0.3
VDD – 0.2
VDDO = 1.8V 0.2V; IOH = -100µA
VDDO = 3.3V 5ꢀ
0.5
0.45
0.4
VDDO = 2.5V 5ꢀ;
VOL
Output Low Voltage; NOTE 1
VDDO = 2.5V 5ꢀ; IOL = 1mA
VDDO = 1.8V 0.2V
0.35
0.2
VDDO = 1.8V 0.2V; IOL = 100µA
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
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8312I Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Output Frequency
250
2.7
MHz
ns
Propagation Delay, Low to High; NOTE 1
ƒ 250MHz
1.2
2.0
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.037
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
150
850
800
55
ps
ps
ps
ꢀ
20ꢀ to 80ꢀ
175
45
ƒ 150MHz
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Output Frequency
250
3.5
MHz
ns
Propagation Delay, Low to High; NOTE 1
ƒ 250MHz
1.25
2.4
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.022
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
155
1.1
800
55
ps
ns
ps
ꢀ
20ꢀ to 80ꢀ
200
45
ƒ 150MHz
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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8312I Datasheet
Table 5C. AC Characteristics, VDD = VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Output Frequency
200
4.9
MHz
ns
Propagation Delay, Low to High; NOTE 1
ƒ 200MHz
1.6
3.3
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.172
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
160
2.4
875
55
ps
ns
ps
ꢀ
20ꢀ to 80ꢀ
175
45
ƒ 100MHz
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Output Frequency
250
2.8
MHz
ns
Propagation Delay, Low to High; NOTE 1
ƒ 250MHz
1.5
2.1
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.045
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
150
1
ps
ns
ps
ꢀ
20ꢀ to 80ꢀ
200
45
800
55
ƒ 150MHz
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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8312I Datasheet
Table 5E. AC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Output Frequency
200
3.5
MHz
ns
Propagation Delay, Low to High; NOTE 1
ƒ 200MHz
1.5
2.5
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.136
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
150
1.4
800
55
ps
ns
ps
ꢀ
20ꢀ to 80ꢀ
200
45
ƒ 100MHz
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5F. AC Characteristics, VDD = 2.5V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
Output Frequency
200
3.9
MHz
ns
Propagation Delay, Low to High; NOTE 1
ƒ 200MHz
1.4
2.7
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.114
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
160
1.6
800
55
ps
ns
ps
ꢀ
20ꢀ to 80ꢀ
200
45
ƒ 100MHz
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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8312I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, 3.3V @ 100MHz
12kHz to 20MHz = 0.037ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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8312I Datasheet
Parameter Measurement Information
1.25V 5ꢀ
1.65V 5ꢀ
V
DD,
V
DD,
V
DDO
V
DDO
-1.25V 5ꢀ
-1.65V 5ꢀ
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
2.05V 5ꢀ
1.25V 5ꢀ
0.9V 0.1V
SCOPE
V
DD
V
DD,
V
DDO
V
DDO
Qx
LVCMOS
GND
VDDO
2
-1.25V 5ꢀ
-0.9V 0.1V
1.8V Core/1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
1.6V 5ꢀ
2.4V 0.9V
0.9V 0.1V
0.9V 0.1V
SCOPE
SCOPE
V
V
DD
DD
V
V
DDO
DDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
VDDO
2
VDDO
2
-0.9V 0.1V
-0.9V 0.1V
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
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8312I Datasheet
Parameter Measurement Information, continued
Part 1
Part 2
VDDO
VDDO
2
Qx
Qy
2
Qx
Qy
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
Output Skew
Part-to-Part Skew
VDDO
2
VDDO
VDDO
2
2
Q0:Q11
VDD
2
VDD
2
tPW
CLK
tPERIOD
VDDO
2
VDDO
2
tPW
tPERIOD
Q0:Q11
odc =
tpLH
tpHL
Propagation Delay
Output Duty Cycle/Pulse Width/Period
80ꢀ
tF
80ꢀ
tR
20ꢀ
20ꢀ
Q0:Q11
Output Rise/Fall Time
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8312I Datasheet
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins:
LVCMOS Outputs:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
All unused LVCMOS output can be left floating. There should be
no trace attached.
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8312I Datasheet
Reliability Information
Table 6. JA vs. Air Flow Table for a 32 Lead LQFP
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for 8312I is: 339
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8312I Datasheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 7. Package Dimensions for 32 Lead LQFP
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
D1 & E1
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
D2 & E2
e
L
0.45
0°
0.75
7°
ccc
N
0.10
32
Reference Document: JEDEC Publication 95, MS-026
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8312I Datasheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
8312AYILF
8312AYILFT
Marking
ICS8312AYILF
ICS8312AYILF
Package
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Temperature
-40C to 85C
-40C to 85C
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8312I Datasheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
9
12
Features section - added lead-free bullet.
Added Recommendations for Unused Input & Output Pins section.
Ordering Information Table - added Lead-Free part number, marking and note.
A
6/28/06
T8
T5A - T5F
7 - 9
10
Added Additive Phase Jitter specs to AC Tables.
Added Additive Phase Jitter Plot.
B
B
B
6/6/08
11/4/14
12/14/15
Updated datasheet to new format.
1
16
Updated Datasheet format
Ordering Information - removed leaded devices - PDN CQ-13-02 expired.
8
1
16
Removed HiPerClockS from the description section.
Removed LF note below the Ordering information table.
Updated datasheet header and footer.
©2015 Integrated Device Technology, Inc
17
December 14, 2015
8312I Datasheet
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DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2015 Integrated Device Technology, Inc. All rights reserved.
8312I_15 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 8312L | EBMPAPST | DC axial compact fan | 获取价格 |
|
| 8312M | EBMPAPST | DC axial compact fan | 获取价格 |
|
| 8313 | FILTRAN | RJ-45 Connector with CMC | 获取价格 |
|
| 83139-001 | AMPHENOL | Interconnection Device | 获取价格 |
|
| 8313FF | APITECH | RF Connector Adapter, BNC-SMA, Female-Female, ROHS COMPLIANT | 获取价格 |
|
| 8313MF | APITECH | RF Connector Adapter, BNC-SMA, Male-Female, ROHS COMPLIANT | 获取价格 |
|
| 8313MM | APITECH | RF Connector Adapter, BNC-SMA, Male-Male, ROHS COMPLIANT | 获取价格 |
|
| 8314 | EBMPAPST | DC axial compact fan | 获取价格 |
|
| 83143 | VISHAY | High Intensity SMD LED | 获取价格 |
|
| 8314G | EBMPAPST | DC axial compact fan | 获取价格 |
|
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