8305AGIT [IDT]
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| 型号： | 8305AGIT |
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INTEGRATED DEVICE TECHNOLOGY |
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8305
General Description
Features
The ICS8305 is a low skew, 1-to-4, Differential/
• Four LVCMOS / LVTTL outputs, 7Ω output impedance
S
IC
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockS™family of High
Performance Clock Solutions from IDT. The
ICS8305 has selectable clock inputs that accept
• Selectable differential or LVCMOS / LVTTL clock inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS,
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A
separate output enable pin controls whether the outputs are in the
active or high impedance state.
LVTTL
• Maximum output frequency: 350MHz
• Output skew: 35ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
Guaranteed output and part-to-part skew characteristics make the
ICS8305 ideal for those applications demanding well defined
performance and repeatability.
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
GND
OE
VDD
1
2
16 Q0
Pullup
CLK_EN
D
15
VDDO
Q1
GND
Q2
Q
14
13
3
4
LE
CLK_EN
CLK
nCLK
Pulldown
LVCMOS_CLK
0
12
11
10
9
5
6
7
8
Q0
Pulldown
Pullup/
Pulldown
VDDO
Q3
CLK
nCLK
1
CLK_SEL
LVCMOS_CLK
GND
Q1
Q2
Q3
Pullup
Pullup
CLK_SEL
ICS8305
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
G Package
OE
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power
Input
Input
Input
Power supply ground
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
2
3
4
5
6
OE
VDD
Pullup
Power supply pin.
Synchronizing clock enable. When LOW, the output clocks are disabled.
When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.
CLK_EN
CLK
Pullup
Pulldown Non-inverting differential clock input.
Pullup/
nCLK
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Pullup
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,
selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.
7
8
CLK_SEL
Input
Input
LVCMOS_CLK
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7Ω output impedance.
LVCMOS/LVTTL interface levels.
10, 12, 14, 16
11, 15
Q3, Q2, Q1, Q0 Output
VDDO Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Power Dissipation Capacitance
(per output)
CPD
11
7
pF
ROUT
Output Impedance
Ω
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Function Tables
Table 3. Control Input Function Table
Inputs
Outputs
Q0:Q3
OE
1
CLK_EN
CLK_SEL
Selected Source
LVCMOS_CLK
CLK/nCLK
0
0
1
1
X
0
1
0
1
X
Disabled; Low
Disabled; Low
Enabled
1
1
LVCMOS_CLK
CLK/nCLK
1
Enabled
0
Hi-Z
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
Enabled
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Q0:Q3
Figure 1. CLK_EN Timing Diagram
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 3.3V 5% or 2.5V 5% or 1.8V 0.5V or 1.5V 5%,
TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
3.135
2.375
1.65
Typical
3.3
Maximum
3.465
3.465
2.625
1.95
Units
V
VDD
Positive Supply Voltage
3.3
V
2.5
V
VDDO
Output Supply Voltage
1.8
V
1.425
1.5
1.575
21
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDO
5
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Table 4B. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
2
Input High
Voltage
VIH
2
V
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
-0.3
-0.3
V
Input Low
Voltage
VIL
1.3
V
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
5
µA
µA
µA
µA
V
Input
IIH
High Current
150
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
-150
-5
Input
IIL
Low Current
V
DD = 3.465V, VIN = 0V
VDDO = 3.3V 5%
VDDO = 2.5V 5%
2.6
1.8
V
VOH
Output High Voltage; NOTE 1
VDDO = 1.8V 0.15V
1.5
V
VDDO = 1.5V 5%
VDDO = 3.3V 5%
VDDO - 0.3
V
0.5
0.5
V
VDDO = 2.5V 5%
V
VOL
Output Low Voltage; NOTE 1
VDDO = 1.8V 0.15V
VDDO = 1.5V 5%
0.4
V
0.35
V
IOZL
IOZH
Output Hi-Z Current Low
Output Hi-Z Current High
-5
µA
µA
5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
Table 4C. Differential DC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
nCLK
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
IIH
Input High Current
150
nCLK
CLK
V
-150
-5
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V .
IH
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0°C to 70°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Propagation
Delay,
Low to High
tpLH
1.75
2.75
ns
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
35
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
700
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time; NOTE 4
20% to 80%
Ref = CLK/nCLK
100
45
700
55
55
5
ps
%
Output Duty Cycle
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
45
%
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
All parameters measured at IJ 350MHz unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C to 70°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Propagation
Delay,
Low to High
tpLH
1.8
2.9
ns
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
35
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
800
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time; NOTE 4
20% to 80%
Ref = CLK/nCLK
100
44
700
56
56
5
ps
%
Output Duty Cycle
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
44
%
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
For NOTES, see Table 5A above.
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Table 5C. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.15V, TA = 0°C to 70°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Propagation
Delay,
Low to High
tpLH
1.95
3.65
ns
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
35
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
900
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time; NOTE 4
20% to 80%
Ref = CLK/nCLK
100
44
700
56
56
5
ps
%
Output Duty Cycle
Ref = LVCMOS_CLK, ƒ ≤ 300MHz
44
%
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
All parameters measured at IJ 350MHz unless noted otherwise.
NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.5V 5%, TA = 0°C to 70°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
LVCMOS_CLK;
NOTE 1A
CLK/nCLK;
NOTE 1B
Propagation
Delay,
Low to High
tpLH
2
4
ns
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
35
1
ps
ns
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time; NOTE 4
20% to 80%
ƒ ≤ 166MHz
ƒ> 166MHz
200
45
900
55
58
5
ps
%
Output Duty Cycle
42
%
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
For NOTES, see Table 5C above.
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
-20
Additive Phase Jitter at 155.52MHz
= 0.04ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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Parameter Measurement Information
2.05V 5%
1.65V 5%
1.25V 5%
SCOPE
SCOPE
V
V
DD,
DD
V
DDO
V
DDO
Qx
Qx
LVCMOS
GND
LVCMOS
CL ≤ 25pF*
*For tR/tF measurement only
-1.65V 5%
-1.25V 5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.4V 0.09V
2.55V 5%
0.75V 5%
0.9V 0.075V
SCOPE
SCOPE
V
DD
V
DD
V
DDO
V
DDO
Qx
Qx
GND
GND
LVCMOS
LVCMOS
-0.9V 0.075V
-0.9V 0.75V
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/1.5V LVCMOS Output Load AC Test Circuit
V
DD
VCCO
2
Qx
nCLK
VPP
VCMR
Cross Points
VCCO
CLK
2
Qy
tsk(b)
GND
Differential Input Level
Output Skew
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Parameter Measurement Information, continued
VDDO
Part 1
2
VDDO
2
Q0:Q3
Qx
Qy
tPW
tPERIOD
Part 2
VDDO
tPW
2
x 100%
odc =
tsk(pp)
tPERIOD
Part-to-Part Skew
Output Duty Cycle/Pulse Width/Period
VDDO
2
LVCMOS_CLK
80%
tF
nCLK
CLK
80%
tR
20%
20%
Clock
Outputs
VDDO
2
Q0:Q3
➤
tPD
➤
Output Rise/Fall Time
Propagation Delay
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Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS_CLK Input
LVCMOS Outputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the LVCMOS_CLK input to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
HiPerClockS
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
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Schematic Example
This application note provides general design guide using
ICS8305 LVCMOS buffer. Figure 4 shows a schematic example of
the ICS8305 LVCMOS clock buffer. In this example, the input is
driven by an LVCMOS driver. CLK_EN is set at logic low to select
LVCMOS_CLK input.
VDD
Zo = 50
VDD
R1
43
R4
1K
R5
1K
U1
1
16
15
14
13
12
GND
Q0
VDDO
Q1
VDD
2
3
4
5
6
7
8
LVCMOS Receiver
OE
VDD
CLK_EN
CLK
GND
Q2
Zo = 50
Zo = 50
11
10
9
R2
43
nCLK
VDDO
Q3
Ro
~
7
Ohm
CLK_SEL
LVCMOS_CLK
GND
R3
43
R6
1K
ICS8305
3,.3V LVCMOS
(U1,3)
(U1,11)
C2
(U1,15)
VDD
C1
0.1u
LVCMOS Receiver
C3
VDD=3.3V
0.1u
0.1u
Figure 4. ICS8305 LVCMOS Clock Output Buffer Schematic Example
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Reliability Information
Table 6. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8305: 459
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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Ordering Information
Table 8. Ordering Information
Part/Order Number
8305AG
8305AGT
8305AGLF
8305AGLFT
Marking
8305AG
8305AG
8305AGLF
8305AGLF
Package
16 Lead TSSOP
16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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Revision History Sheet
Rev
Table
Page
Description of Change
Date
T8
14
Ordering Information table - corrected Part/Order Number typo from
ICS88305AGT to ICS8305AGT.
A
1/20/04
T5A - T5C
T1
5 & 6
7
Added Additive Phase Jitter to AC Characteristics Tables.
Added Additive Phase Jitter Section.
B
B
2/26/04
12/6/04
2
1
Pin Description Table - corrected CLK_EN description.
Features Section - added 1.5V output to Supply Mode bullet and
added Lead-Free buttlet.
T4A
T4B
T5D
4
4
7
10
11
16
Power Supply DC Characteristics Table - added VDDO 1.5V.
LVCMOS DC Characteristics Table - added VOH/VOL 1.5V.
Added 3.3V/1.5V AC Characteristics Table.
Added 3.3V/1.5V Output Load AC Test Circuit Drawing.
Added Recommendations for Unused Input and Output Pins.
Added Lead-Free part number.
C
C
11/17/05
2/22/08
T8
T8
15
Ordering Information Table - added lead-free marking.
Corrected non-lead free marking from ICS8305AG to 8305AG.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS8305AG REV. C OCTOBER 23, 2008
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LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters Asia
Japan
Europe
Integrated Device Technology, Inc. Integrated Device Technology NIPPON IDT KK
IDT Europe, Limited
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
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Sanbancho Tokyu, Bld. 7F,
8-1 Sanbancho
Chiyoda-ku, Tokyo 102-0075 KT22 7TU
321 Kingston Road
Leatherhead, Surrey
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Kolam Ayer Industrial Park
Singapore 349276
800 345 7015
+81 3 3221 9822
England
+408 284 8200 (outside U.S.)
+65 67443356
Fax: +65 67441764
Fax: +81 3 3221 9824
+44 (0) 1372 363 339
Fax: +44 (0) 1372 37885
idteurope@idt.com
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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Printed in USA
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