77252L155DUI [IDT]
ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208;
| 型号： | 77252L155DUI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总17页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT77252
155 Mbps ATM SAR Controller
With ABR Support for PCI-based
Networking Applications
◆
Utility Bus Interface for PHY Management
ꢀꢁꢂꢃꢄꢅꢆꢂꢇ
◆
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Serial EEPROM Interface
EPROM Interface
Full-duplex Segmentation and Reassembly (SAR) at 155
Mbps "wire-speed" (310 Mbps aggregate speed)
Operates with ATM Networks up to 155.52 Mbps
Stand-alone Controller: Embedded Processor not required
Performs ATM Layer Protocol Functions
◆
◆
◆
◆
◆
PCI 2.1 Compliant
UNI 3.1, TM 4.0 Compliant
Meets PCI Bus Power Management and Interface
Specification Revision 1.1
Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats
◆
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◆
Pin Compatible with IDT 77211 SAR
Commercial and Industrial Temperature Ranges
208-Lead PQFP Package (28 x 28mm)
Software Drivers:
Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR),
and Unassigned Bit Rate (UBR), and Available Bit Rate
(ABR) Service Classes
◆
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Segments and Reassembles CS-PDUs into Host Memory
Up to 16K Open Transmit Connections
Up to 16K Simultaneous Receive Connections
ABR, VBR, UBR Selectable per VC Time-out
Automatic AAL5 Padding
–
SARWIN 2 Demonstration Program
NDIS Driver
Vx Works (3rd party)
Linux (3rd party)
–
–
–
Four Buffer Pools for Independent or Chained Reassembly
Supports Any Buffer Alignment Condition
Free Buffer Queues Mapped Into PCI Memory Space
Rx FIFO Size (Configurable to 1024 Kbytes)
Configurable Transmit FIFO Depth for Reduced Latency
Supports Big and Little Endian Data Transfers
Null Cell Disable Option During Transmit
NAND Test Mode
ꢈꢂꢇꢉꢆꢊꢋꢄꢊꢌꢍ
™
The IDT77252 NICStAR is a member of IDT's family of products for
Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs
both the ATM Adaptation Layer (AAL) Segmentation and Reassembly
(SAR) function and the ATM layer protocol functions.
A Network Interface Card (NIC) or internetworking product based on
the ABR SAR uses host memory, rather than local memory, to reas-
semble Convergence Sublayer Protocol Data Units (CS-PDUs) from
ATM cell payloads received from the network. When transmitting, as CS-
PDUs become ready, they are queued in host memory and segmented
RM Cell Handling
UTOPIA Level 1 Interface to PHY
ꢎꢏꢇꢄꢂꢐꢑꢒꢂꢓꢂꢔꢀꢁꢅꢍꢉꢄꢊꢌꢍꢃꢔꢀꢕꢔꢌꢉꢖꢀꢈꢊꢃꢗꢆꢃꢐ
16K x 32 to 512K x 32
EPROM
SRAM
PCI BUS
8
32
Rx UTOPIA Bus
8
2
155Mbps
IDT77252
155Mbps
PCI ATM
ABR SAR
33MHZ
Tx UTOPIA Bus
PHY
8
2
32
Utility Bus
8
80.0MHZ OSC.
EEPROM
4057 drw 01
1 of 17
March 26, 2001
DSC 4057/8
2001 Integrated Device Technology, Inc.
IDT77252
by the ABR SAR into ATM cell payloads. From this, the ABR SAR then creates complete 53-byte ATM cells which are sent through the network. The
ABR SAR's on-chip PCI bus master interface provides efficient, low latency DMA transfers with the host system, while its UTOPIA interface provides
direct connection to PHY components used in 25.6 Mbps to 155 Mbps ATM networks.
The IDT77252 is fabricated using state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the
low-power consumption characteristics of CMOS.
ꢕꢔꢌꢉꢖꢀꢈꢊꢃꢗꢆꢃꢐꢀꢌꢘꢀꢄꢙꢂꢀꢚꢚꢛꢜꢛꢀꢝꢕꢞꢀꢎꢝꢞ
T x
8
/
Transmit
Control
Tx Utopia
Bus
Utopia
Interface
32
/
S R A M
Bus
SRAM INTERFA CE
PCI
32
/
PCI Bus
Interface
Rx
Receive
Control
Rx Utopia
Bus
8
/
Utopia
Interface
8
/
U tility
EEPROM OUT
EEPROM IN
4057 drw 02
ꢃꢉꢖꢃꢗꢂꢀ ꢊꢍꢌꢅꢄ
208 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5
Vcc
1
GND
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7
AD(31)
AD(30)
AD(29)
AD(28)
AD(27)
AD(26)
GND
2
PHY_INT
PHY_RST
UTL_ALE
Index
3
4
5
UTL_RD
UTL_WR
GND
6
7
8
UTL_AD(7)
UTL_AD(6)
UTL_AD(5)
UTL_AD(4)
Vcc
GND
AD(25)
AD(24)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
C/BE(3)
IDSEL
AD(23)
AD(22)
GND
GND
AD(21)
Vcc
UTL_AD(3)
GND
UTL_AD(2)
UTL_AD(1)
UTL_AD(0)
Vcc
SAR_CLK
GND
AD(20)
AD(19)
AD(18)
AD(17)
AD(16)
GND
EEDO
IDT77252 SAR Controller
With ABR Support
208 Pin PQFP
Pinout
EEDI
EESCLK
EECS
Vcc
GND
E_CE
C/BE(2)
Vcc
SR_I/O(31)
SR_I/O(30)
SR_I/O(29)
GND
PU-208
DUI-208
FRAME
IRDY
TRDY
DEVSEL
STOP
GND
SR_I/O(28)
SR_I/O(27)
SR_I/O(26)
SR_I/O(25)
SR_I/O(24)
Vcc
Refer to PSC-4053 for
detailed package drawing
GND
INTA
Vcc
SR_I/O(23)
GND
PERR
SERR
SR_I/O(22)
SR_I/O(21)
SR_I/O(20)
SR_I/O(19)
SR_I/O(18)
SR_I/O(17)
GND
PAR
C/BE(1)
AD(15)
GND
GND
AD(14)
AD(13)
AD(12)
AD(11)
AD(10)
AD(9)
AD(8)
GND
SR_I/O(16)
SR_I/O(15)
SR_I/O(14)
SR_I/O(13)
SR_I/O(12)
SR_I/O(11)
Vcc
1 1 1 1 1
0 0 0 0 0
0 1 2 3 4
5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9
3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
4057 drw 03
2 of 17
March 26, 2001
IDT77252
ꢃꢉꢖꢃꢗꢂꢀꢈꢆꢃ!ꢊꢍꢗ
1.228 ±0.016 (31.2 ±0.4)
1.10 ±0.004 (28.0 ±0.1)
208
157
Index
1
156
0.02 ±0.004
(0.5 ±0.1)
0.008 ±0.004
(0.2 ±0.1)
105
52
104
53
0.133 ±0.004
(3.37 ±0.1)
0.013 ±0.002
(0.33 ±0.06)
0.024 ±0.008
(0.6 ±0.2)
0.063 (1.6)
4057 drw 04
ꢊꢍꢀꢈꢂꢘꢊꢍꢊꢄꢊꢌꢍꢇ
1
VCC
I
power
PCI
2
AD(31)
AD(30)
AD(29)
AD(28)
AD(27)
AD(26)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
3
PCI
4
PCI
5
PCI
6
PCI
7
PCI
8
power
power
PCI
9
GND
I
10
11
12
13
AD(25)
AD(24)
C/BE(3)
IDSEL
I/O
I/O
I/O
I
address/data line
address/data line
bus command
bus ID select
PCI
PCI
PCI
3 of 17
March 26, 2001
IDT77252
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
AD(23)
AD(22)
GND
I/O
I/O
I
PCI
address/data line
address/data line
PCI
power
power
PCI
GND
I
AD(21)
VCC
I/O
I
address/data line
power
PCI
AD(20)
AD(19)
AD(18)
AD(17)
AD(16)
GND
I/O
I/O
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
address/data line
address/data line
PCI
PCI
PCI
PCI
power
power
PCI
GND
I
C/BE(2)
VCC
I/O
I
bus command
power
PCI
Frame
IRDY
TRDY
DEVSEL
STOP
GND
I/O
I/O
I/O
I/O
I/O
I
cycle frame
PCI
initiator ready
PCI
target ready
PCI
target indicating address decode
target requesting master to stop
PCI
power
power
PCI
GND
I
INTA
O
"interrupt" "A" "request"
VCC
I
power
PCI
PERR
SERR
PAR
I/O
O
data parity error
PCI
system error
I/O
I/O
I/O
I
PCI
parity (for AD[0:31] and C/BE[0:3])
bus command
C/BE(1)
AD(15)
GND
PCI
PCI
address/data line
power
power
PCI
GND
I
AD(14)
AD(13)
AD(12)
AD(11)
AD(10)
AD(9)
AD(8)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
PCI
PCI
PCI
PCI
PCI
PCI
power
4 of 17
March 26, 2001
IDT77252
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
VCC
I
power
power
PCI
GND
I
C/BE(0)
AD(7)
I/O
I/O
I
bus command
PCI
address/data line
VCC
power
PCI
AD(6)
I/O
I/O
I/O
I
address/data line
address/data line
address/data line
AD(5)
PCI
AD(4)
PCI
GND
power
SRAM
PCI
SR_A17
AD(3)
O
I/O
I/O
I/O
I/O
I
Address line
address/data line
address/data line
address/data line
address/data line
AD(2)
PCI
AD(1)
PCI
AD(0)
PCI
GND
power
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
SRAM
power
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
SR_A15
SR_WE
SR_A13
SR_A8
SR_A9
SR_A11
SR_OE
SR_A10
SR_CS
SR_A16
GND
O
O
O
O
O
O
O
O
O
O
I
Address line
Write enable
Address line
Address line
Address line
Address line
Output Enable control
Address line
Chip Select
Address line
SR_A14
VCC
O
I
Address line
SR_A12
SR_A7
SR_A6
SR_A5
SR_A4
SR_A3
SR_A2
SR_A1
SR_A0
SR_A18
GND
O
O
O
O
O
O
O
O
O
O
I
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
Address line
5 of 17
March 26, 2001
IDT77252
92
SR_I/O(0)
SR_I/O(1)
SR_I/O(2)
SR_I/O(3)
SR_I/O(4)
SR_I/O(5)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
93
94
95
96
97
98
99
SR_I/O(6)
SR_I/O(7)
SR_I/O(8)
SR_I/O(9)
SR_I/O(10)
GND
I/O
I/O
I/O
I/O
I/O
I
SRAM
SRAM
SRAM
SRAM
SRAM
power
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
VCC
I
power
SR_I/O(11)
SR_I/O(12)
SR_I/O(13)
SR_I/O(14)
SR_I/O(15)
SR_I/O(16)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
SR_I/O(17)
SR_I/O(18)
SR_I/O(19)
SR_I/O(20)
SR_I/O(21)
SR_I/O(22)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
power
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
SR_I/O(23)
VCC
I/O
I
SRAM
power
Data input/output line
SR_I/O(24)
SR_I/O(25)
SR_I/O(26)
SR_I/O(27)
SR_I/O(28)
GND
I/O
I/O
I/O
I/O
I/O
I
SRAM
SRAM
SRAM
SRAM
SRAM
power
Data input/output line
Data input/output line
Data input/output line
Data input/output line
Data input/output line
SR_I/O(29)
SR_I/O(30)
SR_1/O(31)
I/O
I/O
I/O
SRAM
SRAM
SRAM
Data input/output line
Data input/output line
Data input/output line
6 of 17
March 26, 2001
IDT77252
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
E_CE
O
I
EPROM
power
EPROM chip select
VCC
EECS
O
O
I
EEPROM
EEPROM
EEPROM
EEPROM
power
chip select
clock
EESCLK
EEDI
Data input
Data output
EEDO
O
I
GND
SAR_CLK
VCC
I
SAR clock input
I
power
Utility
UTL_AD(0)
UTL_AD(1)
UTL_AD(2)
GND
I/O
I/O
I/O
I
address/data bus
address/data bus
address/data bus
Utility
Utility
power
Utility
UTL_AD(3)
VCC
I/O
I
address/data bus
power
Utility
UTL_AD(4)
UTL_AD(5)
UTL_AD(6)
UTL_AD(7)
GND
I/O
I/O
I/O
I/O
I
address/data bus
address/data bus
address/data bus
address/data bus
Utility
Utility
Utility
power
Utility
UTL_WR
UTL_RD
UTL_ALE
PHY_RST
PHY_INT
GND
O
O
O
O
I
write control
Utility
read control
Utility
address latch enable
rest control
PHY
PHY
interrupt input from PHY
I
power
power
Utility
VCC
I
UTL_CS(0)
UTL_CS(1)
TxData(0)
TxData(1)
TxData(2)
TxData(3)
GND
O
O
O
O
O
O
I
chip select (0)
Utility
chip select (1)
UTOPIA
UTOPIA
UTOPIA
UTOPIA
power
UTOPIA
UTOPIA
power
UTOPIA
UTOPIA
transmit data bit 0
transmit data bit 1
transmit data bit 2
transmit data bit 3
TxData(4)
TxData(5)
VCC
O
O
I
transmit data bit 4
transmit data bit 5
TxData(6)
TxData(7)
O
O
transmit data bit 6
transmit data bit 7
7 of 17
March 26, 2001
IDT77252
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
I
power
TxSOC
TxEnb
O
O
I
UTOPIA
UTOPIA
UTOPIA
UTOPIA
power
transmit start of cell
transmit enable control
transmit buffer full
TxFull/TxCLAV
TxCLK
GND
O
I
transmit data sync clock
RxData(0)
RxData(1)
RxData(2)
RxData(3)
GND
I
UTOPIA
UTOPIA
UTOPIA
UTOPIA
power
receive data bit 0
receive data bit 1
receive data bit 2
receive data bit 3
I
I
I
I
RxData(4)
RxData(5)
RxData(6)
RxData(7)
RxSOC
RxEnb
I
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
power
receive data bit 4
receive data bit 5
receive data bit 6
receive data bit 7
receive start of cell
receive enable control
receive buffer empty
I
I
I
I
O
I
RxEmpty/RxCLAV
GND
I
RxClk
O
I
UTOPIA
UTOPIA
UTOPIA
power
receive data sync clock
Transmit sync clock input
transmit data parity bit
PHY_Clk
TxParity
GND
O
I
NAND_OUT
GND
O
I
power
NAND output chain
power
ADD17_18_EN
VCC
I
power
enables or tristates SR_A17 and SR_A18
I
power
VCC
I
power
CLK_OUT
GND
O
I
power
SAR_Clk divided by 3
NAND input chain
power
GND
I
power
NAND_EN
GND
I
power
I
power
RST
I
PCI
system bus reset
bus clock
CLK
I
PCI
GNT
I
PCI
bus grant signal from arbiter
bus request
REQ
O
I
PCI
VCC
power
GND
I
power
8 of 17
March 26, 2001
IDT77252
ꢝ"ꢇꢌꢔꢅꢄꢂꢀ#ꢃ$ꢊꢐꢅꢐꢀꢞꢃꢄꢊꢍꢗꢇ
VCC
VIN
Supply Voltage
-0.3
6.5
V
Input Voltage
VSS - 0.3 VCC + 0.3
VSS - 0.3 VCC + 0.3
V
VOUT
Tstg
Output Voltage
V
Storage Temperature
-55
125
deg.C
ꢞꢂꢉꢌꢐꢐꢂꢍ%ꢂ%ꢀ&ꢋꢂꢆꢃꢄꢊꢍꢗꢀ'ꢌꢍ%ꢊꢄꢊꢌꢍꢇ
VCC
VI
Supply Voltage
4.75
0
5.25
VCC
70
85
2
V
Input Voltage
V
TA1
TA2
titr
Commercial Operating temperature
Industrial Operating temperature
Input TTL rise time
0
deg.C
deg.C
ns
-40
—
—
titf
Input TTL fall time
2
ns
'ꢔꢌꢉꢖꢊꢍꢗ
SAR_CLK
PHY_CLK
PCI_CLK
SAR clock input freq.
PHY clock input freq.
PCI clock input freq.
155Mb/s
25Mb/s
155Mb/s
25Mb/s
33MHz
77
25
19.44
3
80
MHz
MHz
MHz
MHz
MHz
80
40
40
0
33.3
'ꢃꢋꢃꢉꢊꢄꢃꢍꢉꢂ
CIN
Input Capacitance
Output Capacitance
except PCI Bus
all outputs
—
—
—
—
5
—
4
pF
pF
pF
pF
pF
pF
COUT
Cbid
—
—
10
12
8
6
Bi-Directional Capacitance
all bi-directional pins
10
—
—
—
Cinpci
Cclkpci
Cidsel
PCI Bus Input Capacitance
PCI Bus inputs
PCI Bus Clock Input Capacitance
PCI Bus ID Select Input Capacitance
—
—
—
ꢈ'ꢀ&ꢋꢂꢆꢃꢄꢊꢍꢗꢀ'ꢌꢍ%ꢊꢄꢊꢌꢍꢇ
Vil
Low-level TTL input voltage
—
-0.7V
2
0.8
—
—
—
—
—
V
V
V
V
V
Vih
Vol
Vol
Voh
High-level TTL input voltage
Low-level TTL output voltage
PCI Bus Low-level TTL output voltage
High-level TTL output voltage
—
VCC + 0.2V
0.4
except PCI Bus
PCI Bus voltage
—
—
—
0.55
2.4
—
9 of 17
March 26, 2001
IDT77252
Iol
Ioh
Iol
Low-level TTL output current:
SR_A(18-0)
VSS + 0.4V
2.4V
12
-4
6
—
—
—
—
—
—
mA
mA
mA
High-level TTL output current:
SR_A(18-0)
Low-level TTL output current:
VSS + 0.4V
RxEnb, RxClk, TxSOC, TxData (7-0), TxEnb, TxParity,
TxClk, WE#, OE#, CS#, SR_D31-0
Ioh
Iol
High-level TTL output current:
RxEnb#, RxClk, TxSoc, TxData7-0, TxEnb#, TxParity,
TxClk, SR_WE, SR, OE, SR_CS, SR_I/O(31-0)
2.4V
-2
3
—
—
—
—
—
—
mA
mA
mA
Low-level TTL output current:
UTL_AD(7-0), UTL_RD, UTL_WR, UTL_ALE,
UTL_CS0/1, EESCLK, EECS, EEDO, PHY_RST
VSS + 0.4V
2.4V
Ioh
High-level TTL output current:
-1
UTL_AD(7-0), UTL_RD, UTL_WR, UTL_ALE,
UTL_CS0/1, EESCLK, EECS, EEDO, PHY_RST
Iil
Input leakage current
VSS ≤ VIN ≤ Vdd
-1
1
—
uA
Ityp
Dynamic Supply Current
—
—
300
250
mA
ꢝ'ꢀ&ꢋꢂꢆꢃꢄꢊꢍꢗꢀ'ꢌꢍ%ꢊꢄꢊꢌꢍꢇ
Input Pulse Levels
Input Rise/Fall Times
Input Timing Ref. Level 1.5V
0 to 3.0V
2ns
Output Ref. Level
AC Test Load
1.5V
See Figure Below
Table 1 AC Test Conditions
6
5
4
3
1.5V
50
Ω
tCD
∆
(Typical, ns)
I/O
Z0 = 50
Ω
2
1
20 30 50
80 100
Capacitance (pF)
200
4057 drw 05
(ꢝ(ꢈꢀ)ꢆꢂꢂ
The NAND Chain provides a simple test to verify that all bond wires are installed correctly and that all pads are correctly soldered on a PCB.
All signal pads are linked in a NAND chain, which is enabled by asserting a high, or “1”, on NAND_EN (pin 201). Asserting a “1” on the other inputs
forces NAND_OUT (pin 193) to “1”. By successively setting the inputs to “0”, starting at CLK_OUT (pin 198) and moving to TXPARITY (pin 191),
NAND_OUT will toggle with each change.
1. Apply a "1" to NAND_EN.
2. Set all the I/O's in the chain to "0" and NAND_OUT should be a "1".The connection order of the pins in the chain are shown in the NAND Tree
Pin Order table located on the following page.
3. Set CLK_OUT to a "0" and the NAND_OUT should be a "0".
4. Leaving pin 198 at a "1" set RST (pin 203) to "1" and NAND_OUT should be a "1".
5. Repeat for all remaining I/O's in the NAND chain.
10 of 17
March 26, 2001
IDT77252
CLK_OUT
RST
198
203
204
205
206
2
AD[12]
47
48
49
50
51
55
56
58
59
60
63
64
65
66
69
70
71
72
73
74
75
76
81
82
83
84
85
86
87
88
89
92
93
94
95
96
97
SR_I/O[06]
SR_I/O[07]
SR_I/O[08]
SR_I/O[09]
SR_I/O[10]
SR_I/O[11]
SR_I/O[12]
SR_I/O[13]
SR_I/O[14]
SR_I/O[15]
SR_I/O[16]
SR_I/O[17]
SR_I/O[18]
SR_I/O[19]
SR_I/O[20]
SR_I/O[21]
SR_I/O[22]
SR_I/O[23]
SR_I/O[24]
SR_I/O[25]
SR_I/O[26]
SR_I/O[27]
SR_I/O[28]
SR_I/O[29]
SR_I/O[30]
SR_I/O[31]
E_CE
99
UTL_AD[5]
UTL_AD[6]
UTL_AD[7]
UTL_WR
UTL_RD
UTL_ALE
PHY_RST
PHY_INT
UTL_CS[0]
UTL_CS[1]
TxData[0]
TxData[1]
TxData[2]
TxData[3]
TxData[4]
TxData[5]
TxData[6]
TxData[7]
TxSOC
147
148
149
151
152
153
154
155
158
159
160
161
162
163
165
166
168
169
171
172
173
174
176
177
178
179
181
182
183
184
185
186
187
189
190
191
AD[11]
100
101
102
103
106
107
108
109
110
111
113
114
115
116
117
118
120
122
123
124
125
126
128
129
130
131
133
134
135
136
138
140
141
142
144
146
CLK
AD[10]
GNT
AD[9]
REQ
AD[8]
AD[31]
AD[30]
AD[29]
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
C/BE[3]
IDSEL
AD[23]
AD[22]
AD[21]
AD[20]
AD[19]
AD[18]
AD[17]
AD[16]
C/BE[2]
Frame
IRDY
C/BE[0]
AD[7]
3
4
AD[6]
5
AD[5]
6
AD[4]
7
AD[3]
10
11
12
13
14
15
18
20
21
22
23
24
27
29
30
31
32
33
36
38
39
40
41
42
45
46
AD[2]
AD[1]
AD[0]
SR_WE
SR_A[13]
SR_A[8]
SR_A[9]
SR_A[11]
SR_OE
SR_A[10]
SR_CS
TxEnb
TxCLAV
TxCLK
SR_A[12]
SR_A[7]
SR_A[6]
SR_A[5]
SR_A[4]
SR_A[3]
SR_A[2]
SR_A[1]
SR_A[0]
SR_I/O[00]
SR_I/O[01]
SR_I/O[02]
SR_I/O[03]
SR_I/O[04]
SR_I/O[05]
RxData[0]
RxData[1]
RxData[2]
RxData[3]
RxData[4]
RxData[5]
RxData[6]
RxData[7]
RxSOC
TRDY
DEVSEL
STOP
EECS
EESCLK
INITA
EEDI
PERR
SERR
PAR
EEDO
SAR_CLK
UTL_AD[0]
UTL_AD[1]
UTL_AD[2]
UTL_AD[3]
UTL_AD[4]
RxEnb
RxCLAV
RxCLK
C/BE[1]
AD[15]
AD[14]
AD[13]
PHY_CLK
TxParity
Table 2 NAND Tree Pin Order
11 of 17
March 26, 2001
IDT77252
'*ꢀꢕꢅꢇꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀ,ꢀꢃꢍ%ꢀꢛ-
tval
CLK to Output Signal Valid Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
2
11
12
—
28
—
—
—
—
—
40
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tval(ptp)
ton
CLK to Output Signal Valid Delay: REQ
2
Float to Signal Active Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
Signal Active to Float Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR
Input Setup Time to CLK: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR
Input Setup Time to CLK: GNT, (REQ)
2
toff
—
7
tsu
tsu(ptp)
th
10(12)
21
Input Hold Time from CLK: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, GNT
Reset Active Time After Power Stable
trst-pwr
trst-clk
trst-off
thigh
1
Reset Active Time After CLK Stable
100
Reset Active to Output Float Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR —
Clock high time
Clock low time
11n
11n
tlow
1.
Does not meet PCI Local Bus revision 2.1 timing specification
.)& *ꢝꢀꢕꢅꢇꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀ/-
t1
t2
t3
t4
t5
t6
t7
t8
TxClk, RxClk Delay from PHY_CLK
—
1
5
ns
TxData(7-0), TxSOC, TxEnb, TxParity Output Valid from TxClk
TxFull/TxCLAV Setup Time to TxClk
15
—
—
15
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
10
31
1
TxFull/TxCLAV Hold Time from TxClk
RxEnb Output Valid from RxClk
RxData(7-0), RxSOC Setup Time to RxClk
RxData(7-0), RxSOC Hold Time from RxClk
10
21
10
21
RxEmpty/RxCLAV Setup Time to RxClk
RxEmpty/RxCLAV Hold Time from TxClk
t9
1.
Does not meet UTOPIA 1 timing specification (Af-phy-0017.00)
.ꢄꢊꢔꢊꢄꢏꢀꢕꢅꢇꢀ0ꢆꢊꢄꢂꢀ'ꢏꢉꢔꢂꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀ1-
tw1
tw2
tw3
tw4
tw5
tw6
tw7
tw8
tw9
tw10
tw11
UTL_ALE Pulse Width
25
—
—
80
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTL_CS0/1 Output Valid to UTL_ALE falling edge
UTL_WR Output Valid from UTL_ALE falling edge
UTL_CS0/1 Pulse Width
25
—
275
175
225
30
UTL_WR Pulse Width
UTL_ALE falling edge to UTL_WR rising edge
UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge
UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge
UTL_AD(7-0) Data Setup Time to UTL_WR rising edge
UTL_AD(7-0) Data Hold Time from UTL_WR rising edge
UTL_ALE falling edge to UTL_CS0/1 rising edge
10
185
10
250
12 of 17
March 26, 2001
IDT77252
.ꢄꢊꢔꢊꢄꢏꢀꢕꢅꢇꢀꢞꢂꢃ%ꢀ'ꢏꢉꢔꢂꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀꢜ-
tr1
tr2
tr3
tr4
tr5
tr6
tr7
tr8
tr9
tr10
tr11
UTL_ALE Pulse Width
25
—
—
80
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTL_CS0/1 Output Valid to UTL_ALE falling edge
UTL_RD Output Valid from UTL_ALE falling edge
UTL_CS0/1 Pulse Width
25
—
250
185
250
30
UTL_RD Pulse Width
UTL_ALE falling edge to UTL_RD rising edge
UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge
UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge
UTL_AD(7-0) Data Setup Time to UTL_CS0/1 rising edge
UTL_AD(7-0) Data Hold Time from UTL_CS0/1 rising edge
UTL_ALE falling edge to UTL_CS0/1 rising edge
10
80
10
225
ꢎꢞꢝ#ꢀꢕꢅꢇꢀ0ꢆꢊꢄꢂꢀ'ꢏꢉꢔꢂꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀ2-
t1
t2
t3
t4
t5
t6
SR_A(18-0) Setup Time to SR_WE falling edge
SR_CS falling edge to SR_WE falling edge
SR_CS pulse width
2
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
0
25
6
SR_I/O(31-0) Setup Time to SR_WE rising edge
SR_I/O(31-0) Hold Time from SR_WE rising edge
SR_WE Pulse Width
0
10
ꢎꢞꢝ#ꢀꢕꢅꢇꢀꢞꢂꢃ%ꢀ'ꢏꢉꢔꢂꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀꢚ-
t1
SR_A(18-0) to SR_I/O(31-0) Valid1
—
25
15
—
ns
ns
t2
SR_OE pulse width
1.
SR_I/O (31-0) Setup and Hold times are guaranteed by design when t1 access time is met.
3 ꢞ&#ꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀ4-
t1
t2
t3
t4
SR_I/O(7-0) Hold Time from E_CE rising edge
0
—
—
70
—
ns
ns
ns
ns
E_CE Pulse Width
75
—
75
SR_A(18-0) Change to SR_I/O(7-0) Valid
SR_A(18-0) Pulse Width
3 ꢞ&#ꢀ+ꢎꢂꢂꢀꢁꢊꢗꢅꢆꢂꢀ5-
t1
t2
t3
SAR_CLK to Output Signal Valid Delay: EECS, EEDO, EECLK 100
—
ns
ns
ns
software controlled
software controlled
software controlled
EEDI Input Setup Time to SAR_CLK
EEDI Input Hold Time from SAR_CLK
10
0
—
—
13 of 17
March 26, 2001
IDT77252
tcyc
ton
tval (ptp)
tval
tlow thigh
toff
PCI_CLK(I)
AD31-0(O)
Add
Data0
Data2
Data3
Data1
Cmd
BE3-0
C/ 3-0(O)
BE
tval
toff
FRAME(O)
IRDY(O)
ton
tval
toff
tval
tsu
DEVSEL(I)
tsu
th
tsu
TRDY(I)
REQ(O)
tval(ptp)
tval
ParD0
ton
toff
ParD3
ParA
ParD1
ParD2
PAR(O)
tsu(ptp)
GNT(I)
4057 drw 06
th
Figure 1 The ABR SAR as a PCI Master (illustrates a 4-word write by the ABR SAR to host memory)
tsu
th
PCI_CLK(1)
AD31-0(1)
Data1
BE3-0
Data0
Data2
ParD1
Data3
ParD2
Add
C/BE3-0(1)
PAR(1)
Cmd
tsu
ParA
ParD0
ParD3
th
FRAME(1)
th
tsu
IRDY(1)
toff
th
toff
DEVSEL(1)
tval,
ton
toff
TRDY(O)
PERR(O)
tval,
ton
SERR(O)
tval,
ton
REQ(1)
tsu
REQ(O)
4057 drw 07
tval
Figure 2 The ABR SAR as a PCI Target (illustrates a 4-word write operation by the host device driver to the ABR SAR)
14 of 17
March 26, 2001
IDT77252
t1
PHY_Clk(I)
t3
t7
t9
t4
t5
t6
t2
t8
TxClk,RxClk(O)
TxData 7-0(O)
TxSOC(O)
TxEnb(O)
TxParity(O)
(I)
/
Txfull
TxCLAV
RxEnb(O)
RxData 7-0(I)
RxSOC(I)
(I)
/
RxEmpty
RxCLAV
5349 drw 08
Figure 3 UTOPIA Bus Timing
tw11
tw6
tw1
tw7
tw2
tw8
tw3
UTL_ALE(O)
tw4
UTL_CS0/1(O)
UTL_WR(O)
tw5
tw10
tw9
UTL_AD(7-0)(I/O)
(O) Valid Data
Address (O)
4057 drw 09
Figure 4 Utility Bus Write Cycle
tr6
tr11
tr1
tr7
tr2
tr8
tr3
UTL_ALE
tr4
UTL_CS0/1
tr5
tr10
tr9
UTL_RD
Address (O)
(I) Valid Data
UTL_AD7-0
4057 drw 10
Figure 5 Utility Bus Read Cycle
15 of 17
March 26, 2001
IDT77252
t1
t2
SR_A(18-0)
SR_CS
t3
t6
t5
t4
SR_WE
SR_I/O(31-0)
5349 drw 11
Figure 6 SRAM Bus Write Cycle Timing
t1
SR_A(18-0)
SR_CS
t2
SR_OE
SR_I/O(31-0)
5349 drw 12
Figure 7 SRAM Bus Read Cycle Timing
t3
t4
SR-A (18-0)
t1
t2
E_CE
Valid Data
SR_I/O(7-0)
4057 drw 13
Figure 8 EPROM Timing
t1
SAR_CLK
EECS
EECLK
EEDO
t3
t2
EEDI
5349 drw 14
Figure 9 EEPROM Timing
ꢎꢌꢘꢄ!ꢃꢆꢂꢀꢃꢍ%ꢀꢎꢌꢘꢄ!ꢃꢆꢂꢀꢈꢆꢊꢓꢂꢆꢇ
Several software vendors have written IDT77252 software drivers for various operating systems. Please contact your local IDT sales representa-
tive for a vendor list, or e-mail atmhelp@idt.com.
IDT offers the Sarwin2 demo driver and application suite, which can be used to evaluate the IDT77252 when used with a IDT NIC reference or
evaluation adapter. It may also be used as a reference for sample source code when developing a proprietary device driver. Please contact your IDT
sales representative or e-mail sarhelp@idt.com to obtain a free CD-ROM.
16 of 17
March 26, 2001
IDT77252
(*'ꢀꢞꢂꢘꢂꢆꢂꢍꢉꢂꢀꢃꢍ%ꢀ3ꢓꢃꢔꢅꢃꢄꢊꢌꢍꢀꢝ%ꢃꢋꢄꢂꢆꢇ
NIC Reference and Evaluation adapters are available in several form factors. Bill of Materials (BOM) and schematics are available upon request
for each of the NIC adapters. A list of current NIC adapter offerings can be found at www.idt.com.
Note: ABR SAR User Manual provides a detailed description of the 77252 operation and registers.
&ꢆ%ꢂꢆꢊꢍꢗꢀ*ꢍꢘꢌꢆꢐꢃꢄꢊꢌꢍ
NNNNN
A
NNN
A
IDT
Device Type
Power
Speed
Package
Commerical 208-pin Plastic Quad Flatpack
Revisions A, B, C, D, E, and F
Industrial 208-pin Plastic Quad Flatpack
Revisions A, B, C, D, and E
Industrial 208-pin Plastic Quad Flatpack
Revision F
PG
PGI
DUI
155
L
Speed in Mps
Low Power CMOS
77252
155Mbs ATM Segmentation &
Reassembly (SAR) Controller for the
PCI Local Bus
4057 drw 15
Note: Refer to Errata list for revision history and how to identify revision.
Refer to PSC-4053 for detailed package drawing.
ꢞꢂꢋꢔꢃꢉꢊꢍꢗꢀꢄꢙꢂꢀꢚꢚꢛ,,ꢀ!ꢊꢄꢙꢀꢄꢙꢂꢀꢚꢚꢛꢜꢛ
The 77252 PG package is the same package as the 77211 PQF. The 77252 is a direct replacement to the 77211 SAR. To use the 77252 in a 155
Mbps application, a 80 MHz oscillator is required (replace the 50 MHz oscillator used with the 77211).
ꢈꢃꢄꢃꢀꢎꢙꢂꢂꢄꢀꢈꢌꢉꢅꢐꢂꢍꢄꢀ6ꢊꢇꢄꢌꢆꢏ
12/01/97: Created new document.
01/27/98: Corrected designation of pins 58, 75, and 90 plus made miscellaneous edits.
05/01/98: Changed package designation from PQF to PG. Added AC operating conditions. Edited timing diagrams.
08/11/98: Corrected descriptions for the following pins (pin 62, 90, 193). Edited package pin out diagram (pin 195).
07/07/99: Added Industrial Temp range.
09/15/99: Updated software section.
05/02/99: Added DUI package information, updated SRAM timing diagrams, updated Utility Bus timing diagrams, updated PCI timing parameters, updated
UTOPIA bus timing parameters, updated AC Test Conditions section, updated EEPROM timing diagrams, added NAND Tree description and pin
order, updated software section, and added NIC section.
06/22/00: Corrected Utility Bus Write, Utility Bus Read, and SRAM Write timing tables. Corrected NAND Tree pin order.
03/26/01: Changed from Preliminary to Final data sheet. Added to and rearranged the Features list.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
email:sarhelp@idt.com
phone: 408-492-8208
800-345-7015 or 408-727-6116
fax: 408-330-1748
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17 of 17
March 26, 2001
相关型号：
77252L155PG
ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208
IDT
77252L155PGI
ATM Segmentation and Reassembly Device, 1-Func, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208
IDT
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