77010L155PQFG [IDT]
ATM Network Interface, 1-Func, PQFP80, 12 X 12 X 1.40 MM, PLASTIC, QFP-80;
| 型号： | 77010L155PQFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ATM Network Interface, 1-Func, PQFP80, 12 X 12 X 1.40 MM, PLASTIC, QFP-80 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总21页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT77010
Data Path Interface (DPI) to
Utopia Level 1
Translation Device
Features
Theory of Operation
UTOPIA receive cells are transferred to the DPI-4 interface one cell
at a time. The DPI-4 clock rate is twice the frequency of receive UTOPIA
clock.
!
Single chip ATM Layer UTOPIA Level 1 to 4-bit DPI interface.
!
!
!
!
!
Supports ATM Forum UTOPIA Level 1 interface.
Supports ATM device interface in Cell mode.
Capable of full-duplex operation up-to 160 Mbps.
Utility bus interface to access PHY registers.
In-stream control to access PHY registers.
DPI-4 transmit cells are transferred to the UTOPIA transmit bus one
cell at a time. Transmit flow control is used to match the transmit cell rate
to the PHY's transmit cell rate.
Control cells are inserted and decoded by the control cell decoder.
The control cells are filtered and will not be transferred to the UTOPIA
transmit bus.
Description
The 77010 interfaces a UTOPIA PHY device to a device that uses a
Data Path Interface (DPI). Examples of PHY devices may include the
IDT77105, and the IDT77V400 Switching Memory is an example of a
component that utilizes a DPI interface. Figure 1 illustrates a typical
application using the IDT77010.
The control cell decoder block identifies the control cells and signals
the Utility Bus Interface to execute the commands. For a Utility bus write
command cell, the Utility bus does a one byte write to the specified
Utility bus address. For a Utility bus read command cell, the Utility bus
reads one byte from the specified Utility bus address and loads this byte
to the Cell Generator logic. The Cell Generator makes a request to the
receive cell arbiter to process the cell, and generates a status cell if no
UTOPIA receive cell is detected.
The UTOPIA level 1 bus interface runs at speeds up to 155 Mbps,
with the DPI-4 interface capable of full duplex operation at 160 Mbps.
In-stream programming is used to read and write to the PHY regis-
ters, with the Control Cells being generated from a remote controlling
agent. The Control Cells are used to configure, control and retrieve
status of the PHY device.
A status cell is a complete ATM cell generated and loaded to the
Receive DPI-4 I/F logic.
A receive cell on the DPI-4 bus is either an ATM cell from the receive
UTOPIA bus or a status ATM cell locally generated. Internally generated
ATM cells are output to the Receive DPI-4 Interface only when there are
no UTOPIA Receive cell. Figure 2 below shows the device data flow.
Block Diagram
UTOPIA L1
Receive
DPI Receive
OC-3
or
STS-3
4
IDT77010
UTOPIA L1
to DPI I/F
OC-3
PHY
4
UTOPIA L1
Transmit
DPI Transmit
Utility bus
Switching
Memory
IDT77V400
.
"
"
"
"
"
"
4308 drw 01
Figure 1 Typical IDT77010 Application
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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June 24, 2002
DSC 4308/4
2002 Integrated Device Technology, Inc.
IDT77010
Block Diagram
Cell
MUX
Rx UTOPIA
Interface
8
4
Rx DPI-4
Interface
UTOPIA
Interface
No Rx cell
detector/
arbiter
DPI-4
Interface
Cell
Generator
8
4
Control cell
filter
Tx UTOPIA
Interface
Tx DPI-4
Interface
8
Control cell
Decoder
Utility Bus
Interface
SYSCLK
SysClk/2
4308 drw 02
Figure 2 Functional Block Diagram
1,2
Pin Configuration
INDEX
V
DD
GND
ALE
RSOC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOC
TXPRTY
DATA7
DATA6
DATA5
GND
T
T
T
X
X
X
V
CC
GND
R
X
DATA
DATA
DATA
DATA
DATA
R
R
R
R
X
X
X
X
VCC
IDT77010
PQFP
TX
TX
TX
TX
TX
DATA4
DATA3
DATA2
DATA1
DATA0
GND
TOP
R
X
DATA
VIEW3
R
V
GND
XDATA
CC
RXDATA
RCLK
VCC
TCLK
TCLAV
TENB
CONT_A
GND
RCLAV
RENB
RxLED
VDD
4308 drw 03
1.
All power pins must be connected to the appropriate power supply.
VCC pins to 5.0V ± 0.25V; VDD pins to 3.3V ± 0.3V.
2.
All GND pins must be connected to ground supply.
3.
This text does not indicate orientation of the actual part-marking.
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IDT77010
Pin Definitions
Pin
Number
Input/
Output
Signal Name
Description
SysClk
RST
29
23
I
I
System Clock. All the device circuits are synchronized to this clock.
System Reset. When low the 77010 and the PHY are reset. This is used as a global line card reset where all
the RST signals from all line cards are connected together.
LCRST
24
I
Line Card reset. When low the 77010 and the PHY are reset. This is a local line card reset used to reset a
specific 77010 and PHY on a specific line card.
CONT_A
CONT_B
RxLED
19
22
42
O
O
O
Output Control Pin A. This pin is controlled by a receive control cell. Default output = low.
Output Control Pin B. This pin is controlled by a receive control cell. Default output = low.
Active low. When low a receive cell is being transferred.
This pin may be used for receive activity LED.
TxLED
79
O
Active low. When low a transmit cell is being transferred.
This pin may be used for transmit activity LED.
READ
73
74
59
71
70
69
68
65
64
63
62
78
72
77
45
58
43
44
46
49
50
51
52
53
54
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
Utility bus read signal.
WRITE
Utility bus write signal.
ALE
Utility bus address latch enable. Used for latching the address on the address phase of the Add/Data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus multiplexed address and data bus.
Utility bus PHY chip select.
Add/Data0
Add/Data1
Add/Data2
Add/Data3
Add/Data4
Add/Data5
Add/Data6
Add/Data7
PHYCS
PHYINT
PHYRST
RCLK
Utility bus PHY interrupt signal
O
O
I
Utility bus PHY reset.
UTOPIA bus receive clock.
RSOC
UTOPIA bus receive start of cell.
RENB
O
I
UTOPIA bus receive enable.
RCLAV
UTOPIA bus receive cell available.
UTOPIA bus receive data bit.
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
I
I
UTOPIA bus receive data bit.
I
UTOPIA bus receive data bit.
I
UTOPIA bus receive data bit.
I
UTOPIA bus receive data bit.
I
UTOPIA bus receive data bit.
I
UTOPIA bus receive data bit.
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IDT77010
Pin
Number
Input/
Output
Signal Name
Description
RxData7
TENB
55
18
16
17
2
I
UTOPIA bus receive data bit.
UTOPIA bus Transmit enable.
UTOPIA bus transmit clock.
O
O
I
TCLK
TCLAV
TSOC
UTOPIA bus transmit cell available.
UTOPIA bus transmit start of cell.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data bit.
UTOPIA bus transmit data parity bit.
DPI-4 bus transmit clock. 3.3V Interface.
O
O
O
O
O
O
O
O
O
O
O
I
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
TxPrty
13
12
11
10
9
6
5
4
3
DTxClk
DTxFRM
DTxData0
DTxData1
DTxData2
DTxData3
DRxClk
DRxFRM
DRxData0
DRxData1
DRxData2
DRxData3
VCC
39
38
37
36
35
34
32
33
28
27
26
25
DPI-4 bus transmit start of frame. 3.3V Interface.
DPI-4 bus transmit data bit. 3.3V Interface.
DPI-4 bus transmit data bit. 3.3V Interface.
DPI-4 bus transmit data bit. 3.3V Interface.
DPI-4 bus transmit data bit. 3.3V Interface.
DPI-4 bus receive clock. 3.3V Interface.
DPI-4 bus receive start of frame. 3.3V Interface.
DPI-4 bus receive data bit. 3.3V Interface.
DPI-4 bus receive data bit. 3.3V Interface.
DPI-4 bus receive data bit. 3.3V Interface.
DPI-4 bus receive data bit. 3.3V Interface.
5.0V Power Supply Pins.
I
I
I
I
O
O
O
O
O
O
8,15,48,57,67,76 Power
1,21,31,41,61 Power
VDD
3.3V Power Supply Pins for DPI Interface.
Ground Pins.
GND
7,14,20,30,40,47 GND
,56,60,66,75,80
1.
All signals are 5.0V unless otherwise indicated.
3.3V signals are 5.0V tolerant.
2.
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IDT77010
Absolute Maximum Ratings
Symbol
Parameter
5V Digital Supply Voltage
3.3V Digital Supply Voltage
Min
-0.3
Max
Unit
VCC
VDD
VIN
6.0
4.6
V
-0.3
VSS
____
-55
V
Digital Input Voltage
Output Current
VCC +0.5
50
V
IOUT
TSTG
mA
°C
Storage Temperature
140
Recommended Operating Conditions
Symbol
Parameter
5V Digital Supply Voltage
Min
Max
Unit
VCC
VDD
VIN
TA
4.75
3.0
5.25
3.6
V
3.3V Digital Supply Voltage
TTL Input Voltage
V
-0.3
0
VCC+0.3
70
V
Operating Temperature
Input TTL rise time
°C
ns
ns
V
titr
____
____
2.0
2
titf
Input TTL fall time
2
VIH
VIL
TTL Input High Voltage
TTL Input Low Voltage
____
0.8
____
V
DC Electrical Characteristics
77010
Symbol
Parameter
Test Conditions
Unit
µA
Min
Max
10
[ILI]
[ILO]
VOH
VOL
IDD
Input Leakage Current
VCC = 5.5V, VIN = 0V to VCC
VOUT = 0V to VCC
IOH = -4mA
10
10
2.4
Output Leakage Current
TTL Output High Voltage
TTL Output Low Voltage
Power Supply Current
Power Supply Current
10
µA
V
___
0.4
60
IOL = +4mA
___
___
___
V
155.52 Mbps
mA
mA
ICC
155.52 Mbps
12
Capacitance
Symbol
Parameter
Input Capacitance
Test Conditions
Min
___
Type Max Unit
CIN
All Inputs
4
___
___
___
pF
pF
pF
COUT
CBID
Output Capacitance
All Outputs
___
___
6
Bi-Directional Capacitance
All Bi-directional Pins
10
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IDT77010
Device Interface
This 77010 uses a UTOPIA level 1 interface to receive and transmit ATM cells to and from the PHY device. It mirrors the ATM layer as shown in
Figure 3 below.
DRxFRM
DRxCLK
RSOC
RCLK
DRxDATA[3:0]
RxDATA[7:0]
RENB
DPI-4
3.3V
RCLAV
Interface
IDT77010
UTOPIA-1
Interface
TxPRTY
DTxFRM
DTxCLK
TSOC
TCLK
DTxDATA[3:0]
TxDATA[7:0]
TENB
TCLAV
LCRST
PHYRST
RST
PHYCS
SYSCLK
PHYINT
ADD/DATA[7:0]
Utility Bus
ALE
READ
WRITE
RxLED
TxLED
CONT_A
CONT_B
4308 drw 04
Figure 3 DPI-4 to UTOPIA 1 Interface Device
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IDT77010
Internally generated control cells should be paced so that the sum of
receive UTOPIA status cells and internally generated control cells do not
exceed 160 Mbps.
UTOPIA Receive Interface Operation
UTOPIA cell level handshake is used to receive an ATM cell from a
UTOPIA PHY device. The UTOPIA Receive Clock (RCLK) is a contin-
uous clock generated from the System Clock (SYSCLK) and is half the
frequency of the DPI Receive Clock (DRxCLK).
The PHY is expected to buffer at least two receive cells for the flow
control to function without the loss of a cell. Figure 4 shows the receive
cell muxing with the internally generated status cells.
The receive cell header, including the HEC, and payload are trans-
ferred over the Receive Data bus (RxDATA[7:0]), which is 8-bits wide.
Receive Parity (RxPRTY) is not supported by the 77010, nor does it
calculate the HEC in the header field.
UTOPIA Transmit Interface
Operation
UTOPIA cell level handshake is used to transfer an ATM cell to a
UTOPIA PHY device. The UTOPIA Transmit Clock (TCLK) is a contin-
uous clock generated from the System Clock (SYSCLK) and is half the
frequency of the DPI Transmit Clock (DTxCLK).
The 77010 will assert Receive Enable (RENB) low two clock cycles
after detecting a high Receive Cell Available (RCLAV), if it is not
executing a control cell. Refer to the UTOPIA Receive Flow Control
section for description on muxing internally generated control cells with
UTOPIA receive cells.
Two TCLK cycles after detection of a high Transmit Cell Available
(TCLAV) the 77010 will assert TENB low. One TCLK cycle after TENB
assertion the 77010 will assert Transmit Start Of Cell (TSOC) and the
first valid byte of data. TSOC is one TCLK cycle long and coincides with
the first valid byte of data (TxDATA[7:0]). When the entire cell has been
transferred the 77010 will sample TCLAV for cell availability.
Once Receive Start Of Cell (RSOC) is detected the 77010 will
receive the entire cell without interruption.
UTOPIA Receive Flow Control
The UTOPIA data rate is higher than the cell rate on the transport
media. This provides additional bandwidth for the insertion of control
cells.
The PHY will de-assert TCLAV if it cannot accept another cell. The
77010 will continue transferring the current cell and store up to nine
bytes of the next cell in its pipeline if TCLAV is de-asserted during a cell
transfer.
The 77010 will only generate an internal control cell when RCLAV
and RENB are de-asserted and a cell transfer is not taking place. When
a control cell is inserted RENB is de-asserted high for 55 RCLK cycles,
which prevents the PHY from transferring a cell. During this 55 clock
period the 77010 inserts the control cell and sends it out to the DPI
receive interface.
Control cells from the DPI interface are filtered and not forwarded to
the transmit UTOPIA bus.
Figure 5 shows UTOPIA transmit data flow.
Line Card Interface
Internally
generated status
cell
Receive DPI bus
4
UTOPIA
Receive Bus
PHY
8
No back to back
Rx cell detector
4308 drw 05
Figure 4 UTOPIA Receive Data Flow
UTOPIA
Transmit bus
Control cell
Transmit DPI bus
4 to 8
Interface
UTOPIA
Interface
PHY
filter
8
4
UTOPIA
Interface
Transmit DPI clock
4308 drw 06
DPI
TxCLK
Control
TCLAV
Figure 5 UTOPIA Transmit Data Flow
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IDT77010
UTOPIA bus is at full rate. In this case it is recommended that the
control cells be at least 50 cells apart.
Input Control Cell Formatting
Control cells are generated by a remote computer and are used to
configure and monitor the PHY registers. All cells having the header VPI
= 0x00 hex and VCI = 0x1F hex (VCI bits 11-4) are decoded and
executed as control cells by the 77010.
DPI Interface Operation
Data Path Interface (DPI) is a synchronous bus interface designed to
transfer ATM cells between two devices. The 77010 contains a DPI-4
bus interface, which contains a four bit wide data bus. Therefore, 107
clock cycles are required to transfer a 53 byte ATM cell.
Control Cell Filter Operation
All cells transferred over the DTxDATA[3:0] bus are tested to see if
they are control cells.Cells containing the header VPI = 00 Hex and VCI
= 1F Hex (VCI bits 11-4) are filtered as control cells and not forwarded to
the TxDATA[7:0] bus. The filter ignores the GFC, PTI and CLP bits. The
default control cell identifier value is 00x1F. It can be programmed to a
user defined value via the Change Control Cell Address Command (see
page 16).
The 77010 has separate DPI-4 transmit and receive interfaces, with
each requiring six signals. The signals are a clock, a start of cell marker
and a four bit data bus. All signals are sampled on the rising edge of
their respective clock.
Transmit DPI Bus Interface
The Transmit DPI Clock (DTxCLK) is generated from SYSCLK and is
twice the frequency of TCLK. This clock is not continuous and is used to
control data flow to the PHY device. DTxCLK is initially low and not
driven until the 77010 detects a high TCLAV from the PHY device. On
the rising edge of DTxCLK the 77010 samples Transmit Start of Cell
(DTxFRM), which is generated by the transmitting device for one
DTxCLK cycle. When DTxFRM is asserted high the 77010 will sample
valid data (DTxDATA[3:0]) on the next rising edge of DTxCLK. Cell
transfer will continue without interruption once it has started.
Control Cell Frequency
The control cells arrive multiplexed with data cells in random combi-
nations, and are terminated (filtered) by the 77010.
The RxDATA[3:0] bus multiplexes the receive UTOPIA cells and any
internally generated control cells. The control cell is ignored if a previous
control cell is being executed at that time. A gap in the UTOPIA cell
stream must occur before the new control cell is processed, because the
UTOPIA receive cells have higher priority.
When TCLAV is de-asserted low the current cell is transferred and
DTxCLK goes low until another high TCLAV is detected.
Control cells may be input back-to-back. However, the second
control cell will not be processed and could be dropped, even though the
77010 can filter both of them. Worst case condition is when the receive
DTxFRM and DTxDATA[3:0] are sampled on the rising edge of
DTxCLK.
Control ATM Cell Format
Cell Byte
Number
Bit
Number
Function
Name
Bit
Contents
Description
0
0
1
1
2
3
3
3
4
5
6
7
8
7-4
GFC
0xX
Don't care.
3-0
7-4
3-0
7-0
7-4
3-1
0
VPI 7-4
VPI 3-0
VCI 15-12
VCI 11-4
VCI 3-0
PTI
0x0
Must be set to 0x0.
0x0
Must be set to 0x0.
0x0
Must be set to 0x0.
1
0xYY
0x0
Special VCI value for control and status cells. Default is 0x1F.
Don't care.
000'b
0'b
Don't care.
CLP
Don't care.
7-0
7-0
7-0
7-0
7-0
HEC
0x00
Don't care.
Command
Data A
Data B
reserved
00-FF Hex
0x0 - 0xFF
0x0 - 0xFF
0x00
Command cell byte.
Parameter for control cell.
Parameter for control cell.
Always set to 0x00.
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IDT77010
Cell Byte
Number
Bit
Number
Function
Name
Bit
Contents
Description
.
7-0
reserved
reserved
reserved
0x00
0x00
0x00
Always set to 0x00.
Always set to 0x00.
Always set to 0x00.
.
7-0
7-0
52
1.
This value can be programmed by instream control cells.
DPI Bus Data Sequence
For Transmit and Receive DPI bus in the 53 byte configuration, the following table shows the data nibble sequence.
DPI Nibble Count
DPI Content
GFC [3:0]
Comments
0
GFC bits for the ATM cell header. First nibble to be transmitted/received.
VPI bits MSB of the ATM cell header.
VPI bits LSB of the ATM cell header.
VCI bits MSB of the ATM cell header.
VCI bits of the ATM cell header.
1
VPI [7:4]
2
VPI [3:0]
3
VCI [15:12]
VCI [11:8]
4
5
VCI [7:4]
VCI bits of the ATM cell header.
6
VCI [3:0]
VCI bits of the ATM cell header.
7
PTI [2:0], CLP
HEC [7:4]
PTI and CLP bits of the ATM cell header.
HEC Most Significant nibble.
8
9
HEC [3:0]
HEC Least Significant nibble.
10
11
____
____
104
105
First data byte [7:4]
First data byte [3:0]
____
First data Most Significant nibble of the ATM cell header.
First data Least Significant nibble of the ATM cell header.
____
____
____
Last data byte [7:4]
Last data byte [3:0]
Last data byte Most Significant nibble of the ATM cell.
Last data byte Least Significant nibble of the ATM cell.
DTxClk
(Output)
DTxFRM
(Input)
DTxData[3:0]
(Input)
104
105
1
2
0
Figure 6 DPI-4 Transmit Bus with only one cell
DTxClk
(Output)
DTxFRM
(Input)
DTxData[3:0]
(Input)
102
3
103
105
1
2
4
104
105
1
2
0
0
Figure 7 DPI-4 Transmit Bus with back to back cell
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IDT77010
Receive DPI Bus Interface
The Receive DPI Clock (DRxCLK) is a continuous clock generated from SYSCLK and is twice the frequency of RCLK. The Receive Start of Cell
marker (DRxFRM) is also generated by the 77010 and is asserted for one clock cycle prior to the first nibble of valid data (DRxDATA[3:0]).
There is no flow control in the receive DPI path. It is assumed that the receiving device can accept the incoming cell.
DRxFRM and DRxDATA[3:0] are sampled on the rising edge of DRxCLK.
DRxClk
(Output)
DRxFRM
(Output)
DRxData[3:0]
(Output)
4
3
104
105
1
2
0
4308 drw
Figure 8 DPI-4 Receive Bus with only one cell
DRxClk
(Output)
DRxFRM
(Output)
DRxData[3:0]
(Output)
4
102
105
1
2
3
103
104
105
1
2
0
0
4308 drw
Figure 9 DPI-4 Receive Bus with back to back cell
Utility Bus
The Utility bus is used for accessing the internal PHY registers. An 8-bit read or write command is implemented via instream (in-band) program-
ming to access the registers. The commands are input to the 77010 via the DPI-4 transmit path. The PHY register commands are decoded by the
77010 and executed using the Utility bus.
Figure 10 shows the Utility bus interface.
UTILITY BUS
PHYCS
PHYINT
PHY
or an
Add/Data[7:0]
IDT77010
External
device
ALE
READ
PHYRST
WRITE
4308 drw 11
Figure 10 Utility Bus Interface
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IDT77010
Utility Bus Read Operation
When the 77010 decodes the command cells for a Utility bus read operation, it drives the PHY chip select (PHYCS), Address Latch Enable
(ALE),Read(READ) and the Address Data bus (Add/Data[7:0]). At the falling edge of ALE, the PHY samples the address phase of the Add/Data[7:0].
The 77010 then floats the Add/Data[7:0] bus. The PHY drives the Add/Data[7:0] bus until rising edge of PHYCS or READ. See Figure 11 below.
SYSCLK
tALPW
tPALE
ALE
PHYCS
tPPHY
tALR
tRDPW
READ
tALA
tAAL
Add/Data[7:0]
Address
Read Data from PHY
4308 drw 12
tDRH
tDRS
Figure 11 Utility Bus Read Operation
Utility Bus Write Operation
When the 77010 decodes the command cell for a Utility bus write operation, it drives the PHY chip select (PHYCS), Address Latch Enable (ALE),
Write (WRITE), and the Address Data bus (Add/Data[7:0]). At the falling edge of ALE, the PHY samples the address phase of the Add/Data[7:0]. The
PHY samples the write data byte on the Add/Data[7:0] bus at the rising edge of PHYCS or WRITE. See Figure 12 below.
SYSCLK
tALPW
t
PALE
ALE
PHYCS
tPPHY
WRITE
tALW
tAAL
tALA
Address
Write Data to PHY
Add/Data[7:0]
4308 drw 13
tDWH
tDWS
Figure 12 Utility Bus Write Operation
Reply Command Cell
Interrupt Reply Cell Notification
Return command cell indicating an interrupt has occurred on the Utility bus.
Command Fields Field Value (Hex)
Command
Description
00
xx
xx
Interrupt Cell Return Command
DataA
DataB
See Data A and Data B Tables on page 14.
See Data A and Data B Tables on page 14.
11 of 21
June 24, 2002
IDT77010
Command Cells
Reset PHY Chip Command
Resets the PHY device and the Utility bus. PHYRST will assert low for 16 SYSCLK cycles. This command does not generate nor return a
command cell.
Command Fields
Command
Field Value (Hex)
Description
01
xx
xx
Reset Phy Chip.
DataA
DataB
Don't care. It may contain any number.
Don't care. It may contain any number.
Utility Bus Write Command
Writes one byte per command cell to the Utility bus. The Utility bus is used to write to the PHY registers. This command does not generate nor
return a command cell.
Command Fields
Command
Field Value (Hex)
Description
02
Write to Utility bus.
DataA
DataB
00 - FF
00 - FF
Utility bus address.
Utility bus data byte to be written.
Utility Bus Read Command
Reads one byte per command cell from the Utility bus. The Utility bus is used to read the PHY registers. This command generates a return com-
mand cell. See Reply Cell Format Table.
Command Fields
Command
Field Value (Hex)
Description
03
Read to Utility bus.
Utility bus address.
DataA
DataB
00 - FF
xx
Don't care on command. Will return value from Data B Table.
Output Pin Control Command
This command controls the output pins CONT_A and CONT_B, and causes an internally generated cell. See internally generated cell format
section.
Command Fields
Field Value (Hex)
Description
Define CONT_A and CONT_B Output State.
Command
DataA
04
xx
Don't Care.
DataB
Control pins output state.
CONT_A CONT_B
00
01
02
03
Low
Low
High
High
Low
High
Low
High
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June 24, 2002
IDT77010
Status Read Command
This command reads the 77010 Revision number and the Interrupt pin state, and causes an internally generated cell. See internally generated cell
format section.
Command Fields
Command
Field Value (Hex)
Description
05
xx
xx
Status cell.
DataA
DataB
See Data A and Data B Tables on page 14.
See Data A and Data B Tables on page 14.
Change Control Cell Address Command
This command is used to change the control cell address. Once modified the IDT77010 will not filter old (default = 0x1Fx) values from the ATM cell
stream. The command does not return a command cell.
Command Fields
Command
Field Value (Hex)
Description
06
Status cell.
DataA
DataB
00--FF
xx
New Control Cell Address; placed in lower byte of VCI Field
Don’t care.
Internally Generated Reply Cell Format
Internal cells are generated in response to a command cell or PHY interrupt. The cells are remotely sent and switched to the 77010. The cell format
of an internally generated cell is as follows:
Cell Byte
Number
Function
Name
Bit Number
Bit Contents
0x0
Description
0
0
1
1
2
3
3
3
4
7-4
3-0
7-4
3-0
7-0
7-4
3-1
0
GFC
Always set to 0x0
Always set to 0x0
Always set to 0x0
Always set to 0x0
VPI 7-4
VPI 3-0
VCI 15-12
VCI 11-4
VCI 3-0
PTI
0x0
0x0
0x0
0x02
0x0
Special VCI value for control and status cells.
Special VCI value for control and status cells.
Always set to 000'b.
000'b
0'b
CLP
Always set to 0.
7-0
HEC
0x00
Transmit HEC byte, always set to 0x00. The PHY device generates and
calculates the HEC byte.
5
7-0
Command
00-FF Hex
This returned cell value is the same as the command cells Command byte.
For interrupt cell this byte = 00 hex.
6
7
8
.
7-0
7-0
7-0
7-0
7-0
7-0
Data 1
See below
See below
0x00
See below.
Data 2
See below.
reserved
reserved
reserved
reserved
Always set to 0x00.
Always set to 0x00.
Always set to 0x00.
Always set to 0x00.
0x00
.
0x00
52
0x00
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June 24, 2002
IDT77010
Internally Generated Reply Cell Table - Data A
Internally Generated
Cell Type
Data A Byte Bit
Number
Description
Address of the Utility bus read.
Utility Bus Read
Status Read Cell
7-0
7
6-0
This bit has the value of the interrupt pin at the time of this cell's generation.
Reserved. Set to 0.
Interrupt Cell Return
7
6-0
This bit has the value of the interrupt pin at the time of this cell's generation.
Reserved. Set to 0.
Internally Generated Reply Cell Table - Data B
Internally Generated
Cell Type
Data A Byte Bit
Number
Description
Data value of the Utility bus read.
Utility Bus Read
7-0
7-0
7-0
Status Read Cell
Interrupt Cell Return
Revision number of the device.
Revision number of the device.
14 of 21
June 24, 2002
IDT77010
77010
Max
____
Symbol
Parameter
Unit
Min
tCYC
SCLK Cycle Time
SCLK High Time
SCLK Low Time
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
____
____
____
____
____
20
tCL
8
tUCYC
tUCH
tUCL
UTOPIA TCLK/RCLK Cycle Time
50
20
20
1
UTOPIA TCLK/RCLK High Time
UTOPIA TCLK/RCLK Low Time
tTOV
tUTS
TxDATA, TxPRTY, TENB, TSOC Output Valid from TCLK
TCLAV to TCLK Setup Time
10
1
____
____
20
tUTH
TCLAV to TCLK Hold Time
tROV
tURS
RENB Output Valid from RCLK
1
RxDATA, RSOC, RCLAV to RCLKSetup Time
RxDATA, RSOC, RCLAV to RCLK Hold Time
DPI DTxCLK/DRxCLK Cycle Time
10
1
____
____
____
____
____
____
____
13
tURH
tDCYC
tDCH
tDCL
25
9
DPI DTxCLK/DRxCLK High Time
DPI DTxCLK/DRxCLK Low Time
9
tDTS
DTxFRM, DTxDATA to DTCLK Setup Time
DTxFRM, DTxDATA to DTCLK Hold Time
DRxCLK to DRxDATA(0-3), DRxFRM Propagation Delay
ALE Pulse Width
6
tDTH
2
tPDRD
tALPW
tALR
____
40
____
22
System Clock to READ Low Propagation Delay
System Clock to WRITE Low Propagation Delay
Read Pulse Width
____
____
80
tALW
tRDPW
tAAL
22
____
____
____
____
____
____
____
____
____
____
22
Address to ALE Falling Edge Setup Time
Address to ALE Falling Edge Hold Time
Data to rising edge of READ Setup Time
Data to rising edge of READ Hold Time
Data to rising edge of WRITE Setup Time
Data to rising edge of WRITE Hold Time
Write Pulse Width
20
tALA
10
tDRS
5
tDRH
tDWS
tDWH
tWRPW
tPINTS
tPINTH
tPALE
tPPHY
tPPHYR
tPRCLK
1
5
1
40
System Clock to PHYINT Setup Time
System Clock to PHYINT Hold Time
ALE to System Clock Propagation Delay
System Clock to PHYCS Propagation Delay
System Clock to PHYRST Propagation Delay
System Clock to Utopia Receive Clock Propagation Delay
10
1
____
____
____
____
22
22
20
15 of 21
June 24, 2002
IDT77010
77010
Symbol
Parameter
Unit
Min
____
Max
tPTCLK
tPDRxCLK
tPDTxCLK
tPRLED
tPTLED
tPCNTA
tPCNTB
tPRSTS
System Clock to Utopia Transmit Clock Propagation Delay
System Clock to DPI Receive Clock Propagation Delay
System Clock to DPI Transmit Clock Propagation Delay
System Clock to RxLED Propagation Delay
20
10
10
19
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
System Clock to TxLED Propagation Delay
System Clock to CONT_A Propagation Delay
System Clock to CONT_B Propagation Delay
22
22
Rising Edge of RST and LCRST to Rising Edge of System Clock Setup Time 10
____
____
tPRSTH
Rising Edge of RST and LCRST to Rising Edge of System Clock Hold Time
3
16 of 21
June 24, 2002
IDT77010
System Clock Timing Waveform
t
CYC
SYSCLK
tCH
tCL
4308 drw 14
UTOPIA Transmit Timing Waveform
tUCYC
TCLK
tUCH
t
TOV
tUCL
TxDATA(0-7), TENB, TSOC
TCLAV
t
UTH
tUTS
4308 drw 15
UTOPIA Receive Timing Waveform
RCLK
tURS
tURH
t
ROV
RENB
RxDATA(0-7), RSOC, RCLAV
4308 drw 16
DPI Transmit Timing Waveform
tDCYC
DTxCLK
t
DCH
tDCL
tDTS
tDTH
DTxFRM, DTxDATA(0-3)
4308 drw 17
DPI Receive Timing Waveform
DRxCLK
tPDRD
DRxFRM, DRxDATA(0-3)
4308 drw 18
17 of 21
June 24, 2002
IDT77010
System Clock to UTOPIA Receive Clock Propagation Delay
SYSCLK
tPRCLK
RCLK
4308 drw 19
System Clock to UTOPIA Transmit Clock Propagation Delay
SYSCLK
tPTCLK
TCLK
4308 drw 20
System Clock to DPI Receive Clock Propagation Delay
SYSCLK
tPDRxCLK
DRxCLK
4308 drw 21
System Clock to DPI Transmit Clock Propagation Delay
SYSCLK
tPDTxCLK
DTxCLK
4308 drw 22
4308 drw 23
4308 drw 24
System Clock to RxLED Propagation Delay
SYSCLK
tPRLED
RxLED
System Clock to TxLED Propagation Delay
SYSCLK
tPTLED
TxLED
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June 24, 2002
IDT77010
System Clock to Count_A Propagation Delay
SYSCLK
tPCNTA
CONT_A
4308 drw 25
4308 drw 26
4308 drw 27
4308 drw 28
System Clock to Count_B Propagation Delay
SYSCLK
tPCNTB
CONT_B
System Clock to PHYRST Propagation Delay
SYSCLK
tPPHYR
PHYRST
System Clock to PHYINT Setup and Hold Times
SYSCLK
tPINTS
tPINTH
PHYINT
System Clock to RST and LCRST Setup Time
SYSCLK
tPRSTH
tPRSTS
RST, LCRST
4308 drw 31
19 of 21
June 24, 2002
IDT77010
Package Information
Plastic QFP 80pin Body size 12 x 12 x 1.4mm (QFP14)
HD
D
60
41
61
40
f
HE
E
b
Index
80
21
1
20
θ
θ
2
R
1
R
θ
3
L2
L
C
4308 drw 29
L1
1
Symbol
Dimension in Millimeters
Min Norm Max
Dimension in Inches
Min
Norm
Max
E
11.9
11.9
12
12
12.1
12.1
1.7
(0.469)
(0.469)
(0.472)
(0.472)
(0.476)
(0.476)
(0.066)
D
A
A1
A2
f
0.1
1.4
0.5
0.18
(0.004)
(0.055)
(0.020)
(0.007)
(0.005)
1.3
1.5
(0.052)
(0.059)
b
0.13
0.1
0o
0.28
0.175
10o
(0.006)
(0.004)
(0o)
(0.011)
(0.006)
(10o)
C
q
0.125
L
0.3
0.5
1
0.7
(0.012)
(0.020)
(0.039)
(0.020)
(0.551)
(0.551)
(0.027)
L1
L2
0.5
14
14
HE
HD
q2
q3
R
13.6
13.6
14.4
14.4
(0.536)
(0.536)
(0.566)
(0.566)
0.2
0.2
(0.008)
(0.008)
R1
1.
for reference
20 of 21
June 24, 2002
IDT77010
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0 Degrees C to +70 Degrees C)
Blank
PQF
155
L
PQFP (80-pin)
4-bit Port Bandwidth in Mbps
Low Power
UTOPIA 1 TO DATA PATH INTERFACE (DPI)
TRANSLATION DEVICE
77010
4308 drw
Data Sheet Document History
4/02/99
5/18/99
6/24/99
7/06/99
2/12/01
6/24/02
Changed format
Changed tDTH from 6ns to 2ns, changed tALPW from 20ns to 40ns, added TxPRTY prop. delay.
Changed tDCH and tDCL from 8ns to 9ns, added tTOV and tROV min of 1ns.
Changed tPTCLK from 11ns to 20ns to match RCLK.
Changed to Final. Made general corrections. No parameters changed.
Added drawing 4308d31, System Clock to RST and LCRST Setup Time. Added tPRSTS and tPRSTH timing to timing parameters table. Changed
e-mail URL from atmhelp@idt.com to switchstarhelp@idt.com.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
email:
switchstarhelp@idt.com
phone: 408-492-8208
800-345-7015 or 408-727-6116
fax: 408-330-1748
www.idt.com
21 of 21
June 24, 2002
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