74LVC2952APY [IDT]

SSOP-24, Tube;


型号：	74LVC2952APY
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	SSOP-24, Tube
文件：	总6页 (文件大小：73K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC2952A

3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3V CMOS OCTAL BUS

TRANSCEIVER AND

IDT74LVC2952A

PUTS AND 5 VOLT TOLERANT I/O

DESCRIPTION:

FEATURES:

–

0.5 MICRON CMOS Technology

The LVC2952A octal bus transceiver and register is built using ad-

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

1.27mm pitch SOIC, 0.65mm pitch SSOP,

0.635mm pitch QSOP, 0.65mm pitch TSSOP packages

Extended commercial range of – 40°C to +85°C

VCC = 3.3V ±0.3V, Normal Range

vanced dual metal CMOS technology. This high speed low power device

isorganizedas8-bitback-to-backregisterswithseparateinputandoutput

control for indepedent control of data flow in either direction. Data on the

AorBbusisstoredintheregistersonthelow-to-hightransitionoftheclock

(CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or

CLKENBA) input is low. Taking the output-enable (OEABorOEBA) input

low accesses the data of either port.

–

VCC = 2.3V to 3.6V, Extended Range

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

All inputs, outputs and I/O are 5 Volt tolerant

Supports hot insertion

Allpinscanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V system environ-

ment.

Drive Feature for LVC2952A:

Balanced Output Drivers: ±24mA

The LVC2952A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

–

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

CLKENAB

CLKAB

OEAB

CLKENBA

CLKBA

OEBA

¹D

C¹

¹D

TO SEVEN OTHER CHANNELS

EXTENDED COMMERCIAL TEMPERATURE RANGE

OCTOBER 1999

1999 Integrated Device Technology, Inc.

DSC-4581/-

IDT74LVC2952A

3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER

EXTENDEDCOMMERCIALTEMPERATURERANGE

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Max.

Unit

Terminal Voltage with Respect to GND

Storage Temperature

– 0.5 to +6.5

– 65 to +150

VCC

°C

IOUT

DC Output Current

– 50 to +50

– 50

IIK

IOK

ICC

Continuous Clamp Current,

VI < 0 or VO < 0

Continuous Current through

±100

ISS

each VCC or GND

8LVC

SO24-2

SO24-7

SO24-8

SO24-9

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

OEAB

CLKAB

OEBA

CAPACITANCE (TA = +25°C, f = 1.0MHZ)

Symbol

Parameter⁽¹⁾

Conditions

Typ.

Max. Unit

CLKBA

CLKENAB

GND

CIN

Input Capacitance

VIN = 0V

4.5

CLKENBA

COUT

CI/O

Output

Capacitance

I/O Port

VOUT = 0V

VIN = 0V

5.5

6.5

SOIC/ SSOP/ QSOP/ TSSOP

TOP VIEW

Capacitance

8LVC Link

NOTE:

1. As applicable to the device type.

FUNCTION TABLE ^{(1, 2)}

PIN DESCRIPTION

Pin Names

Description

Inputs

Outputs

OEAB

OEBA

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Clock Enable Input (Active LOW)

B-to-A Clock Enable Input (Active LOW)

A-to-B Clock Input

CLKENAB CLKAB

OEAB

(3)

B₀

CLKENAB

CLKENBA

CLKAB

CLKBA

(3)

B₀

H or L

↑

B-to-A Clock Input

A-to-B Data Inputs or B-to-A 3-State Outputs

B-to-A Data Inputs or A-to-B 3-State Outputs

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑

= LOW-to-HIGH Transition

2. A-to-B data flow is shown; B-to-A flow control is similar but uses

CLKENBA, CLKBA, and OEBA.

3. B₀= Level of B before the indicated steady-state input conditions

were established.

IDT74LVC2952A

3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER

EXTENDEDCOMMERCIALTEMPERATURERANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = – 40°C To +85°C

Symbol

Parameter

Test Conditions

Min.

Typ.⁽¹⁾

Max.

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 3.6V

1.7

—

0.7

0.8

±5

VIL

Input LOW Voltage Level

Input Leakage Current

—

IIH

IIL

VI = 0 to 5.5V

µA

IOZH

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOZL

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

VCC = 2.3V, IIN = – 18mA

VCC = 3.3V

—

– 0.7

100

—

±50

– 1.2

—

µA

Input Hysteresis

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

(2)

—

3.6 ≤ VIN ≤ 5.5V

∆ICC

Quiescent Power Supply

Current Variation

One input at VCC - 0.6V,

other inputs at VCC or GND

500

µA

8LVC Link

NOTES:

1. Typical values are at V^CC= 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

Output HIGH Voltage

Test Conditions⁽¹⁾

Min.

Max.

Unit

VOH

VCC = 2.3V to 3.6V

VCC = 2.3V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC – 0.2

—

VCC = 2.3V

1.7

2.2

2.4

2.2

—

VCC = 2.7V

—

VCC = 3.0V

—

VCC = 3.0V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

Output LOW Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3.0V

—

8LVC Link

NOTE:

1. V^IHand VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V^CCrange. TA = – 40°C to +85°C.

IDT74LVC2952A

3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER

EXTENDEDCOMMERCIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, V

= 3.3V ± 0.3V, T = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

Power Dissipation Capacitance per Transceiver Outputs enabled

Power Dissipation Capacitance per Transceiver Outputs disabled

CL = 0, f = 10Mhz

CPD

SWITCHING CHARACTERISTICS ⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fMAX

—

150

—

150

—

MHz

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Propagation Delay

—

8.8

8.2

7.8

—

CLKAB or CLKBA to Bx or Ax

Output Enable Time

OEBA or OEAB to Ax or Bx

Output Disable Time

OEBA or OEAB to Ax or Bx

Set-up Time,

Data Before CLK↑ HIGH

Hold Time,

Data After CLK↑ HIGH

Set-up Time,

—

8.8

—

1.7

1.8

1.3

1.4

3.3

—

1.3

1.1

3.3

—

tSU

CLKEN Before CLK↑ HIGH

Hold Time,

CLKEN After CLK↑ HIGH

Pulse Duration,

CLK HIGH or LOW

(2)

tSK(0)

Output Skew

NOTES:

1. See test circuits and waveforms. T^A= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC2952A

3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER

EXTENDEDCOMMERCIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

PROPAGATIONDELAY

VIH

(1)

(2)

VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V

Symbol

Unit

SAME PHASE

VLOAD

2 x Vcc

Vcc

INPUT TRANSITION

tPHL

tPLH

VIH

2.7

1.5

300

2.7

1.5

300

VOH

OUTPUT

VCC / 2

150

VOL

VLZ

VHZ

VIH

150

OPPOSITE PHASE

INPUT TRANSITION

8LVC Link

LVC Link

TEST CIRCUITS FOR ALL OUTPUTS

ENABLEANDDISABLETIMES

VLOAD

VCC

DISABLE

ENABLE

VIH

Open

GND

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

Pulse ^{(1, 2)}

Generator

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

V^OL+VLZ

VOL

tPHZ

tPZH

VOH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

VOH-VHZ

LVC Link

DEFINITIONS:

C^L= Load capacitance: includes jig and probe capacitance.

LVC Link

R^T= Termination resistance: should be equal to ZOUT of the Pulse

NOTE:

Generator.

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2ns; tR ≤ 2ns.

SET-UP, HOLD, AND RELEASE TIMES

SWITCHPOSITION

VIH

DATA

INPUT

Test

Switch

t^SU

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

VLOAD

VIH

TIMING

INPUT

tREM

VIH

GND

ASYNCHRONOUS

CONTROL

Open

VIH

SYNCHRONOUS

CONTROL

8LVC Link

tSU

OUTPUT SKEW - tsk (x)

VIH

LVC Link

INPUT

PULSEWIDTH

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

VOH

HIGH-LOW-HIGH

PULSE

VOL

LVC Link

tPLH2

tPHL2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

NOTES:

1. For t^SK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t^SK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC2952A

3.3VCMOSOCTALBUSTRANSCEIVERANDREGISTER

EXTENDEDCOMMERCIALTEMPERATURERANGE

ORDERINGINFORMATION

LVC

Temp. Range

IDT

XXXX

Bus-Hold Device Type Package

Small Outline IC (gull wing) (SO24-2)

Shrink Small Outline Package (SO24-7)

Quarter Size Small Outline Package (SO24-8)

Thin Shrink Small Outline Package (SO24-9)

2952A

Octal Bus Transceiver and Register with 3-State Outputs, ±24mA

Blank

No Bus-hold

–40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

74LVC2952APY [IDT]

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