74FCT162H245ATPF [IDT]
Bus Driver/Transceiver, 2-Func, 8-Bit, True Output, CMOS, PDSO48;
| 型号： | 74FCT162H245ATPF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver/Transceiver, 2-Func, 8-Bit, True Output, CMOS, PDSO48 光电二极管 |
| 文件： | 总6页 (文件大小：566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS 16-BIT
IDT74FCT162H245AT/CT
BIDIRECTIONAL
TRANSCEIVER
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT162H245T 16-bit transceiver is built using advanced dual metal
CMOS technology. These high-speed, low-power transceivers are ideal for
synchronouscommunicationbetweentwobusses(AandB).TheDirectionand
OutputEnablecontrolsoperatethesedevicesaseithertwoindependent8-bit
transceiversorone16-bittransceiver.Thedirectioncontrolpin(xDIR)controls
thedirectionofdataflow.Theoutputenablepin(xOE)overridesthedirection
control and disables both ports. All inputs are designed with hysteresis for
improvednoisemargin.
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤ 1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull up resistors
• Power off disable outputs permit “live insertion”
• Available in SSOP, TSSOP, and TVSOP packages
The FCT162H245T has "Bus Hold" which retains the input's last state
whenevertheinputgoestohighimpedance. Thisprevents"floating"inputsand
eliminatestheneedforpull-up/downresistors.
FUNCTIONALBLOCKDIAGRAM
1 DIR
2 DIR
1OE
2OE
1A1
2A1
1B1
2B1
1A2
2A2
1B2
2B2
1A3
2A3
1B3
2B3
1A4
2A4
1B4
2B4
1A5
2A5
1B5
2B5
1A6
2A6
1B6
2B6
1A7
2A7
1B7
2B7
1A8
2A8
1B8
2B8
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
APRIL 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5459/1
IDT74FCT162H245AT/CT
FASTCMOS16-BITBIDIRECTIONALTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
V
°C
mA
(2)
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
–0.5 to 7
(3)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VTERM
1DIR
1B1
1OE
1A1
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
2
3
1B2
1A2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GND
4
GND
5
1B3
1A3
6
1B4
1A4
2. All device terminals except FCT162XXXT and FCT166XXT (A-Port) Output and
I/O terminals.
VCC
7
VCC
3. Output and I/O terminals for FCT162XXXT and FCT166XXXT (A-Port).
8
1B5
1A5
CAPACITANCE (TA = +25°C, f = 1.0MHz)
9
1B6
1A6
Symbol
CIN
Parameter(1)
Conditions
VIN = 0V
Typ.
3.5
Max. Unit
6
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
Input Capacitance
pF
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
1B7
1B8
2B1
1A7
1A8
2A1
NOTE:
1. This parameter is measured at characterization but not tested.
PINDESCRIPTION
2B2
2A2
Pin Names
xOE
Description
OutputsEnableInput(ActiveLOW)
DirectionControl Inputs
GND
GND
xDIR
2B3
2A3
xAx
xBx
SideAInputsor3-StateOutputs(1)
SideBInputsor3-StateOutputs(1)
2B4
2A4
NOTE:
VCC
VCC
1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os.
2B5
2A5
FUNCTIONTABLE(1)
2B6
2A6
Inputs
GND
GND
Output
Bus B Data to Bus A
Bus A Data to Bus B
HighZState
xOE
L
xDIR
2B7
2B8
2A7
2A8
L
H
X
L
H
2DIR
NOTE:
2OE
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
SSOP/ TSSOP/ TVSOP
TOP VIEW
Z = High-Impedance
2
IDT74FCT162H245AT/CT
FASTCMOS16-BITBIDIRECTIONALTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
VIL
Parameter
Input HIGH Level
TestConditions(1)
Guaranteed Logic HIGH Level
GuaranteedLogicLOWLevel
Min.
2
Typ.(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
Unit
V
InputLOWLevel
Input
—
—
—
—
—
—
—
—
—
–50
50
—
—
—
–80
—
—
0.8
V
IIH
StandardInput(5) VCC = Max.
VI = VCC
±1
µA
HIGH
StandardI/O(5)
Bus-holdInput
Bus-hold I/O
±1
Current(4)
±100
±100
±1
IIL
Input
StandardInput(5)
StandardI/O(5)
Bus-holdInput
Bus-hold I/O
VI = GND
LOW
±1
Current(4)
±100
±100
—
—
±1
IBHH
IBHL
IOZH
IOZL
VIK
Bus-holdSustain
Current(4)
HighImpedanceOutputCurrent
(3-StateOutputpins)(5,6)
ClampDiodeVoltage
Bus-holdInput
VCC = Min.
VCC = Max.
VI = 2V
µA
µA
VI = 0.8V
VO = 2.7V
VO = 0.5V
±1
VCC = Min., IIN = –18mA
–1.2
–250
—
V
IOS
ShortCircuitCurrent
VCC = Max., VO = GND(3)
mA
mV
µA
VH
InputHysteresis
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
500
OUTPUTDRIVECHARACTERISTICS
Symbol
IODL
Parameter
OutputLOW Current
Output HIGH Current
Output HIGH Voltage
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
Min.
Typ.(2)
115
–115
3.3
Max.
200
–200
—
Unit
mA
mA
V
60
–60
2.4
IODH
VOH
VCC = Min.
IOH = –24mA
VIN = VIH or VIL
VCC = Min.
VOL
OutputLOWVoltage
IOH = 24mA
—
0.3
0.55
V
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus-hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
6. Does not include Bus-hold I/O pins.
3
IDT74FCT162H245AT/CT
FASTCMOS16-BITBIDIRECTIONALTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
VIN = VCC
—
60
100
µA/
OutputsOpen
VIN = GND
MHz
xOE = xDIR = GND
OneInputToggling
50% Duty Cycle
VCC = Max.
OutputsOpen
fi = 10MHz
50% Duty Cycle
xOE = xDIR = GND
OneBitToggling
VCC = Max.
OutputsOpen
fi = 2.5MHz
IC
TotalPowerSupplyCurrent(6)
VIN = VCC
—
—
—
—
0.6
0.9
2.4
6.4
1.5
2.3
mA
VIN = GND
VIN = 3.4V
VIN = GND
VIN = VCC
4.5(5)
16.5(5)
VIN = GND
50% Duty Cycle
VIN = 3.4V
VIN = GND
xOE = xDIR = GND
SixteenBitsToggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
FCT162H245AT
FCT162H245CT
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Unit
ns
tPLH
PropagationDelay
CL = 50pF
1.5
4.6
1.5
3.5
tPHL
A to B, B to A
RL = 500Ω
tPZH
tPZL
OutputEnableTime
1.5
1.5
1.5
1.5
—
6.2
5
1.5
1.5
1.5
1.5
—
4.4
4
ns
ns
ns
ns
ns
xOE to A or B
tPHZ
OutputDisableTime
tPLZ
xOE to A or B
tPZH
tPZL
OutputEnableTime
6.2
5
4.8
4
xDIR to A or B(3)
tPHZ
OutputDisableTime
xDIR to A or B(3)
tPLZ
tSK(o)
OutputSkew(4)
0.5
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4
IDT74FCT162H245AT/CT
FASTCMOS16-BITBIDIRECTIONALTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
V CC
7.0V
SWITCHPOSITION
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
CL
All Other Tests
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
5
IDT74FCT162H245AT/CT
FASTCMOS16-BITBIDIRECTIONALTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT XXX
Drive
XXXX
XX
X
Temp. Range
Bus Hold Device Type
Package
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Bidirectional Transceiver
Bus-Hold
245AT
245CT
H
162
74
Double-Density, 5 Volt, Balanced Drive
–40°C to +85°C
DATASHEETDOCUMENTHISTORY
4/11/2002 Removedblankspeedoption
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Santa Clara, CA 95054
www.idt.com
6
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