7429FCT52CTPY [IDT]
FAST CMOS OCTAL REGISTERED TRANSCEIVERS; 快速CMOS八路注册收发器
| 型号： | 7429FCT52CTPY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT29FCT52AT/BT/CT/DT
IDT29FCT2052AT/BT/CT
IDT29FCT53AT/BT/CT
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
DESCRIPTION:
The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/
CT are 8-bit registered transceivers built using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis-
ters store data flowing in both directions between two bidirec-
tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.
TheIDT29FCT52AT/BT/CT/DTandIDT29FCT2052AT/BT/
CT are non-inverting options of the IDT29FCT53AT/BT/CT.
The IDT29FCT2052AT/BT/CT has balanced drive outputs
with current limiting resistors. This offers low ground bounce,
minimal undershoot and controlled output fall times-reducing
the need for external series terminating resistors. The
IDT29FCT2052T part is a plug-in replacement for
IDT29FCT52T part.
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for 29FCT52/29FCT53T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
• Features for 29FCT2052T:
– A, B and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
– Reduced system switching noise
FUNCTIONAL BLOCK DIAGRAM(1)
CPA
CEA
OEB
CE CP
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A
Reg.
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
D0
D1
D2
D3
D4
D5
D6
D7
B
Reg.
CE CP
OEA
CPB
CEB
NOTE:
1. IDT29FCT52T/IDT29FCT2052T function is shown. IDT29FCT53T is
the inverting option.
2629 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 1995
1995 Integrated Device Technology, Inc.
6.1
DSC-4224/5
1
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
24
23
22
21
20
19
18
17
16
15
14
13
1
B7
B6
B5
B4
B3
B2
B1
Vcc
A7
A6
A5
A4
A3
A2
A1
A0
2
4
3
2
28 27 26
3
5
25
24
23
22
21
20
19
B4
B3
B2
NC
B1
B0
A5
A4
A3
NC
A2
A1
1
P24-1
D24-1
SO24-2
SO24-7*
SO24-8*
&
4
6
5
7
6
8
L28-1
7
9
8
0
B
10
11
E24-1
9
OEB
CPA
CEA
GND
OEB
A0
10
11
12
OEA
CPB
CEB
12 13 14 15 16 17 18
2629 drw 03
2629 drw 02
LCC
TOP VIEW
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
PIN DESCRIPTION
Name
I/O
I/O
I/O
I
Description
A0-7
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
B0-7
CPA
Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of
the CPA signal.
CEA
OEB
CPB
CEB
OEA
I
I
I
I
I
Clock Enable for the A Register. WhenCEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When
OEB is HIGH, the B0-7 outputs are in the high-impedance state.
Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of
the CPB signal.
Clock Enable for the B Register. WhenCEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When
OEA is HIGH, the A0-7 outputs are in the high-impedance state.
2629 tbl 01
6.1
2
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
REGISTER FUNCTION TABLE(1)
(Applies to A or B Register)
OUTPUT CONTROL(1)
Internal
Y-Outputs
Inputs
Internal
Q
X
L
52/2052
53
Z
Function
OE
H
D
X
L
CP
X
Q
NC
L
Function
Hold Data
Load Data
CE
H
Z
L
Disable Outputs
Enable Outputs
L
H
L
↑
L
L
H
H
H
↑
L
H
NOTE:
2629 tbl 03
2629 tbl 02
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
COUT
VOUT = 0V
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
–0.5 to
V
Capacitance
VCC +0.5
VCC +0.5
2640 lnk 05
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2529 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.1
3
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
VIL
II H
II L
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State Output pins)(4)
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max.
VCC = Max.
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
—
IOZH
IOZL
II
—
µA
—
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
—
µA
V
VIK
VH
ICC
–0.7
200
0.01
mV
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
1
mA
2629tbl06
OUTPUT DRIVE CHARACTERISTICS FOR 29FCT52T/29FCT53T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
IOH = –6mA MIL.
2.4
2.0
—
3.3
3.0
0.3
—
V
IOH = –8mA COM'L.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 48mA MIL.
—
V
V
VOL
Output LOW Voltage
Short Circuit Current
VCC = Min.
VIN = VIH or VIL
VCC = Max., VO = GND(3)
0.55
IOL = 64mA COM'L.
IOS
–60
—
–120 –225
±1
mA
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2629tbl07
OUTPUT DRIVE CHARACTERISTICS FOR 29FCT2052T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
I
I
ODL
Output LOW Current
V
CC = 5V, VIN = VIH or VIL,
CC = 5V, VIN = VIH or VIL,
V
V
OUT= 1.5V(3)
16
–16
2.4
48
–48
3.3
—
—
—
mA
ODH
Output HIGH Current
Output HIGH Voltage
V
OUT= 1.5V(3)
mA
V
V
OH
OL
V
V
V
V
CC = Min.
I
I
I
OH = –12mA MIL.
OH = –15mA COM'L.
OL = 12mA
IN = VIH or VIL
CC = Min.
V
Output LOW Voltage
—
0.3
0.50
V
IN = VIH or VIL
2629tbl08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.1
4
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
VCC = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4) VCC = Max.
VIN = VCC FCTxxxT
VIN = GND
—
0.15
0.25
mA/
MHz
Outputs Open
OEA or OEB = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
FCT2xxxT
—
—
—
—
0.06
1.5
0.12
3.5
IC
Total Power Supply Current(6)
VIN = VCC FCTxxxT
VIN = GND
mA
Outputs Open
fCP = 10MHz
50% Duty Cycle
OEA or OEB = GND
FCT2xxxT
0.6
2.2
VIN = 3.4V FCTxxxT
VIN = GND FCT2xxxT
2.0
1.1
5.5
4.2
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
VIN = VCC FCTxxxT
VIN = GND
—
—
3.8
1.5
7.3(5)
4.0(5)
FCT2xxxT
50% Duty Cycle
OEA or OEB = GND
VIN = 3.4V FCTxxxT
VIN = GND FCT2xxxT
—
—
6.0
3.8
16.3(5)
13.0(5)
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
2629tbl09
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.1
5
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
29FCT52AT/53AT
29FCT52BT/53BT
29FCT2052BT
29FCT2052AT
Com'l.
Mil.
Com'l.
Mil.
. Max. Unit
Symbol
Parameter
Condition(1)
= 50pF
= 500
Min (2)
.
Max. Min (2)
.
Max. Min (2)
.
Max. Min (2)
t
t
t
t
t
t
t
PLH
Propagation Delay
CL
2.0
10.0
10.5
10.0
—
2.0
11.0
13.0
10.0
—
2.0
7.5
8.0
7.5
—
2.0
8.0
8.5
8.0
—
ns
ns
ns
ns
ns
ns
ns
PHL
CPA, CPB to An, Bn
Output Enable Time
OEA or OEB to An, Bn
Output Disable Time
OEA or OEB to An, Bn
Set-up Time, HIGH or LOW
An, Bn to CPA, CPB
Hold Time, HIGH or LOW
An, Bn to CPA, CPB
Set-up Time, HIGH or LOW
CEA, CEB to CPA, CPB
Hold Time, HIGH or LOW
CEA, CEB to CPA, CPB
Clock Pulse Width HIGH or
LOW(3)
R
L
Ω
PZH
PZL
PHZ
PLZ
SU
1.5
1.5
2.5
2.0
3.0
2.0
3.0
1.5
1.5
2.5
2.0
3.0
2.0
3.0
1.5
1.5
2.5
1.5
3.0
2.0
3.0
1.5
1.5
2.5
1.5
3.0
2.0
3.0
t
t
t
t
H
—
—
—
—
SU
H
—
—
—
—
—
—
—
—
W
—
—
—
—
ns
2629 tbl 10
29FCT52CT/53CT
29FCT2052CT
29FCT52DT
Com'l.
Max. Min (2) Max. Min (2)
Com'l.
Mil.
Mil.
. Max. Unit
Symbol
Parameter
Condition(1)
= 50pF
= 500
Min (2) Max. Min (2)
.
.
.
t
t
t
t
t
t
t
PLH
Propagation Delay
CL
2.0
1.5
1.5
2.5
1.5
3.0
2.0
3.0
6.3
7.0
6.5
—
2.0
7.3
8.0
7.5
—
2.0
4.5
5.6
4.3
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
PHL
CPA, CPB to An, Bn
Output Enable Time
OEA or OEB to An, Bn
Output Disable Time
OEA or OEB to An, Bn
Set-up Time, HIGH or LOW
An, Bn to CPA, CPB
Hold Time, HIGH or LOW
An, Bn to CPA, CPB
Set-up Time, HIGH or LOW
CEA, CEB to CPA, CPB
Hold Time, HIGH or LOW
CEA, CEB to CPA, CPB
Clock Pulse Width HIGH or
LOW(3)
R
L
Ω
PZH
PZL
PHZ
PLZ
SU
1.5
1.5
2.5
1.5
3.0
2.0
3.0
1.5
1.5
1.5
1.0
2.0
1.0
3.0
—
—
—
—
—
—
—
t
t
t
t
H
—
—
—
SU
H
—
—
—
—
—
—
W
—
—
—
ns
NOTES:
2629 tbl 11
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
6.1
6
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
VCC
7.0V
Closed
Enable Low
500Ω
Open
VOUT
All Other Tests
VIN
2629 lnk 12
Pulse
Generator
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
D.U.T.
50pF
C L
RT = Termination resistance: should be equal to ZOUT of the Pulse
500Ω
Generator.
T
R
2629 drw 03
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
PRESET
3V
2629 drw 05
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2629 drw 04
PROPAGATION DELAY
ENABLE
tPZL
DISABLE
tPLZ
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2629 drw 06
0V
2629 drw 07
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.1
7
IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XX 29FCT X
Temp. Range Family
XX
XX
X
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
E
L
SO
PY
Q
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
52AT
53AT
52BT
53BT
52CT
53CT
52DT
Non-inverting Octal Registered Transceiver
Inverting Octal Registered Transceiver
Blank
20
High Drive
Balanced Drive
54
74
–55
°C to +125°C
0
°
C to +70°C
2629 drw 08
6.1
8
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