72V3634L10PF8 [IDT]
TQFP-128, Reel;
| 型号： | 72V3634L10PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-128, Reel 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总34页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncBiFIFOTM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3624
IDT72V3634
IDT72V3644
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
FEATURES:
• Memory storage capacity:
IDT72V3624–256 x 36 x 2
IDT72V3634–512 x 36 x 2
IDT72V3644–1,024 x 36 x 2
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent clocked FIFOs buffering data in opposite
directions
• Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB
flags functions) or First Word Fall Through Timing (using ORA,
ORB, IRA, and IRB flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible version of the 5V operating
IDT723624/723634/723644
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• Serial or parallel programming of partial flags
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
Port-A
Control
Logic
CSA
W/RA
ENA
RAM ARRAY
256 x 36
36
36
MBA
512 x 36
1,024 x 36
36
FIFO1,
Mail1
Reset
Logic
MRS1
PRS1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
EFB/ORB
AEB
FFA/IRA
AFA
FIFO1
FIFO2
SPM
FS0/SD
Programmable Flag
Offset Registers
Timing
Mode
FWFT
FS1/SEN
A
0-A35
B0-B35
10
EFA/ORA
Status Flag
Logic
FFB/IRB
AFB
AEA
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
RAM ARRAY
256 x 36
36
36
512 x 36
CLKB
CSB
W/RB
ENB
MBB
BE
1,024 x 36
Port-B
Control
Logic
Mail 2
Register
BM
SIZE
MBF2
4664 drw01
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc.NSynGcBEiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
FEBRUARY 2009
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4664/5
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
fastas 6.5ns. Twoindependent256/512/1,024x36dual-portSRAMFIFOs
onboardeachchipbufferdatainoppositedirections.FIFOdataonPortBcan
beinputandoutputin36-bit,18-bit,or9-bitformatswithachoiceofBig-orLittle-
Endianconfigurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
DESCRIPTION:
TheIDT72V3624/72V3634/72V3644arepinandfunctionallycompatible
versionsoftheIDT723624/723634/723644,designedtorunoffa3.3Vsupply
forexceptionallylow-powerconsumption. Thesedevicesare monolithic,high-
speed,low-power,CMOSbidirectionalsynchronous(clocked)FIFOmemory
whichsupportsclockfrequenciesupto100MHzandhasreadaccesstimesas
PIN CONFIGURATION
INDEX
W/RA
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CLKB
PRS2
1
2
3
4
5
6
7
8
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
Vcc
B35
B34
B33
B32
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
4664 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or EFB/ORB)andacombinedFull/InputReadyFlag(FFA/IRAand FFB/IRB).
coincident. The enables for each port are arranged to provide a simple TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- whetherornottheFIFOmemoryisempty.FFshowswhetherthememoryis
nouscontrol.
fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox mode.IRindicateswhetherornottheFIFOhasavailablememorylocations.
registers.Themailboxregisters’widthmatchestheselectedPortBbuswidth. ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe
EachMailboxregisterhas a flag(MBF1 andMBF2)tosignalwhennewmail presenceofvaliddataontheoutputs.
has beenstored.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial aprogrammableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen
Reset.MasterResetinitializesthereadandwritepointerstothefirstlocationof aselectednumberofwordsremainintheFIFOmemory.AFAandAFBindicate
thememoryarray,configurestheFIFOforBig-orLittle-Endianbytearrange- whenthe FIFOcontains more thana selectednumberofwords.
mentandselectsserialflagprogramming,parallelflagprogramming,oroneof
threepossibledefaultflagoffsetsettings,8,16or64.TherearetwoMasterReset clockthatwritesdataintoitsarray.EFA/ORA,EFB/ORB,AEAandAEBaretwo-
pins, MRS1 and MRS2. stagesynchronizedtotheportclockthatreadsdatafromitsarray.Program-
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe mableoffsetsforAEA,AEB,AFAandAFBareloaded inparallelusingPortA
memory.UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., orinserialviatheSDinput.TheSerialProgrammingModepin(SPM)makes
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset thisselection.Threedefaultoffsetsettingsarealsoprovided.TheAEAandAEB
is useful since it permits flushing of the FIFO memory without changing any thresholdcanbesetat8,16or64locationsfromtheemptyboundaryandthe
configurationsettings.EachFIFOhasitsown,independentPartialResetpin, AFAandAFBthresholdcanbesetat8,16or64locationsfromthefullboundary.
PRS1 and PRS2.
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,
AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
thefirstwordwrittentoanemptyFIFOis depositedintothememoryarray.A If, at any time, the FIFO is not actively performing a function, the chip will
read operation is required to access that word (along with all other words automatically power down. During the power down state, supply current
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong- consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
word (36-bit wide) written to an empty FIFO appears automatically on the inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
outputs,noreadoperationisrequired(Nevertheless,accessingsubsequent
TheIDT72V3624/72V3634/72V3644arecharacterizedforoperationfrom
wordsdoesnecessitateaformalreadrequest).ThestateoftheBE/FWFTpin 0°Cto70°C.Industrialtemperaturerange(-40°Cto+85°C)isavailable.They
duringFIFOoperationdetermines themodeinuse.
arefabricatedusingIDT’shighspeed,submicronCMOStechnology.
EachFIFOhas a combinedEmpty/OutputReadyFlag(EFA/ORAand
3
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/O 36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-
EmptyFlag
O
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2is
lessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
AEB
PortBAlmost-
EmptyFlag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.Itis LOWwhenthenumberofwords inFIFO1is
lessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
AFA
PortAAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsin
FIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
AFB
PortBAlmost-
Full Flag
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofemptylocationsin
FIFO2is less thanorequaltothevalueintheAlmost-FullBOffsetregister,Y2.
B0-B35
PortAData
I/O 36-bitbidirectionaldataportforsideB.
BE/FWFT Big-Endian/
FirstWord
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this
case, dependingonthe bus size, the mostsignificantbyte orwordonPortAis readfromPortBfirst
(A-to-Bdataflow)orwrittentoPortBfirst(B-to-Adataflow). ALOWonBEwillselectLittle-Endianoperation.
In this case, the leastsignificantbyte orwordonPortAis readfromPortBfirst(forA-to-Bdata flow)or
written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on
FWFTselectsIDTStandardmode,aLOWselectsFirstWordFallThroughmode. Oncethetimingmodehas
beenselected,thelevelonFWFTmustbestaticthroughoutdeviceoperation.
Fall Through
Select
BM
Bus-Match
Select
(Port B)
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
LOWselects longwordoperation. BMworks withSIZEandBEtoselectthe bus size andendian
arrangementforPortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.
CLKA
CLKB
PortAClock
I
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbeasynchronous
orcoincidenttoCLKB. FFA/IRA, EFA/ORA, AFA, andAEA are allsynchronizedtothe LOW-to-HIGH
transitionofCLKA.
PortBClock
I
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbeasynchronous
orcoincidenttoCLKA.FFB/IRB,EFB/ORB,AFB,andAEB aresynchronizedtotheLOW-to-HIGHtransition
ofCLKB.
CSA
CSB
Port A Chip
Select
I
CSA mustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The A0-A35
outputsareinthehigh-impedancestatewhenCSAisHIGH.
Port B Chip
Select
I
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB. The
B0-B35outputs areinthehigh-impedancestatewhenCSBis HIGH.
EFA/ORA PortAEmpty/
OutputReady
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFA functionis selected. EFA indicates whether
ornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis selected. ORAindicates the
presence ofvaliddata onA0-A35outputs, available forreading. EFA/ORAis synchronizedtothe LOW-to-
HIGHtransitionofCLKA.
EFB/ORB PortBEmpty/
OutputReady
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the EFB functionis selected. EFB indicates whether
ornottheFIFO1memoryis empty. IntheFWFTmode,theORBfunctionis selected. ORBindicates the
presenceofvaliddataontheB0-B35outputs,availableforreading. EFB/ORBissynchronizedtotheLOW-to-
HIGHtransitionofCLKB.
ENA
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.
ENB
FFA/IRA
Port A Full/
Input Ready
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates
whetherornotthe FIFO1memoryis full. Inthe FWFTmode, the IRAfunctionis selected. IRAindicates
whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the
LOW-to-HIGHtransitionofCLKA.
FFB/IRB
PortB Full/
Input Ready
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFB functionis selected. FFB indicates whether
or not the FIFO2 memory is full. In theFWFT mode, the IRB function is selected. IRB indicates whether or
not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH
transitionofCLKB.
4
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
FS1/SEN FlagOffsetSelect1/
I
FS1/SEN andFS0/SDare dual-purpose inputs usedforflagoffsetregisterprogramming. DuringMaster
Reset,FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffset
registerprogrammingmethods are available:automaticallyloadone ofthree presetvalues (8, 16, or64),
parallelloadfromPortA, andserialload.
Serial Enable,
FS0/SD FlagOffsetSelect0/
SerialData
I
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenablesynchronous
totheLOW-to-HIGHtransitionofCLKA. When FS1/SEN is LOW, a risingedge onCLKAloadthe bitpresent
onFS0/SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe offsetregisters is 32
for the 72V3624, 36 for the 72V3634, and 40 for the 72V3644. The first bit write stores the Y-register (Y1)
MSBandthelastbit writestores theX-register(X2)LSB.
MBA
MBB
MBF1
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBAselectsdatafromthemail2registerforoutputandaLOWlevel
selectsFIFO2outputregisterdataforoutput.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutputandaLOWlevel
selectsFIFO1outputregisterdataforoutput.
Mail1Register
Flag
O
MBF1 is setLOWby a LOW-to-HIGH transition of CLKA that writes data tothe mail1register. Writes to
themail1registerare inhibitedwhile MBF1 is LOW. MBF1 is setHIGHbya LOW-to-HIGHtransitionofCLKB
when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial
ResetofFIFO1.
MBF2
MRS1
Mail2Register
Flag
O
I
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.Writestothe
mail2registerareinhibitedwhileMBF2is LOW.MBF2is setHIGHbyaLOW-to-HIGHtransitionofCLKA
when a Port A read is selected and MBA is HIGH. MBF2 is setHIGHfollowingeithera MasterorPartial
ResetofFIFO2.
FIFO1Master
Reset
A LOW on this pin initializes the FIFO1 read and write pointers to the first locationof memory and sets the
Port B output register to all zeroes. A LOW-to-HIGH transition onMRS1selectstheprogrammingmethod(serial
orparallel)andone ofthree programmable flagdefaultoffsets forFIFO1andFIFO2. Italsoconfigures Port
Bforbussizeandendianarrangement. FourLOW-to-HIGHtransitionsofCLKA andfourLOW-to-HIGHtransitions
ofCLKBmustoccurwhileMRS1isLOW.
MRS2
FIFO2Master
Reset
I
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemory andsetsthe
PortAoutputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS2,toggledsimultaneouslywithMRS1,selects
theprogrammingmethod(serialorparallel)andoneoftheprogrammableflagdefaultoffsetsforFIFO2. FourLOW-
to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
PRS1
PRS2
SIZE
FIFO1Partial
Reset
I
I
I
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthe
PortBoutputregistertoallzeroes. DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,
programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
FIFO2Partial
Reset
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePort
A outputregistertoallzeroes. DuringPartialReset,thecurrentlyselectedbus size,endianarrangement,
programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
BusSizeSelect
AHIGHonthispinwhenBMisHIGHselectsbytebus(9-bit)sizeonPortB. ALOWonthispinwhenBMisHIGH
selects word(18-bit)bus size. SIZEworks withBM andBEtoselectthebussizeandendianarrangementforPort
B. The level of SIZE mustbestaticthroughoutdeviceoperation.
SPM
SerialProgramming
Mode
I
I
I
ALOWonthispinselectsserialprogrammingofpartialflagoffsets. AHIGHonthispinselectsparallelprogramming
or defaultoffsets (8, 16, or64).
W/RA
W/RB
Port-AWrite/
ReadSelect
AHIGHselectsawriteoperationandaLOWselectsareadoperationonPortAforaLOW-to-HIGHtransitionof
CLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.
Port-BWrite/
ReadSelect
ALOWselectsawriteoperationandaHIGHselectsareadoperationonPortBforaLOW-to-HIGHtransitionof
CLKB. The B0-B35outputs are inthe HIGHimpedance state whenW/RBis LOW.
5
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
Min.
3.0
2
Typ.
3.3
—
Max.
Unit
(1)
VCC
SupplyVoltage
3.6
V
VIH
VIL
IOH
IOL
TA
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
VCC+0.5
0.8
V
—
—
—
0
—
V
—
–4
mA
mA
°C
—
8
—
70
NOTE:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70° C; JEDEC JESD8-A compliant.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3624
IDT72V3634
IDT72V3644
Commercial
tCLK = 10(1), 15ns
Symbol
VOH
Parameter
Test Conditions
IOH = –4 mA
IOL = 8 mA
Min.
2.4
—
Typ.(2)
—
—
—
—
—
—
4
Max.
—
Unit
V
OutputLogic"1"Voltage
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
VOL
OutputLogic"0"Voltage
0.5
±10
±10
5
V
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
—
µ A
µ A
mA
mA
pF
ILO
—
ICC2(3)
ICC3(3)
Standby Current (with CLKA and CLKB running)
StandbyCurrent(noclocksrunning)
InputCapacitance
VI = VCC - 0.2V or 0
—
VI = VCC - 0.2V or 0
f = 1 MHz
—
1
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
—
8
—
pF
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70° C; JEDEC JESD8-A compliant.
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
5. Industrial temperature range is available by special order.
6
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3624/72V3634/72V3644 with
CLKAandCLKBsettofS. Alldatainputs anddataoutputs changestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC x fo)
N
where:
N
CL
fo
=
=
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
output capacitance load
switchingfrequencyofanoutput
200
175
150
fdata = 1/2 fS
TA = 25οC
CL = 0 pF
VCC = 3.6V
VCC = 3.3V
125
100
VCC = 3.0V
75
50
25
0
80
100
0
10
20
30
40
50
60
70
90
4664 drw03
fS Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0°Cto +70°C; JEDEC JESD8-A compliant
IDT72V3624L10(1)
IDT72V3634L10(1)
IDT72V3644L10(1)
IDT72V3624L15
IDT72V3634L15
IDT72V3644L15
Symbol
Parameter
Min.
—
10
4.5
4.5
3
Max.
100
—
Min.
—
15
6
Max.
66.7
—
Unit
MHz
ns
fS
Clock Frequency, CLKA or CLKB
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
—
—
ns
PulseDuration,CLKAandCLKBLOW
SetupTime, A0-A35before CLKA↑andB0-B35before CLKB↑
SetupTimeCSAbeforeCLKA↑;CSBbeforeCLKB↑
—
6
—
ns
—
4
—
ns
tENS1
tENS2
4
—
4.5
4.5
—
ns
Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB
beforeCLKB↑
3
—
—
ns
(2)
tRSTS
tFSS
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑or CLKB↑
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH
SetupTime, BE/FWFT beforeMRS1 andMRS2HIGH
Setup Time, SPM before MRS1 and MRS2 HIGH
SetupTime,FS0/SDbeforeCLKA↑
5
7.5
7.5
7.5
3
—
—
—
—
—
—
—
—
—
5
7.5
7.5
7.5
4
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBES
tSPMS
tSDS
tSENS
tFWS
tDH
SetupTime,FS1/SENbeforeCLKA↑
3
4
SetupTime,BE/FWFTbeforeCLKA↑
0
0
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
0.5
0.5
1
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and
MBBafterCLKB↑
1
(2)
tRSTH
tFSH
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑
4
2
—
—
—
—
—
—
—
—
4
2
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
Hold Time, SPM after MRS1 and MRS2 HIGH
HoldTime, FS0/SDafterCLKA↑
tBEH
2
2
tSPMH
tSDH
2
2
0.5
0.5
2
1
tSENH
tSPH
HoldTime,FS1/SENHIGHafterCLKA↑
1
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
2
tSKEW1(3)
SkewTime betweenCLKA↑andCLKB↑forEFA/ORA,EFB/ORB,FFA/IRA,
and FFB/IRB
5
7.5
tSKEW2(3,4) Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
12
—
12
—
ns
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
8
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF
Commercial: VCC = 3.3V +/- 0.30V; for 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V ; TA = 0°C to +70°C; JEDEC JESD8-A compliant
IDT72V3624L10(1)
IDT72V3634L10(1)
IDT72V3644L10(1)
IDT72V3624L15
IDT72V3634L15
IDT72V3644L15
Symbol
tA
Parameter
Min.
2
Max.
6.5
6.5
6.5
6.5
6.5
6.5
Min.
2
Max.
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
Propagation Delay Time, CLKA↑ to FFA/IRAandCLKB↑ to FFB/IRB
PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑toEFB/ORB
PropagationDelayTime, CLKA↑toAEA andCLKB↑toAEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
10
8
tWFF
tREF
tPAE
tPAF
tPMF
2
2
ns
1
1
8
ns
1
1
8
ns
1
1
8
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW orMBF2 HIGH and CLKB↑
to MBF2 LOW or MBF1 HIGH
0
0
8
ns
tPMR
tMDV
tRSF
PropagationDelayTime, CLKA↑toB0-B35(2) andCLKB↑toA0-A35(3)
2
2
1
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid
6.5
10
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and
MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2
HIGH
tEN
tDIS
Enable Time, CSA or W/RA LOW to A0-A35 Active and CSB LOW andW/RB
2
1
6
6
2
1
10
8
ns
ns
HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB
HIGH or W/RBLOWtoB0-B35atHIGHimpedance
NOTES:
1. For 10ns (100 MHz operation), VCC = 3.3V +/- 0.15V; TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
9
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
writtentoorreadfromPortB.Thisselectiondeterminestheorderbywhichbytes
(or words) of data are transferred through this port. For the following
illustrations,assumethatabyte(orword)bussizehasbeenselectedforPort
B. (Note thatwhenPortBis configuredfora longwordsize, the Big-Endian
SIGNALDESCRIPTION
MASTER RESET (MRS1, MRS2)
Afterpowerup,aMasterReset operationmustbeperformedbyproviding
aLOWpulsetoMRS1andMRS2simultaneously. Afterwards,eachofthetwo
FIFOmemoriesoftheIDT72V3624/72V3634/72V3644undergoesacomplete
resetbytakingitsassociatedMasterReset(MRS1,MRS2)inputLOWforat
leastfourPortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGH
transitions. TheMasterResetinputscanswitchasynchronouslytotheclocks.
AMasterReset initializes the associatedwrite andreadpointers tothe first
locationofthememoryandforces theFull/InputReadyflag(FFA/IRA,FFB/
IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost-Emptyflag(AEA,AEB)LOWandforcestheAlmost-Fullflag(AFA,AFB)
HIGH. AMasterResetalsoforcestheassociatedMailboxFlag(MBF1,MFB2)
oftheparallelmailboxregisterHIGH. AfteraMasterReset,theFIFO's Full/
InputReadyflagissetHIGHaftertwowriteclockcycles. ThentheFIFOisready
tobewrittento.
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input
latches the values ofthe Big-Endian(BE)inputfordeterminingthe orderby
whichbytes are transferredthroughPortB. Italso latches the values ofthe
Flag Select (FS0, FS1) and Serial Programming Mode (SPM) inputs for
choosingtheAlmost-FullandAlmost-Emptyoffsetprogrammingmethod.
ALOW-to-HIGHtransitionontheFIFO2MasterReset(MRS2)clearsthe
Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the
FIFO2MasterReset(MRS2)togetherwiththeFIFO1MasterReset(MRS1)
inputlatchesthevalueoftheBig-Endian(BE)inputforPortBandalsolatches
thevaluesoftheFlagSelect(FS0,FS1)andSerialProgrammingMode(SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method. (FordetailsseeTable1,FlagProgramming,andtheProgramming
theAlmost-EmptyandAlmost-FullFlagssection). TherelevantFIFOMaster
Resettimingdiagramcanbe foundinFigure 3.
1
functionhas noapplicationandthe BEinputis a “don’tcare” .)
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata
ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
dataismovinginthedirectionfromPortBtoPortA,thebyte(word)writtento
PortBfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortBlastwillbereadfromPortAastheleast
significantbyte (word)ofthe longword.
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata
ismovinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
dataismovinginthedirectionfromPortBtoPortA,thebyte(word)writtento
PortBfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word;thebyte(word)writtentoPortBlastwillbereadfromPortAasthemost
significantbyte(word)ofthelongword.RefertoFigure2foranillustrationof
the BE function. See Figure 3 (Master Reset) for the Endian select timing
diagram.
— TIMING MODE SELECTION
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice
betweentwopossible timingmodes:IDTStandardmode orFirstWordFall
Through(FWFT)mode.OncetheMasterReset(MRS1,MRS2)inputisHIGH,
aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(forFIFO1)andCLKB(forFIFO2)willselectIDTStandardmode.Thismode
usestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereare
anywords presentinthe FIFOmemory. Ituses the FullFlagfunction(FFA,
FFB)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must
be requestedusinga formalreadoperation.
OncetheMasterReset(MRS1,MRS2)inputisHIGH,aLOWontheBE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKB(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata
outputs(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata
outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby
performingaformalreadoperation.
PARTIAL RESET (PRS1, PRS2)
EachofthetwoFIFOmemoriesofthesedevicesundergoesalimitedreset
bytakingitsassociatedPartialReset(PRS1,PRS2)inputLOWforatleastfour
PortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.
ThePartialResetinputs canswitchasynchronouslytotheclocks.APartial
ResetinitializestheinternalreadandwritepointersandforcestheFull/Input
Readyflag(FFA/IRA,FFB/IRB)LOW,theEmpty/OutputReadyflag(EFA/
ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Fullflag(AFA,AFB)HIGH.APartialResetalsoforcestheMailboxFlag
(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,the
FIFO’s Full/InputReadyflagis setHIGHaftertwowrite clockcycles. Then
the FIFO is ready to be written to.
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof
the reset operation. A Partial Reset may be useful in the case where
reprogrammingaFIFOfollowingaMasterResetwouldbeinconvenient.See
Figure4forthePartialResettimingdiagram.
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation.Refer
toFigure3(MasterReset)foraFirstWordFallThroughselecttimingdiagram.
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS
FourregistersintheIDT72V3624/72V3634/72V3644areusedtoholdthe
offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags.ThePortBAlmost-
Emptyflag(AEB)OffsetregisterislabeledX1andthePortAAlmost-Emptyflag
(AEA)Offsetregisteris labeledX2. The PortAAlmost-Fullflag(AFA)Offset
registeris labeledY1andthe PortBAlmost-Fullflag(AFB)Offsetregisteris
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
isactive,permittingachoiceofBigorLittle-Endianbytearrangementfordata
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
10
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
transitionofMRS1andMRS2.Afterthisresetiscomplete,theXandYregister
valuesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-to-HIGH
transitionofCLKAthattheFS1/SENinputisLOW.Thereare32-,36-,or40-
bit writes needed to complete the programming for the IDT72V3624,
IDT72V3634,orIDT72V3644,respectively.Thefourregistersarewrittenin
theorderY1,X1,Y2,andfinally,X2. Thefirst-bitwritestoresthemostsignificant
bitoftheY1registerandthelast-bitwritestorestheleastsignificantbitoftheX2
register.Eachregistervaluecanbeprogrammedfrom1to252(IDT72V3624),
1 to 508 (IDT72V3634), or 1 to 1,020 (IDT72V3644).
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,thePort
AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
isloadedtoallownormalFIFO1operation.ThePortBFull/InputReady(FFB/
IRB)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until
allregisterbitsarewritten.FFB/IRBissetHIGHbytheLOW-to-HIGHtransition
ofCLKBafterthelastbitisloadedtoallownormalFIFO2operation.SeeFigure
6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (IDT Standard and FWFT Modes) timing diagram.
labeledY2.TheindexofeachregisternamecorrespondstoitsFIFOnumber.
TheoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofaFIFO,
programmedinparallelusingtheFIFO’sPortAdatainputs,orprogrammed
in serial using the Serial Data (SD) input (see Table 1).
SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard
andFWFTmodes.
— PRESET VALUES
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(SPM)
andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH
transitionofitsMasterResetinput(MRS1,MRS2).Forexample,toloadthe
preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when
FlFO1reset(MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2
areloadedwithoneofthepresetvaluesinthesamewaywithFIFO2Master
Reset(MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For
relevantpresetvalue loadingtimingdiagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
FIFO WRITE/READ OPERATION
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster
ResetonbothFlFOssimultaneouslywithSPMHIGHandFS0andFS1LOW
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is
complete,thefirstfourwritestoFIFO1donotstoredataintheRAMbutload
theoffsetregistersintheorderY1,X1,Y2,X2.ThePortAdatainputsusedby
the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The highest numbered input is
used as the most significant bit of the binary number in each case. Valid
programmingvaluesfortheregistersrangefrom1to252fortheIDT72V3624;
1to508fortheIDT72V3634;and1to1,020fortheIDT72V3644.Afterallthe
offsetregistersareprogrammedfromPortA,thePortBFull/InputReadyflag
(FFB/IRB)issetHIGH,andbothFIFOsbeginnormaloperation.RefertoFigure
5foratimingdiagramillustrationofparallelprogrammingoftheflagoffsetvalues.
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-
impedance state wheneitherCSA orW/RAis HIGH. The A0-A35lines are
active outputs whenbothCSA andW/RAare LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSAisLOW,W/RAisHIGH,ENAisHIGH,MBAis
LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand
writes on Port A are independent of any concurrent Port B operation.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read
select(W/RA).ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB).TheB0-B35
lines are inthe high-impedance state wheneither CSB is HIGHorW/RBis
— SERIAL LOAD
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset
withSPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH
TABLE 1 — FLAG PROGRAMMING
SPM
H
FS1/SEN FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
↑
X
↑
X
↑
↑
↑
↑
↑
↑
64
X
H
64
64
H
16
X
H
16
16
H
8
X
H
8
Parallel programming via Port A
Serial programming via SD
Reserved
8
Parallel programming via Port A
Serial programming via SD
Reserved
H
L
L
L
Reserved
Reserved
L
Reserved
Reserved
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
11
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput
registersonlywhenareadisselectedusingtheport’sChipSelect,Write/Read
select,Enable,andMailboxselect.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause
theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe
ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.
Instead, data residing in the FIFO's memory array is clocked to the output
registeronlywhenareadisselectedusingtheport’sChipSelect,Write/Read
select,Enable,andMailboxselect.WriteandreadtimingdiagramsforPortA
canbefoundinFigure7and14. RelevantPortBwriteandreadcycle timing
diagrams togetherwithBus-MatchingandEndianselectoperations canbe
found in Figures 8 through 13.
LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RBis
HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhenCSB is LOW,W/RBis LOW,ENBis HIGH,MBBis
LOW,andFFB/IRBisHIGH.DataisreadfromFIFO1totheB0-B35outputs
byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB
isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand
writes on Port B are independent of any concurrent Port A operation.
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects
andWrite/Readselects areonlyforenablingwriteandreadoperations and
arenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable
isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay
changestates duringthesetupandholdtimewindowofthecycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
High-Impedance
Input
None
None
H
H
L
Input
FIFO1 write
Mail1write
H
L
↑
Input
X
↑
Output
Output
Output
Output
None
L
H
L
L
FIFO2read
None
L
H
H
X
↑
L
H
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
H
L
L
L
L
L
L
L
X
L
X
L
X
X
L
X
X
↑
High-Impedance
Input
None
None
L
H
H
L
Input
FIFO2 write
Mail2write
L
H
L
↑
Input
H
H
H
H
X
↑
Output
Output
Output
Output
None
H
L
L
FIFO1read
None
H
H
X
↑
H
Mail1 read (set MBF1 HIGH)
SYNCHRONIZED FIFO FLAGS
EachFIFOis synchronizedtoits portclockthroughatleasttwoflip-flop
EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready
stages.Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability (ORA,ORB)functionisselected.WhentheOutput-ReadyflagisHIGH,new
ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone dataispresentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. thepreviousdatawordispresentintheFIFOoutputregisterandattempted
EFB/ORB,AEB,FFB/IRB,andAFBaresynchronizedtoCLKB.Tables4and FIFO reads are ignored.
5 show the relationship of each port flag to FIFO1 and FIFO2.
12
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT72V3624
IDT72V3634
IDT72V3644
EFB/ORB
AEB
AFA
FFA/IRA
0
1toX1
0
1toX1
0
1toX1
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
(X1+1)to[256-(Y1+1)]
(256-Y1)to255
256
(X1+1)to[512-(Y1+1)]
(512-Y1)to511
512
(X1+1)to[1,024-(Y1+1)]
(1,024-Y1)to1,023
1,024
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKA
Synchronized
to CLKB
Number of Words in FIFO Memory(1,2)
(3)
(3)
(3)
IDT72V3624
IDT72V3634
IDT72V3644
EFA/ORA
AEA
AFB
H
FFB/IRB
0
1toX2
0
1toX2
0
1toX2
L
H
H
H
H
L
L
H
H
H
H
L
H
(X2+1)to[256-(Y2+1)]
(256-Y2)to255
256
(X2+1)to[512-(Y2+1)]
(512-Y2)to511
512
(X2+1)to[1,024-(Y2+1)]
(1,024-Y2)to1,023
1,024
H
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAMmemory Flagwillindicatethepresenceofdataavailableforreadinginaminimumof
forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious twocyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlag
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare isLOWifawordinmemoryisthenextdatatobesenttotheFlFOoutputregister
ignored.
andtwocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsed
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW
thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes, untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
the FIFOreadpointeris incrementedeachtime a newwordis clockedtoits forcing the Empty Flag HIGH; only then can data be read.
outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
memorystatusisempty,empty+1,orempty+2. attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted can be the first synchronization cycle (see Figures 15, 16, 17, and 18).
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady
flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB)
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntil functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta- HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites
outputregister.
to the FIFO are ignored.
13
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat offill.Therefore,the Almost-Fullflagofa FIFOcontaining[256/512/1,024-
writesdatatoitsarray.ForbothFWFTandIDTStandardmodes,eachtime (Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine notelapsedsince the readthatreducedthe numberofwords inmemoryto
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer [256/512/1,024-(Y+1)].AnAlmost-FullflagissetHIGHbythesecondLOW-
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2. to-HIGHtransitionofitssynchronizingclockaftertheFIFOreadthatreduces
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready thenumberofwordsinmemoryto[256/512/1,024-(Y+1)].ALOW-to-HIGH
to be written to in a minimum of two cycles of the Full/Input Ready flag transitionofanAlmost-Fullflagsynchronizingclockbeginsthefirstsynchro-
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthan
twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince
the next memory write location has been read. The second LOW-to-HIGH
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets
the Full/InputReadyflagHIGH.
nizationcycleifitoccursattime tSKEW2 orgreaterafterthereadthatreduces
the number of words in memory to [256/512/1,024-(Y+1)]. Otherwise, the
subsequentsynchronizingclockcyclemaybethefirstsynchronizationcycle
(see Figure 25 and 26).
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcycle
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenPortAandPortBwithoutputtingitinqueue.TheMailbox
select(MBA,MBB)inputs choosebetweenamailregisterandaFIFOfora
port data transfer operation. The usable width of both the Mail1 and Mail2
registersmatchestheselectedbussizeforPortB.
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
data from its array. The state machine that controls an Almost-Empty flag
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.
Thealmost-emptystateisdefinedbythecontentsofregisterX1forAEBand
registerX2forAEA.Theseregisters areloadedwithpresetvalues duringa
FIFOreset,programmedfromPortA,orprogrammedserially(seeAlmost-
Empty flag and Almost-Full flag offset programming section). An Almost-
EmptyflagisLOWwhenitsFIFOcontainsXorlesswordsandisHIGHwhen
itsFIFOcontains(X+1)ormorewords.AdatawordpresentintheFIFOoutput
registerhas beenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel
offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsince
thewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflagisset
HIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition
ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization
cycleifitoccursattimetSKEW2 orgreaterafterthewritethatfillstheFIFOto(X+1)
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register
employsdatalinesA0-A35.IftheselectedPortBbussizeis18bits,thenthe
usablewidthoftheMail1RegisteremploysdatalinesA0-A17.(Inthiscase,
A18-A35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,then
theusablewidthoftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,
A9-A35 are don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
RegisterwhenaPortBwriteisselectedbyCSB,W/RB,andENBwithMBB
HIGH.IftheselectedPortBbussizeisalso36bits,thentheusablewidthof
theMail2employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,
thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthis
case,B18-B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,
thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B8.(Inthis
case, B9-B35are don’tcare inputs.)
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe
words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst mailregisterwhenthe portMailboxselectinputis HIGH.
synchronization cycle. (See Figure 23 and 24).
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition
onCLKBwhenaPortBreadisselectedbyCSB,W/RB,andENBwithMBB
ALMOST-FULL FLAGS (AFA, AFB)
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthis
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors case,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailboxdata
a write pointer and read pointer comparator that indicates when the FIFO are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate
isdefinedbythecontentsofregisterY1forAFAandregisterY2forAFB.These onCLKAwhenaPortAreadisselectedbyCSA,W/RA,andENAwithMBA
registersareloadedwithpresetvaluesduringaFlFOreset,programmedfrom HIGH.
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition
PortA,orprogrammedserially(seeAlmost-EmptyflagandAlmost-Fullflag
Fora 36-bitbus size, 36bits ofmailboxdata are placedonA0-A35. For
offsetprogrammingsection).AnAlmost-FullflagisLOWwhenthenumberof an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase,
words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) A18-A35are indeterminate.)Fora 9-bitbus size,9bits ofmailboxdata are
fortheIDT72V3624,IDT72V3634,orIDT72V3644respectively.AnAlmost- placedonA0-A8. (Inthis case, A9-A35are indeterminate.)
Fullflagis HIGHwhenthe numberofwords inits FIFOis less thanorequal
Thedatainamailregisterremainsintactafteritisreadandchangesonly
to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT72V3624, whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect
IDT72V3634,orIDT72V3644respectively.Notethatadatawordpresentin onmailboxdata.FormailregisterandMailRegisterFlagtimingdiagrams,see
the FIFOoutputregisterhas beenreadfrommemory.
Figure 27 and 28.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
arerequiredafteraFIFOreadforits Almost-Fullflagtoreflectthenewlevel
14
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
BUS SIZING
example, when a word-size bus is selected, then mailbox data can be
The Port B bus can be configured in a 36-bit long word, 18-bit word, or transmitted only between A0-A17 and B0-B17. When a byte-size bus is
9-bit byte format for data read from FIFO1 or written to FIFO2. The levels selected,thenmailboxdatacanbetransmittedonlybetweenA0-A8andB0-
appliedtothePortBBus Sizeselect(SIZE)andtheBus-Matchselect(BM) B8. (See Figures 27 and 28).
determinethePortBbussize.TheselevelsshouldbestaticthroughoutFIFO
operation.BothbussizeselectionsareimplementedatthecompletionofMaster BUS-MATCHING FIFO1 READS
Reset,bythetimetheFull/InputReadyflagissetHIGH,asshowninFigure2.
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.Ifalong
TwodifferentmethodsforsequencingdatatransferareavailableforPort wordbus sizeis implemented,theentirelongwordimmediatelyshifts tothe
Bwhenthebussizeselectioniseitherbyte-orword-size.Theyarereferred FIFO1outputregister.IfbyteorwordsizeisimplementedonPortB,onlythe
toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant firstoneortwobytesappearontheselectedportionoftheFIFO1outputregister,
bytefirst).ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW- with the rest of the long word stored in auxiliary registers. In this case,
to-HIGHtransitionofMRS1andMRS2selectstheendianmethodthatwillbe subsequentFIFO1readsoutputtherestofthelongwordtotheFIFO1output
active during FIFO operation. BE is a don’t care input when the bus size register in the order shown by Figure 2.
selected for Port B is long word. The endian method is implemented at the
WhenreadingdatafromFIFO1inbyteorwordformat,theunusedB0-B35
completionofMasterReset,bythetimetheFull/InputReadyflagissetHIGH, outputsareindeterminate.
as shown in Figure 2.
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories
BUS-MATCHING FIFO2 WRITES
ontheIDT72V3624/72V3634/72V3644.Bus-matchingoperationsaredone
afterdataisreadfromtheFIFO1RAMandbeforedataiswrittentotheFIFO2
RAM. These bus-matching operations are not available when transferring
data via mailbox registers. Furthermore, both the word- and byte-size bus
selections limit the width of the data bus that can be used for mail register
operations.Inthiscase,onlythosebytelanesbelongingtotheselectedword-
orbyte-sizebus cancarrymailboxdata.Theremainingdataoutputs willbe
indeterminate. The remaining data inputs will be don’t care inputs. For
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary
registers.TheCLKBrisingedgethatwritesthefourthbyteorthesecondword
oflongwordtoFIFO2alsostorestheentirelongwordintheFIFO2memory.
The bytes are arranged in the manner shown in Figure 2.
WhenwritingdatatoFIFO2inbyteorwordformat,theunusedB0-B35inputs
aredon'tcareinputs.
15
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
A35 A27
A26 A18
A17 A9
A8 A0
BYTE ORDER ON PORT A:
Write to FIFO1/
Read from FIFO2
D
A
B
C
B35 B27
B26 B18
B17 B9
B8 B0
BYTE ORDER ON PORT B:
BE BM SIZE
Read from FIFO1/
Write to FIFO2
A
B
D
C
X
L
X
(a) LONG WORD SIZE
B35 B27
B35 B27
B26 B18
B17 B9
B8 B0
1st: Read from FIFO1/
Write to FIFO2
BE BM SIZE
A
B
H
H
L
B26 B18
B17 B9
B8 B0
2nd: Read from FIFO1/
Write to FIFO2
C
D
(b) WORD SIZE
BIG ENDIAN
B35 B27
B35 B27
B26 B18
B17 B9
B8 B0
1st: Read from FIFO1/
Write to FIFO2
BE BM SIZE
C
D
L
H
L
B26 B18
B17 B9
B8 B0
2nd: Read from FIFO1/
Write to FIFO2
A
B
(c) WORD SIZE
LITTLE-ENDIAN
B35 B27
B35 B27
B35 B27
B35 B27
B26 B18
B17 B9
B8 B0
BE BM SIZE
1st: Read from FIFO1/
Write to FIFO2
A
H
H
H
B26 B18
B26 B18
B26 B18
B17 B9
B17 B9
B17 B9
B8 B0
2nd: Read from FIFO1/
Write to FIFO2
B
B8 B0
3rd: Read from FIFO1/
Write to FIFO2
C
B8 B0
4th: Read from FIFO1/
Write to FIFO2
D
(d) BYTE SIZE
BIG-ENDIAN
B35 B27
B35 B27
B35 B27
B35 B27
B26 B18
B17 B9
B8 B0
BE BM SIZE
1st: Read from FIFO1/
Write to FIFO2
D
L
H
H
B26 B18
B26 B18
B17 B9
B17 B9
B8 B0
2nd: Read from FIFO1/
Write to FIFO2
C
B8 B0
3rd: Read from FIFO1/
Write to FIFO2
B
B26 B18
B17 B9
B8 B0
4th: Read from FIFO1/
Write to FIFO2
A
4664 drw04
(e) BYTE SIZE
LITTLE-ENDIAN
Figure 2. Bus Sizing
16
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
t
RSTS
tRSTH
MRS1
BE/FWFT
SPM
t
BEH
t
BES
tFWS
BE
0,1
FWFT
t
SPMS
t
SPMH
t
FSS
tFSH
FS1,FS0
FFA/IRA
EFB/ORB
AEB
t
WFF
t
WFF
(3)
REF
t
t
RSF
t
RSF
AFA
t
RSF
MBF1
4664 drw05
NOTES:
1. FIFO2 Master Reset (MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2.
2. PRS1 must be HIGH during Master Reset.
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)
CLKA
CLKB
t
RSTS
tRSTH
PRS1
t
WFF
t
WFF
FFA/IRA
(3)
tREF
EFB/ORB
AEB
t
RSF
t
RSF
AFA
t
RSF
MBF1
4664 drw06
NOTES:
1. Partial Reset is performed in the same manner for FIFO2.
2. MRS1 must be HIGH during Partial Reset.
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. FIFO1 Partial Reset(1) (IDT Standard and FWFT Modes)
17
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
2
1
4
MRS1,
MRS2
t
FSS
t
FSH
SPM
t
FSS
t
FSH
0,0
FS1,FS0
t
WFF
FFA/IRA
(1)
tSKEW1
tENS2
tENH
ENA
tDH
tDS
A0-A35
AEB Offset
AFA Offset
AFB Offset
(Y 2)
AEA Offset
(X 2)
First Word to FIFO1
(X1)
(Y1)
CLKB
1
2
t
WFF
FFB/IRB
4664 drw07
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
4
MRS1,
MRS2
t
FSS
tFSH
SPM
FFA/IRA
FS1/SEN
t
WFF
(1)
SKEW
t
t
SENS
t
FSS
t
SENH
SDH
t
SENS
tSENH
tSPH
tSDS
t
tSDH
tSDS
(3)
FS0/SD
AFA Offset (Y1) MSB
AEA Offset (X2) LSB
CLKB
4
t
WFF
4664 drw08
FFB/IRB
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA and FFB/IRB is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)
18
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA HIGH
t
ENH
ENH
t
ENS1
CSA
t
ENS2
t
W/RA
t
ENS2
t
ENH
ENH
MBA
ENA
tENS2
tENS2
tENH
t
ENS2
tENH
t
tDS
tDH
W1(1)
W2(1)
A0 - A35
No Operation
4664 drw09
NOTE:
1. Written to FIFO1.
Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
FFB/IRB HIGH
tENS1
tENS2
tENS2
t
ENH
CSB
tENH
W/RB
tENH
MBB
tENS2
tENS2
tENH
tENH
tENS2
tENH
ENB
tDH
tDS
W1(1)
W2(1)
B0-B35
No Operation
4664 drw10
NOTE:
1. Written to FIFO2.
DATA SIZE TABLE FOR LONG-WORD WRITES TO FIFO2
SIZE MODE(1)
SIZE
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
BM
BE
B35-B27
B26-B18
B17-B9
B8-B0
A35-A27
A26-A18
A17-A9
A8-A0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Master Reset: BM and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
19
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS1
FFB/IRB HIGH
tENH
CSB
tENS2
W/RB
tENS2
tENS2
tENH
tENH
MBB
tENS2
tENS2
tENH
tENH
ENB
tDH
tDS
B0-B17
4664 drw11
DATA SIZE TABLE FOR WORD WRITES TO FIFO2
SIZE MODE(1)
WRITE
NO.
DATA WRITTEN
TO FIFO2
DATA READ FROM FIFO2
BM
SIZE
BE
B17-B9
B8-B0
A35-A27
A26-A18
A17-A9
A8-A0
1
2
1
2
A
C
C
A
B
D
D
B
H
L
H
A
B
C
D
D
H
L
L
A
B
C
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
CLKB
tENS1
FFB/IRB HIGH
tENH
CSB
tENS2
W/RB
MBB
tENH
tENH
tENS2
tENS2
tENH
tENS2
tENH
ENB
tDS
tDH
B0-B8
4664 drw12
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2
SIZE MODE(1)
WRITE
NO.
DATA WRITTEN
TO FIFO2
DATA READ FROM FIFO2
BM
SIZE
BE
B8-B0
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
H
A
B
C
D
H
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
20
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
EFB/ORB
HIGH
CSB
W/RB
MBB
tENH
tENS2
tENH
tENS2
tENH
tENS2
ENB
t
MDV
No Operation
W2(1)
tDIS
t
A
t
A
t
EN
(1)
W1
B0-B35
Previous Data
(Standard Mode)
t
MDV
tDIS
tA
t
A
OR
tEN
W2(1)
W3(1)
(1)
B0-B35
W1
(FWFT Mode)
4664 drw13
NOTE:
1. Read From FIFO1.
DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1
SIZE MODE(1)
SIZE
DATA WRITTEN TO FIFO1
DATA READ FROM FIFO1
BM
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .
Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKB
HIGH
EFB/ORB
CSB
W/RB
MBB
ENB
t
ENS2
tENH
No Operation
Read 2
t
MDV
t
A
tA
t
DIS
DIS
t
EN
B0-B17
Previous Data
Read 1
Read 2
(Standard Mode)
t
MDV
OR
t
A
tA
t
t
EN
B0-B17
(FWFT Mode)
Read 3
Read 1
4664 drw14
NOTE:
1. Unused word B18-B35 are indeterminate for word-size reads.
DATA SIZE TABLE FOR WORD READS FROM FIFO1
SIZE MODE(1)
SIZE
DATA WRITTEN TO FIFO1
READ NO.
DATA READ FROM FIFO1
BM
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .
Figure 12. Port-B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
21
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
EFB/ORB
HIGH
CSB
W/RB
MBB
tENS2
tENH
ENB
No Operation
t
DIS
DIS
t
MDV
t
A
t
A
t
A
t
A
t
EN
B0-B8
Read 2
Read 1
Previous Data
Read 4
Read 5
Read 3
(Standard Mode)
t
MDV
t
OR
t
A
tA
tA
t
A
t
EN
B0-B8
Read 1
Read 2
Read 3
Read 4
(FWFT Mode)
4664 drw15
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ
FROM FIFO1
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B8-B0
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
H
A
B
C
D
H
L
A
B
C
D
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKL
tCLKH
CLKA
EFA/ORA HIGH
CSA
W/RA
MBA
tENS2
tENS2
tENH
tENH
tENH
tENS2
ENA
No Operation
W2(1)
t
MDV
t
DIS
DIS
t
A
t
A
t
EN
A0-A35
W1(1)
W2(1)
Previous Data
(Standard Mode)
t
MDV
t
tA
t
A
OR
t
EN
A0-A35
(1)
W1
W3(1)
(FWFT Mode)
4664 drw16
NOTE:
1. Read From FIFO2.
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
22
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
IRA
HIGH
tDS
tDH
A0-A35
W1
t
CLKtCLKL
(1)
tCLKH
tSKEW1
CLKB
1
2
3
t
REF
tREF
ORB
FIFO1 Empty
LOW
CSB
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
Old Data in FIFO1 Output Register
W1
B0-B35
4664 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
23
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKA
CSA
LOW
HIGH
W/RA
t
ENS2
t
ENH
ENH
MBA
t
t
ENS2
ENA
FFA
HIGH
tDS
tDH
W1
A0-A35
t
CLK
CLKH
(1)
SKEW1
t
tCLKL
t
CLKB
1
2
t
REF
t
REF
FIFO1 Empty
LOW
EFB
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
tA
W1
B0-B35
4664 drw18
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 16. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
24
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
W/RB
MBB
ENB
tENS2
tENH
tENH
tENS2
IRB
HIGH
tDH
tDS
W1
B0-B35
t
CLK
(1)
tCLKH
t
CLKL
tSKEW1
1
2
CLKA
ORA
3
t
REF
tREF
FIFO2 Empty
CSA
LOW
LOW
LOW
W/RA
MBA
ENA
tENS2
tENH
tA
Old Data in FIFO2 Output Register
W1
A0-A35
4664 drw19
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKB edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
25
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKB
CSB
LOW
LOW
W/RB
t
ENS2
ENS2
tENH
MBB
ENB
t
tENH
HIGH
FFB
tDH
tDS
W1
B0-B35
(1)
t
CLK
tSKEW1
t
CLKH
t
CLKL
1
2
CLKA
t
REF
t
REF
EFA
FIFO2 Empty
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
tA
A0-A35
W1
4664 drw20
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
26
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
W/RB
HIGH
LOW
MBB
tENS2
tENH
tA
ENB
ORB
HIGH
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0-B35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
1
2
CLKA
tWFF
tWFF
FIFO1 Full
IRA
CSA
LOW
W/RA
HIGH
tENH
tENH
tDH
tENS2
tENS2
tDS
MBA
ENA
Write
A0-A35
4664 drw21
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENS2
tENH
tA
ENB
EFB
HIGH
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0-B35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKA
1
2
tWFF
tWFF
FFA
CSA
FIFO1 Full
LOW
W/RA
HIGH
tENS2
tENS2
tENH
tENH
MBA
ENA
tDH
tDS
Write
A0-A35
4664 drw22
To FIFO1
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 20. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
27
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
ORA
HIGH
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0-A35
(1)
tCLK
t
tCLKH
tCLKL
1
2
CLKB
t
WFF
t
WFF
IRB
CSB
FIFO2 FULL
LOW
W/RB
LOW
tENS2
tENH
MBB
ENB
tENS2
tENH
tDS
tDH
Write
B0-B35
4664 drw23
To FIFO2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
28
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0-A35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKB
1
2
t
WFF
t
WFF
FIFO2 Full
LOW
FFB
CSB
W/RB
LOW
tENS2
tENH
MBB
ENB
t
ENS2
t
ENH
tDS
tDH
Write
B0-B35
4664 drw24
To FIFO2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.
Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
29
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
tENS2
tENH
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
t
PAE
AEB X1 Words in FIFO1
(X1+1) Words in FIFO1
ENS2
t
t
ENH
ENB
4664 drw25
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 23. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
CLKB
tENS2
tENH
ENB
(1)
tSKEW2
1
2
CLKA
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
tENH
t
ENA
4664 drw26
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 24. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKA
ENA
tENS2
tENH
t
PAF
t
PAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
ENB
tENS2
tENH
4664 drw27
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644.
4. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 25. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
30
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKB
ENB
tENH
tENS2
t
PAF
t
PAF
(D-Y2) Words in FIFO2
AFB
[D-(Y2+1)] Words in FIFO2
CLKA
ENA
tENS2
tENH
4664 drw28
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644.
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
CLKA
tENS1
t
ENH
ENH
CSA
tENS2
t
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
tDH
tDS
W1
A0-A35
CLKB
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
PMR
tEN
t
MDV
tDIS
B0-B35
W1 (Remains valid in Mail1 Register after read)
4664 drw29
FIFO1 Output Register
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be
indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data
(B9-B35 will be indeterminate).
Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
31
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS1
tENH
CSB
W/RB
MBB
ENB
t
ENS2
t
ENH
tENS2
t
ENH
tENS2
t
t
ENH
DH
tDS
W1
B0-B35
CLKA
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
PMR
tEN
tDIS
t
MDV
A0-A35
W1 (Remains valid in Mail 2 Register after read)
FIFO2 Output Register
4664 drw30
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data
(A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’t care inputs). In this
second case, A0-A8 will have valid data (A9-A35 will be indeterminate).
Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
32
IDT72V3624/72V3634/72V36443.3VCMOSSyncBiFIFOTM WITHBUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330Ω
From Output
Under Test
30 pF (1)
510Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
Input
1.5V
1.5V
GND
GND
3V
t
S
th
tW
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
Input
1.5V
1.5V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
t
PZL
GND
tPLZ
3V
≈ 3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
≈ OV
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
V
t
PHZ
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4664 drw31
NOTE:
1. Includes probe and jig capacitance.
Figure 29. Output Load and AC Test Conditions
33
ORDERING INFORMATION
X
XX
X
X
XXXXXX
X
Device Type Power Speed Package
Process/
Temperature
Range
BLANK
G
Commercial (0°C to +70°C)
Green
PF
Thin Quad Flat Pack (TQFP, PK128-1)
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
72V3624
72V3634
72V3644
256 x 36 x 2 ⎯ 3.3V SyncBiFIFO
™
™
with Bus-Matching
with Bus-Matching
512 x 36 x 2 ⎯ 3.3V SyncBiFIFO
1,024 x 36 x 2 ⎯ 3.3V SyncBiFIFO
™
with Bus-Matching
4664 drw32
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
12/12/2000
03/21/2001
08/01/2001
02/10/2009
pg. 12.
pgs. 6 and 7.
pgs. 6, 8, 9 and 34.
pg. 34.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
34
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