72V3611L15PQF [IDT]
PQFP-132, Tray;
| 型号： | 72V3611L15PQF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PQFP-132, Tray |
| 文件： | 总20页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncFIFOTM
64 x 36
IDT72V3611
• Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
FEATURES:
• 64 x 36 storage capacity
•
•
Industrial temperature range (–40°C to +85°C) is available
Pin and functionally compatible version of the 5V operating
IDT723611
• Supports clock frequencies up to 67MHz
• Fast access times of 10ns
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
•
Green parts available, see ordering information
DESCRIPTION:
• Synchronous data buffering from Port A to Port B
• Mailbox bypass register in each direction
• Programmable Almost-Full (AF) and Almost-Empty (AE) flags
• Microprocessor Interface Control Logic
The IDT72V3611 is a pin and functionally compatible version of the
IDT723611, designed to run off a 3.3V supply for exceptionally low power
consumption. This device is a monolithic, high-speed, low-power, CMOS
• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA Synchronous(clocked)FIFOmemorywhichsupportsclockfrequenciesupto
• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
67MHzandhasreadaccesstimesasfastas10ns.The64 x 36dual-portFIFO
buffers datafromPortAtoPortB.TheFIFOoperates inIDTStandardmode
andhasflagstoindicateemptyandfullconditions,andtwoprogrammableflags,
Almost-Full(AF)andAlmost-Empty(AE),toindicatewhenaselectednumber
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
MBF1
PEFB
Parity
Gen/Check
Mail 1
Register
PGB
RST
Reset
Logic
ODD/
EVEN
RAM
ARRAY
64 x 36
36
36
A
0
- A35
Read
Pointer
Write
Pointer
B0 - B35
FF
AF
Status Flag
JUNE 7 , 2005
EF
AE
Logic
FIFO
Programmable
Flag Offset
Registers
FS
0
1
FS
PGA
Mail 2
Register
Parity
Gen/Check
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
PEFA
MBF2
4657 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
FEBRUARY 2009
COMMERCIAL TEMPERATURE RANGE
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4657/3
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronizedtotheportclockthatwritesdataintoitsarray(CLKA). TheEmpty
Flag(EF)andAlmost-Empty(AE)flagoftheFIFOaretwo-stagesynchronized
totheportclockthatreadsdatafromitsarray.
DESCRIPTION(CONTINUED)
ofwordsisstoredinmemory. Communicationbetweeneachportcantakeplace
throughtwo36-bitmailboxregisters. Eachmailboxregisterhasaflagtosignal
when newmailhasbeenstored. Parityischeckedpassivelyoneachportand
maybeignoredifnotdesired. Paritygenerationcanbeselectedfordataread
fromeachport. Twoormoredevices maybeusedinparalleltocreatewider
datapaths.
The IDT72V3611 is a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface. Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
TheIDT72V3611ischaracterizedforoperationfrom0°Cto70°C. Industrial
temperaturerange(–40°Cto+85°C)isavailablebyspecialorder. Thisdevice
isfabricatedusingIDT'shighspeed,submicronCMOStechnology.
PIN CONFIGURATION
A
A
A
23
22
21
1
B
22
21
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
B
3
GND
GND
4
B
B
B
B
B
B
B
B
B
B
B
20
19
18
17
16
15
14
13
12
11
10
A
A
A
A
A
A
A
A
A
A
A
20
19
18
17
16
15
14
13
12
11
10
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
B
B
B
V
B
B
B
B
9
8
7
A
A
A
9
8
7
CC
6
VCC
A
A
A
A
6
5
4
3
5
4
3
GND
GND
B
B
B
EF
AE
NC
2
1
0
A
A
A
2
1
0
NC
NC
4657 drw 02
NOTES:
1. Pin 1 identifier in corner.
2. NC = No internal connection
TQFP (PN120-1, order code: PF)
TOP VIEW
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FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION(CONTINUED)
GND
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AE
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
EF
A
A
A
0
1
2
B
B
B
0
1
2
GND
GND
A
A
A
A
3
4
5
6
B
B
B
B
V
B
B
B
3
4
5
6
CC
7
8
V
CC
A
A
A
7
8
9
9
GND
GND
A
10
11
B
B
V
B
B
B
10
11
CC
12
13
14
A
V
CC
98
A
12
13
14
97
A
96
A
GND
95
GND
94
A
A
A
A
A
A
15
16
17
18
19
20
B
B
B
B
B
B
15
16
17
18
19
20
93
92
91
90
89
88
GND
GND
87
A21
A22
A23
B21
B22
B23
86
85
84
4657 drw 03
NOTES:
1. Electrical pin 1 in center of beveled edge.
2. NC = No internal connection
PQFP (PQ132-1, order code: PQF)
TOP VIEW
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FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
36-bitbidirectionaldataportforsideA.
Port-AData
Almost-EmptyFlag
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB. ItisLOWwhenthenumberofwords
in the FIFO is less than or equal to the value in the offset register, X.
AF
Almost-FullFlag
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA. ItisLOWwhenthenumberofempty
locations intheFIFOis less thanorequaltothevalueintheOffsetregister,X.
B0-B35
CLKA
Port-BData.
Port-A Clock
I/O
I
36-bitbidirectionaldataportforsideB.
CLKAisacontinuousclockthatsynchronizesalldatatransfersthroughport-Aandcanbe
asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKB
Port-BClock
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughport-Bandcanbe
asynchronous or coincident to CLKA. EF and AE are synchronized totheLOW-to-HIGH
transitionofCLKB.
CSA
CSB
EF
Port-AChipSelect
Port-BChipSelect
EmptyFlag
I
I
CSA mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onport-A.
The A0-A35outputs are inthe high-impedance state whenCSA is HIGH.
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onport-B.
The B0-B35outputs are inthe high-impedance state whenCSB is HIGH.
EF is synchronizedtotheLOW-to-HIGHtransitionofCLKB. WhenEFis LOW,theFIFOis empty,
andreads fromits memoryare disabled. Data canbe readfromthe FIFOtoits outputregister
when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGHtransitionofCLKBafterdataisloadedintoemptyFIFOmemory.
O
ENA
ENB
FF
Port-AEnable
Port-BEnable
Full Flag
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onport-A.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onport-B.
O
FFis synchronizedtothe LOW-to-HIGHtransitionofCLKA. WhenFFis LOW, the FIFOis full, and
writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by
thesecondLOW-to-HIGHtransitionofCLKAafterreset.
FS1, FS0
Flag-OffsetSelects
I
The LOW-to-HIGHtransitionof RST latches the values ofFS0andFS1, whichloads one offour
presetvaluesintotheAlmost-FullandAlmost-EmptyOffsetregister(X).
MBA
MBB
Port-AMailboxSelect
Port-BMailboxSelect
I
I
A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35outputsareactive,aHIGHlevelonMBBselectsdatafromthemail1registerforoutput,
andaLOWlevelselectstheFIFOoutputregisterdataforoutput.
MBF1
MBF2
Mail1RegisterFlag
Mail2RegisterFlag
O
O
MBF1issetLOWbyaLOW-to-HIGHtransitionofCLKAthatwritesdatatothemail1register.Writes
tothe mail1registerare inhibitedwhile MBF1 is setLOW. MBF1 is setHIGHbya LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when the
deviceisreset.
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.Writes
tothe mail2registerare inhibitedwhile MBF2 is LOW. MBF2 is setHIGHbya LOW-to-HIGH
transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH when the
deviceisreset.
ODD/
EVEN
Odd/EvenParity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVEN alsoselects thetypeofparitygeneratedforeachportifparity
generation is enabled for a read operation.
PEFA
Port-A Parity Error
Flag
O
Whenanybyte appliedtoterminals A0-A35fails parity, PEFA is LOW. Bytes are organizedas
[PortA) A0-A8,A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyteservingas the
paritybit. The type ofparitycheckedis determinedbythe state ofthe ODD/EVEN input. The
paritytrees usedtocheckthe A0-A35inputs are sharedbythe mail2registertogenerate parityif
parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by
having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced
HIGHregardlessofthestateofA0-A35inputs.
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FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/O
Description
Whenanybyte appliedtoterminals B0-B35fails parity, PEFB is LOW. Bytes are organizedas
PEFB
Port-B Parity Error
Flag
O
(Port B) B0-B8,B9-B17,B18-B26,B27-B35,withthemostsignificantbitofeachbyteservingas theparity
bit. The type ofparitycheckedis determinedbythe state ofthe ODD/EVEN input. The parity
trees usedtocheckthe B0-B35inputs are sharedbythe mail1registertogenerate parityifparity
generationis selectedbyPGB. Therefore, ifa mail1readwithparitygenerationis setupby
having CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced
HIGHregardlessofthestateoftheB0-B35inputs
PGA
PGB
RST
Port-AParity
Generation
I
I
I
Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity
generatedis selectedbythestateoftheODD/EVEN input.Bytes areorganizedas A0-A8,
A9-A17,A18-A26,andA27-A35.Thegeneratedparitybitsareoutputinthemostsignificantbit
ofeachbyte.
Port-BParity
Generation
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated
is selectedbythe state ofthe ODD/EVEN input. Bytes are organizedas B0-B8, B9-B17,
B18-B26, and B27-B35. The generated paritybitsareoutputinthemostsignificantbitof
eachbyte.
Reset
Toresetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsof
CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the
EF,AE,andFF flags LOW. TheLOW-to-HIGHtransitionofRSTlatches thestatus oftheFS1
andFS0inputstoselectAlmost-FullandAlmost-Emptyflagoffset.
W/RA
W/RB
Port-AWrite/Read
Select
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a
LOW-to-HIGHtransitionofCLKA. TheA0-A35outputsareinthehigh-impedancestate
when W/RA is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on port B for a
LOW-to-HIGHtransitionofCLKB. TheB0-B35outputsareinthehigh-impedancestate
when W/RB is HIGH.
Port-BWrite/Read
Select
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FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
InputVoltageRange
OutputVoltageRange
(2)
VI
V
(2)
VO
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO = < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±500
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at
these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ.
Max.
3.6
Unit
V
VCC SupplyVoltage
3.0
2
3.3
—
—
—
—
—
VIH
VIL
IOH
IOL
TA
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
VCC+0.5
0.8
V
—
—
—
0
V
–4
mA
mA
°C
8
OperatingFree-Air
Temperature
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3611
Commercial
tCLK = 15, 20 ns
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
Test Conditions
IOH = –4 mA
IOL = 8 mA
Min. Typ.(1) Max. Unit
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
2.4
—
—
—
—
—
—
—
—
—
—
—
4
—
0.5
±5
V
V
OutputLogic"0"Voltage
Input Leakage Current (Any Input)
OutputLeakageCurrent
StandbyCurrent
ILI
VI = VCC or 0
VO = VCC or 0
µA
µA
µA
pF
pF
ILO
ICC(2)
±5
VI = VCC - 0.2V or 0
500
—
CIN
InputCapacitance
f = 1 MHz
f = 1 MHZ
COUT
OutputCapacitance
VO = 0,
8
—
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
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FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
TheICC(f)dataforthegraphwastakenwhilesimultaneouslyreadingandwritingtheFIFOontheIDT72V3611withCLKAandCLKBoperatingatfrequency
fS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnectedtonormalize
thegraphtoazero-capacitanceload. Oncethecapacitanceloadperdata-outputchannelisknown,thepowerdissipationcanbecalculatedwiththeequation
below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3611 may be calculated by:
PT = VCC x ICC(f) + Σ(CL x (VOH - VOL)2 x fO)
N
where:
N
=
=
=
=
=
number of outputs = 36
output capacitance load
switching frequency of an output
output high-level voltage
output low-level voltage
CL
fO
VOH
VOL
When no read or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculatedby:
PT = VCC x fS x 0.025 mA/MHz
150
fdata = 1/2 fS
125
100
75
T
A
= 25 C
C
L = 0 pF
VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
50
25
0
0
10
20
30
40
50
60
70
4657 drw 04
fS
⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURES
IDT72V3611L15
IDT72V3611L20
Symbol
Parameter
Min.
–
Max.
Min.
–
Max.
Unit
Mhz
Mhz
ns
fS
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKAorCLKBLOW
66.7
–
50
–
tCLK
tCLKH
tCLKL
tDS
15
6
20
8
–
–
6
–
8
–
ns
SetupTime, A0-A35before CLKA↑andB0-B35
beforeCLKB↑
4
–
5
–
ns
tENS1
tENS2
tENS3
tPGS
CSA,W/RA,beforeCLKA↑;CSB,W/RBbeforeCLKB↑
ENAbeforeCLKA↑;ENBbeforeCLKB↑
6
4
4
4
5
5
1
1
1
1
0
6
4
8
–
–
–
–
–
–
–
–
6
5
5
5
6
6
1
1
1
1
0
6
4
8
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MBAbeforeCLKA↑;ENBbeforeCLKB↑
(1)
SetupTime,ODD/EVENandPGBbeforeCLKB↑
(2)
tRSTS
tFSS
SetupTime, RSTLOWbeforeCLKA↑orCLKB↑
Setup Time, FS0 and FS1 before RST HIGH
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
CSA,W/RAafterCLKA↑;CSB,W/RBafterCLKB↑
ENAafterCLKA↑;ENBafterCLKB↑
tDH
tENH1
tENH2
tENH3
tPGH
MBAafterCLKA↑;MBBafterCLKB↑
(1)
HoldTime,ODD/EVENandPGBafterCLKB↑
–
–
–
–
–
–
–
–
(2)
tRSTH
tFSH
HoldTime, RST LOWafterCLKA↑orCLKB↑
Hold Time, FS0 and FS1 after RST HIGH
tSKEW1(3)
SkewTime,betweenCLKA↑andCLKB↑
for EF, FF
tSKEW2(3,4)
SkewTime,betweenCLKA↑andCLKB↑
for AE, AF
14
–
16
–
ns
NOTES:
1. Only applies for a rising edge of CLKB that does a FIFO read.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
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FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
IDT72V3611L15
IDT72V3611L20
Symbol
fS
Parameter
Min.
–
Max.
Min.
–
Max.
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
AccessTime,CLKB↑toB0-B35
66.7
10
10
10
10
10
9
50
12
12
12
12
12
12
tA
2
2
tWFF
tREF
tPAE
tPAF
tPMF
PropagationDelayTime, CLKA↑toFF
PropagationDelayTime, CLKB↑toEF
PropagationDelayTime,CLKB↑toAE
PropagationDelayTime, CLKA↑toAF
2
2
ns
2
2
ns
2
2
ns
2
2
ns
PropagationDelayTime, CLKA↑toMBF1 LOWor
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
1
1
ns
tPMR
PropagationDelayTime,CLKA↑toB0-B35(1)
2
10
3
12
ns
andCLKB↑toA0-A35(2)
tMDV
PropagationDelayTime, MBBtoB0-B35Valid
1
2
10
10
1
2
11.5
11
ns
ns
tPDPE
PropagationDelayTime, A0-A35ValidtoPEFA
Valid;B0-B35ValidtoPEFBValid
tPOPE
PropagationDelayTime, ODD/EVEN toPEFA
and PEFB
2
2
1
10
10
10
2
2
1
12
12
12
ns
ns
ns
(3)
tPOPB
PropagationDelayTime,ODD/EVENtoParity
Bits (A8, A17, A26, A35) and (B8, B17, B26, B35)
tPEPE
PropagationDelayTime,CSA, ENA, W/RA,
MBA, or PGA to PEFA; CSB, ENB, W/RB,
MBB, or PGB to PEFB
(3)
tPEPB
Propagation Delay Time, CSA, ENA W/RA,
MBA, or PGA to Parity Bits (A8, A17, A26,
A35); CSB, ENB, W/RB, MBB, or PGB to Parity
Bits (B8, B17, B26, B35)
2
10
2
12
ns
tRSF
tEN
tDIS
Propagation Delay Time, RST to AE LOW and
(AF, MBF1, MBF2) HIGH
1
2
1
15
10
9
1
2
1
20
12
10
ns
ns
ns
EnableTime,CSAandW/RALOWtoA0-A35Active
and CSB LOW and W/RB HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35
at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when reading data from a mail register.
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(FS0, FS1) inputs. The values that can be loaded into the register are shown
in Table 1. For the relevant Reset timing and preset value loading timing
diagram,seeFigure2. TherelevantWritetimingdiagramforPortAcanbefound
in Figure 3.
SIGNALDESCRIPTION
RESET ( RST )
The IDT72V3611 is reset by taking the Reset (RST) input LOW for at
least four port-A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH
transitions. Theresetinputcanswitchasynchronouslytotheclocks. Adevice
resetinitializestheinternalreadandwritepointersoftheFIFOandforcesthe
FullFlag(FF)LOW,theEmptyFlag(EF)LOW,theAlmost-Emptyflag(AE)LOW,
and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags
(MBF1, MBF2)HIGH. Aftera reset, FF is setHIGHaftertwoLOW-to-HIGH
transitions ofCLKA. The device mustbe resetafterpowerupbefore data is
writtentoitsmemory.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-
AChipSelect(CSA)andtheport-AWrite/Readselect(W/RA). TheA0-A35
outputs are inthe high-impedance state wheneitherCSA orW/RAis HIGH.
The A0-A35 outputs are active when both CSA and W/RA are LOW. Data
isloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGHtransition
ofCLKAwhenCSAisLOW,W/RAisHIGH,ENAisHIGH,MBAisLOW,and
FF is HIGH (see Table 2).
The port-B control signals are identical to those of port A. The state of
the port-B data (B0-B35) outputs is controlled by the port-B Chip Select
(CSB)andtheport-BWrite/Readselect(W/RB). TheB0-B35outputs arein
the high-impedance state when either CSB or W/RB is HIGH. The B0-B35
outputsareactivewhenbothCSBandW/RBareLOW. Dataisreadfromthe
FIFOtotheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKBwhenCSB
isLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,andEFisHIGH(seeTable
3). The relevant Read timing diagram for Port B can be found in Figure 4.
The setup and hold-time constraints to the port clocks for the port Chip
Selects(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenabling
write and read operations and are not related to HIGH-impedance control of
the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip
SelectandWrite/Readselectcanchangestatesduringthesetupandhold-time
window of the cycle.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the value selected by the Flag Select
TABLE 1 – FLAG PROGRAMMING
Almost-Full and
Almost-Empty Flag
Offset Register (X)
FS1
FS0
RST
16
12
8
H
H
L
L
H
L
H
L
↑
↑
↑
↑
4
TABLE 2 – PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
X
Data A (A0-A35) I/O
Port Functions
Input
Input
None
H
L
X
X
None
L
H
H
L
↑
Input
FIFOWrite
L
H
H
H
↑
Input
Mail1Write
L
L
L
L
X
Output
Output
Output
Output
None
L
L
H
L
↑
None
None
L
L
L
H
X
L
L
H
H
↑
Mail2 Read (set MBF2 HIGH)
TABLE 3 – PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
X
Data B (B0-B35) I/O
Port Functions
Input
Input
None
H
L
X
X
None
L
H
H
L
↑
Input
None
Mail2Write
L
H
H
H
↑
Input
L
L
L
L
X
Output
Output
Output
Output
None
L
L
H
L
↑
FIFO Read
L
L
L
H
X
None
L
L
H
H
↑
Mail1 Read (set MBF1 HIGH)
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SYNCHRONIZED FIFO FLAGS
ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchronizationcycle
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages. ofareadiftheclocktransitionoccursattimetSKEW1orgreateraftertheread.
This is done to improve the flags’ reliability by reducing the probability of Otherwise,thesubsequentclockcyclecanbethefirstsynchronizationcycle(see
metastableeventsontheiroutputswhenCLKAandCLKBoperateasynchro- Figure 6).
nouslytooneanother. FFandAFaresynchronizedtoCLKA. EFandAEare
synchronizedtoCLKB. Table4showstherelationshiptotheflagstotheFIFO. ALMOST-EMPTY FLAG (AE)
TheFIFOAlmost-Emptyflagissynchronizedtotheportclockthatreads
EMPTY FLAG ( EF )
datafromitsarray(CLKB). ThestatemachinethatcontrolstheAEflagmonitors
TheFIFOEmptyFlagis synchronizedtotheportclockthatreads datafrom a write pointer and read pointer comparator that indicates when the FIFO
itsarray(CLKB). WhentheEFisHIGH,newdatacanbereadtotheFIFOoutput memorystatus is almost-empty, almost-empty+1, oralmost-empty+2. The
register. When the EF is LOW, the FIFO is empty and attempted FIFO reads almost-emptystateisdefinedbythevalueoftheAlmost-FullandAlmost-Empty
are ignored.
Offsetregister(X). Thisregisterisloadedwithoneoffourpresetvaluesduring
The FIFO read pointer is incremented each time a new word is clocked a device reset (see the Reset section). The AE flag is LOW when the FIFO
toits outputregister. Thestatemachinethatcontrols anEFmonitorsawrite containsXorlesswordsinmemoryandisHIGHwhentheFIFOcontains(X+1)
pointer and read pointer comparator that indicates when the FIFO memory or more words.
statusisempty,empty+1,orempty+2. AwordwrittentotheFIFOcanberead
Two LOW-to-HIGH transitions on the port-B clock (CLKB) are required
totheFIFOoutputregisterinaminimumofthreeport-Bclock(CLKB)cycles. after a FIFO write for the AE flag to reflect the new level of fill. Therefore, the
Therefore,anEFisLOWifawordinmemoryisthenextdatatobesenttothe AE flag of a FIFO containing (X+1) or more words remains LOW if two CLKB
FIFOoutputregisterandtwoCLKBcycleshavenotelapsedsincethetimethe cycleshavenotelapsedsincethewritethatfilledthememorytothe(X+1)level.
wordwaswritten. TheEFoftheFIFOissetHIGHbythesecondLOW-to-HIGH TheAEflagissetHIGHbythesecondCLKBLOW-to-HIGHtransitionafterthe
transition of CLKB, and the new data word can be read to the FIFO output FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition on
registerinthefollowingcycle.
CLKBbeginsthefirstsynchronizationcycleifitoccursattimetSKEW2orgreater
A LOW-to-HIGH transition on CLKB begins the first synchronized cycle of afterthewritethatfillstheFIFOto(X+1)words. Otherwise,thesubsequentCLKB
a write if the clock transition occurs at time tSKEW1 or greater after the write. cycle can be the first synchronization cycle (see Figure 7).
Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 5).
ALMOST-FULL FLAG ( AF )
The FIFO Almost-Full flag is synchronized to the port clock that writes
datatoitsarray(CLKA). ThestatemachinethatcontrolsanAFflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memorystatusisalmost-full,almost-full-1,oralmost-full-2. Thealmost-fullstate
isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).
Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset(see
theResetsection). TheAFflagisLOWwhentheFIFOcontains(64-X)ormore
wordsinmemoryandisHIGHwhentheFIFOcontains[64-(X+1)]orlesswords.
Two LOW-to-HIGH transitions on the port-A clock (CLKA) are required
aftera FIFOreadforthe AF flagtoreflectthe newleveloffill. Therefore, the
AFflagofaFIFOcontaining[64-(X+1)]orlesswordsremainsLOWiftwoCLKA
cycles have notelapsedsince the readthatreducedthe numberofwords in
memoryto[64-(X+1)]. TheAFflagissetHIGHbythesecondCLKALOW-to-
HIGHtransitionaftertheFIFOreadthatreducesthenumberofwordsinmemory
to[64-(X+1)]. ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchroni-
zationcycleifitoccursattimetSKEW2orgreaterafterthereadthatreducesthe
numberofwordsinmemoryto[64-(X+1)]. Otherwise,thesubsequentCLKA
cycle canbe the firstsynchronizationcycle (see Figure 8).
FULL FLAG ( FF )
TheFIFOFullFlagissynchronizedtotheportclockthatwritesdatatoits
array(CLKA). WhentheFFisHIGH,aFIFOmemorylocationisfreetoreceive
newdata. NomemorylocationsarefreewhentheFFisLOWandattempted
writes to the FIFO are ignored.
EachtimeawordiswrittentotheFIFO,itswritepointerisincremented. The
state machine thatcontrols the FF monitors a write pointerandreadpointer
comparatorthatindicateswhentheFIFOmemorystatusisfull,full-1,orfull-2.
From the time a wordis readfromthe FIFO, its previous memorylocationis
readytobewritteninaminimumofthreeport-Aclockcycles. Therefore,aFF
isLOWiflessthantwoCLKAcycleshaveelapsedsincethenextmemorywrite
locationhasbeenread. ThesecondLOW-to-HIGHtransitiononCLKAafter
thereadsetstheFFHIGHanddatacanbewritteninthefollowingclockcycle.
TABLE 4 – FIFO FLAG OPERATION
MAILBOX REGISTERS
Synchronized
Synchronized
Two36-bitbypassregistersareontheIDT72V3611topasscommandand
controlinformationbetweenportAandportB. TheMailboxselect(MBA,MBB)
inputs choose between a mail register and a FIFO for a port data transfer
operation. ALOW-to-HIGHtransitiononCLKAwritesA0-A35datatothemail1
registerwhenport-AwriteisselectedbyCSA,W/RA,andENAwithMBAHIGH.
ALOW-to-HIGHtransitiononCLKBwritesB0-B35datatothemail2register
whenport-BwriteisselectedbyCSB,W/RB,andENBwithMBBHIGH. Writing
data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW.
AttemptedwritestoamailregisterareignoredwhileitsmailflagisLOW.
When the port-B data (B0-B35) outputs are active, the data on the bus
comesfromtheFIFOoutputregisterwhentheport-BMailboxselect(MBB)input
isLOWandfromthemail1registerwhenMBBisHIGH. Mail2dataisalways
Number of Words
in the FIFO
0
to CLKB
to CLKA
EF
L
AE
L
AF
H
H
H
L
FF
H
H
H
H
L
1 to X
H
H
H
H
L
(X+1) to [64-(X+1)]
(64-X) to 63
64
H
H
H
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag register.
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presentontheport-Adata(A0-A35)outputswhentheyareactive. TheMail1 HIGH, and PGB HIGH, the port-B Parity Error Flag (PEFB) is held HIGH
RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhen regardlessofthelevelsappliedtotheB0-B35inputs.
aport-BreadisselectedbyCSB,W/RB,andENBwithMBBHIGH. TheMail2
RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhen PARITYGENERATION
aport-AreadisselectedbyCSA,W/RA,andENAwithMBAHIGH. Thedata
AHIGHlevelontheport-AParityGenerateselect(PGA)orport-BParity
inamailregisterremainsintactafteritisreadandchangesonlywhennewdata Generate select (PGB) enables the IDT72V3611 to generate parity bits for
iswrittentotheregister. Forrelevantmailregisterandmailregisterflagtiming portreadsfromaFIFOormailboxregister. Port-AbytesarearrangedasA0-
diagrams, see Figure 9 and Figure 10.
A8,A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyte
usedastheparitybit. Port-BbytesarearrangedasB0-B8,B9-B17,B18-B26,
andB27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. A
PARITY CHECKING
The port-A (A0-A35) inputs and port-B (B0-B35) inputs each have four writetoaFIFOormailregisterstores thelevels appliedtoallthirty-sixinputs
paritytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs. When
onone ormore bytes ofthe inputbus is reportedbya LOWlevelonthe port dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
ParityErrorFlag(PEFA,PEFB). Oddorevenparitycheckingcanbeselected, eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
and the Parity Error Flags can be ignored if this feature is not desired.
EVENselect. Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/ writtentothemostsignificantbitsofeachbyteasthewordisreadtothedata
Even parity (ODD/EVEN) select input. A parity error on one or more bytes outputs.
ofaportisreportedbyaLOWlevelonthecorrespondingportParityErrorFlag
ParitybitsforFIFOdataaregeneratedafterthedataisreadfromtheFIFO
(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18- RAMandbeforethedataiswrittentotheoutputregister. Therefore,theport-
A26, and A27-A35, and port-B bytes are arranged as B0-B8, B9-B17, B18- B Parity Generate select (PGB) and ODD/EVEN have setup and hold time
B26,andB27-B35. WhenOdd/Evenparityisselected,aportParityErrorFlag constraintstotheport-Bclock(CLKB)forarisingedgeofCLKBusedtoread
(PEFA,PEFB)isLOWifanybyteontheporthasanodd/evennumberofLOW a new word to the FIFO output register.
levelsappliedtoitsbits.
Thecircuitusedtogenerateparityforthemail1dataissharedbytheport-
The fourparitytrees usedtocheckthe A0-A35inputs are sharedbythe Bbus (B0-B35)tocheckparityandthe circuitusedtogenerate parityforthe
mail2 register when parity generation is selected for port-A reads mail2datais sharedbytheport-Abus (A0-A35)tocheckparity. Theshared
(PGA=HIGH). Whenport-Areadfromthemail2registerwithparitygeneration paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA whentheportWrite/Readselect(W/RA,W/RB)inputisLOW,theportMailselect
HIGH,theport-AParityErrorFlag(PEFA)isheldHIGHregardlessofthelevels (MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA,
appliedtotheA0-A35inputs. Likewise,theparitytreesusedtochecktheB0- ENB) is HIGH, and the port Parity Generate select (PGA, PGB) is HIGH.
B35inputsaresharedbythemail1registerwhenparitygenerationisselected Generating parity for mail register data does not change the contents of the
forport-Breads(PGB=HIGH). Whenaport-Breadfromthemail1registerwith register (see Figure 13 and Figure 14).
paritygenerationis selectedwithCSB LOW, ENBHIGH, W/RBLOW, MBB
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CLKA
CLKB
t
RSTH
t
RSTS
t
FSH
t
FSS
RST
FS1,FS0
0,1
t
WFF
t
WFF
FF
t
REF
EF
AE
AF
t
PAE
t
PAF
t
RSF
MBF1,
MBF2
4657 drw 05
Figure 2. Device Reset and Loading the X Register with the Value of Eight
tCLK
tCLKL
tCLKH
CLKA
FF
HIGH
tENS1
tENH1
CSA
t
ENS1
t
ENH1
ENH3
ENH2
W/RA
t
t
ENS3
MBA
tENS2
t
t
ENS2
tENH2
tENS2
tENH2
ENA
tDH
tDS
W1
No Operation
W2
A0 - A35
ODD/
EVEN
tPDPE
tPDPE
Valid
Valid
PEFA
4657 drw 06
Figure 3. FIFO Write Cycle Timing
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FEBRUARY10,2009
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tCLK
tCLKH
tCLKL
CLKB
EF
HIGH
CSB
W/RB
tENS2
MBB
ENB
tENS2
tENH2
tENH2
tENH2
tENS2
No Operation
Word 2
t
MDV
tDIS
t
A
tA
tEN
Word 1
Previous Data
B0 - B35
tPGH
tPGH
tPGS
tPGS
PGB,
ODD/
EVEN
4657 drw 07
Figure 4. FIFO Read Cycle Timing
t
CLK
t
CLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS3
tENH3
MBA
tENH2
tENS2
ENA
FFA
HIGH
tDS
tDH
W1
A0 - A35
(1)
t
CLK
tSKEW1
t
CLKL
t
CLKH
1
2
CLKB
t
REF
tREF
Empty FIFO
EF
CSB
LOW
LOW
LOW
W/RB
MBB
tENS2
tENH2
ENB
tA
W1
B0 - B35
4657 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Figure 5. EF Flag Timing and First Data Read when the FIFO is Empty
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COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
LOW
W/RB
MBB
tENS2
tENH2
ENB
EFB
HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0 -B35
(1)
t
CLKH CLK tCLKL
tSKEW1
t
1
2
CLKA
t
WFF
t
WFF
FIFO Full
FF
LOW
CSA
WRA HIGH
tENS3
tENH3
MBA
tENS2
tENH2
ENA
tDS
tDH
A0 - A35
4657 drw 09
To FIFO
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Figure 6. FF Flag Timing and First Available Write when the FIFO is Full
CLKA
tENH2
tENS2
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
tPAE
X Word in FIFO
AE
(X+1) Words in FIFO
ENS2
t
tENH2
ENB
4657 drw 10
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 7. Timing for AE when the FIFO is Almost-Empty
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COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKA
tENS2
tENH2
ENA
AF
t
PAF
t
PAF
(64-X) Words in FIFO
[64-(X+1)] Words in FIFO
CLKB
tENH2
tENS2
ENB
4657 drw 11
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 8. Timing for AF when the FIFO is Almost-Full
CLKA
tENS1
t
ENH1
ENH1
CSA
W/RA
t
ENS1
t
t
ENS1
tENH1
MBA
tENS1
tENH1
ENA
tDH
tDS
W1
A0 - A35
CLKB
t
PMF
tPMF
MBF1
CSB
W/RB
MBB
ENB
tENH2
tENS2
tEN
tPMR
t
MDV
tDIS
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4657 drw 12
NOTE:
1. Port-B parity generation off (PGB = L)
Figure 9. Timing for Mail1 Register and MBF1 Flag
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FEBRUARY10,2009
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CLKB
t
ENS1
t
ENH1
ENH1
CSB
W/RB
MBB
t
ENS1
t
t
ENS1
tENH1
tENS1
tENH1
ENB
tDH
tDS
B0 - B35
W1
CLKA
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH2
tENS2
tEN
t
PMR
tDIS
W1 (Remains valid in Mail2 Register after read)
A0 - A35
4657 drw 13
NOTE:
1. Port-A parity generation off (PGA = L)
Figure 10. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
t
PEPE
tPOPE
tPEPE
tPOPE
PEFA
Valid
Valid
Valid
Valid
4657 drw 14
NOTE:
1. CSA = L and ENA = H.
Figure 11. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
ODD/
EVEN
W/RB
MBB
PGB
t
PEPE
t
PEPE
tPOPE
tPOPE
PEFB
Valid
Valid
Valid
Valid
4657 drw 15
NOTE:
1. CSB = L and ENB = H.
Figure 12. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing
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ODD/
EVEN
LOW
CSA
W/RA
MBA
PGA
tEN
t
PEPB
tPOPB
tPEPB
A8, A17,
A26, A35
Generated Parity
Mail2 Data
Generated Parity
Mail2 Data
4657 drw 16
NOTE:
1. ENA = H.
Figure 13. Parity Generation Timing when reading from the Mail2 Register
ODD/
EVEN
LOW
CSB
W/RB
MBB
PGB
t
PEPB
t
MDV
tEN
tPOPB
tPEPB
B8, B17,
B26, B35
Generated Parity
Mail1 Data
Generated Parity
4657 drw 17
Mail1
Data
NOTE:
1. ENB = H.
Figure 14. Parity Generation Timing when reading from the Mail1 Register
18
FEBRUARY10,2009
IDT72V36113.3V,CMOSSyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330Ω
From Output
Under Test
30 pF (1)
510Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
GND
1.5 V
GND
tS
th
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
¯
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
¯
OL
OV
4657 drw 18
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTE:
1. Includes probe and jig capacitance.
Figure 15. Load Circuit and Voltage Waveforms
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FEBRUARY10,2009
ORDERING INFORMATION
X
X
XX
X
X
XXXXXX
Process/
Temperature
Range
Device Type Power
Speed
Package
Commercial (0°C to +70°C)
BLANK
Green
G
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Clock Cycle Time (tCLK
Commercial Only
)
15
20
Speed in Nanoseconds
Low Power
L
64 x 36 ⎯ 3.3V SyncFIFO
72V3611
4657 drw 19
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
07/10/2000
05/27/2003
06/07/2005
02/10/2009
pg. 1
pg. 6.
pgs. 1, 2, 3 and 20.
pg. 20.
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800-345-7015 or 408-284-8200
fax: 408-284-2775
for TECH SUPPORT:
408-360-1753
FIFOhelp@idt.com
www.idt.com
20
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