72V275L20PFGI8 [IDT]
3.3 VOLT CMOS SuperSync FIFO;
| 型号： | 72V275L20PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS SuperSync FIFO 先进先出芯片 |
| 文件： | 总25页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SuperSync FIFO™
32,768 x 18
65,536 x 18
IDT72V275
IDT72V285
Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:
•
IDT72V275
IDT72V285
32,768 x 18
65,536 x 18
• Green parts are available, see ordering information
• Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
DESCRIPTION:
The IDT72V275/72V285 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheother
has been removed. The Frequency Select pin (FS) has been removed,
thusitisnolongernecessarytoselectwhichofthetwoclockinputs,RCLK
or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento
an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period
found on previous SuperSync devices has been eliminated on this
SuperSyncfamily.)
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
•
Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-
munications,datacommunicationsandotherapplicationsthatneedtobuffer
largeamountsofdata.
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
FUNCTIONAL BLOCK DIAGRAM
D0 -D17
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
32,768 x 18
65,536 x 18
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
4512 drw 01
Q0 -Q17
OE
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER2014
1
DSC-4512/4
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
DESCRIPTION (Continued)
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input
and Read Enable (REN) input. Data is read from the FIFO on every rising
edgeofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovided
forthree-statecontroloftheoutputs.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Q17
Q16
GND
Q15
Q14
WEN
SEN
DC(1)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
VCC
5
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
VCC
6
Q13
Q12
Q11
GND
Q10
Q9
7
8
9
10
11
12
13
14
15
16
Q8
Q7
Q6
D8
GND
D7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D
6
4512 drw 02
TQFP (PN64, order code: PF)
STQFP (PP64, order code: TF)
TOP VIEW
NOTE:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
anddefaultoffsetsselected.
ThePartialReset(PRS)alsosetsthereadandwritepointerstothefirst
locationofthememory. However,thetimingmode,partialflagprogramming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand
offsetsineffect. PRSisusefulforresettingadeviceinmid-operation,when
reprogrammingpartialflagswouldbeundesirable.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operationbysettingthereadpointertothefirstlocationofthememoryarray.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
TheIDT72V275/72V285arefabricatedusingIDT’shighspeedsubmicron
CMOStechnology.
DESCRIPTION (Continued)
TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),
FF/IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFand
FFfunctionsareselectedinIDTStandardmode. TheIRandORfunctions
are selected in FWFT mode. HF, PAE and PAF are always available for
use,irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypoint
inmemory. (SeeTable1andTable2.) Programmableoffsetsdeterminethe
flagswitchingthresholdandcanbeloadedbytwomethods:parallelorserial.
Twodefaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitch
at127or1,023locationsfromtheemptyboundaryandthePAFthresholdcan
besetat127or1,023locationsfromthefullboundary. Thesechoicesaremade
withtheLDpinduringMasterReset.
For serial programming, SENtogether with LDon each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72V275
72V285
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF-FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4512 drw 03
Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO
3
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
I/O
Description
Data Inputs
I
I
Data inputs for a 18-bit bus.
Master Reset
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
Write Clock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN
OE
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN
LD
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023
and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master
Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
Output Ready
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
Programmable
Almost-Full Flag
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
PAE
Programmable
Almost-Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF
Half-Full Flag
Data Outputs
Power
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
Q0–Q17
VCC
+3.3 Volt power supply pins.
GND
Ground
Ground pins.
4
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDDCOPERATING
Symbol
Rating
Commercial
Unit
CONDITIONS
VTERM
TerminalVoltage
–0.5to+4.6
V
Symbol
Parameter
Min.
Typ.
Max.
Unit
with respect to GND
VCC
Supply Voltage(Com’l & Ind’l)
Supply Voltage(Com’l & Ind’l)
3.0
3.3
3.6
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50 to +50
°C
GND
VIH
0
0
0
V
InputHighVoltage
(Com’l & Ind’l)
DC Output Current
mA
2.0
—
VCC + 0.5
V
(1)
NOTE:
VIL
InputLowVoltage
(Com’l & Ind’l)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
—
0
—
—
0.8
70
V
oC
TA
OperatingTemperature
Commercial
TA
OperatingTemperature
Industrial
-40
⎯
85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0oC to +70oC; Industrial: VCC = 3.3V 0.3V, TA = -40°C to +85°C)
IDT72V275L
IDT72V285L
Com’’l & Ind’l
(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
1
μA
μA
V
(3)
ILO
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
60
20
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for the 15ns is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 11 + 1.65*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25oC, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL
= capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25oC, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0oC to +70oC; Industrial: VCC = 3.3V 3.3V, TA = -40°C to + 85°C)
Commercial
Com’l & Ind’l (2)
Commercial
IDT72V275L10
IDT72V275L15
IDT72V275L20
IDT72V285L10
IDT72V285L15
IDT72V285L20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
Min.
—
2
Max.
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
tA
DataAccessTime
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
20
8
Clock High Time
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tLDS
tLDH
tRS
EnableSetupTime
4
5
EnableHoldTime
0.5
3
1
1
LoadSetupTime
4
5
LoadHoldTime
ResetPulseWidth(3)
0.5
10
10
10
—
0
1
1
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
OutputEnabletoOutputinLowZ(4)
OutputEnabletoOutputValid
OutputEnabletoOutputinHighZ(4)
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
Read Clock to PAE
Clock to HF
3
4
5
0
0
0
2
3
3
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
2
6
3
8
3
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
10
tSKEW1
Skew time between RCLK and WCLK
forFF/IR
tSKEW2
tSKEW3
Skew time between RCLK and WCLK
for PAEand PAF
12
60
—
—
15
60
—
—
20
60
—
—
ns
ns
Skew time between RCLK and WCLK
forEF/OR
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
3.3V
2
330Ω
D.U.T.
510Ω
AC TEST CONDITIONS
Input Pulse Levels
30pF*
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
OutputLoad
1.5V
4512 drw 04
1.5V
Figure 2. Output Load
Includes jig and scope capacitances.
SeeFigure2
*
6
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONALDESCRIPTION
RelevanttimingdiagramsforIDTStandardmodecanbefoundinFigure
7, 8 and 11.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
TheIDT72V275/72V285supporttwodifferenttimingmodesofoperation:
IDTStandardmodeorFirstWordFallThrough(FWFT)mode. Theselection
ofwhichmodewilloperateisdeterminedduringMasterReset,bythestateof
FIRST WORD FALL THROUGH MODE (FWFT)
Inthismode,thestatusflags,IR,PAF,HF,PAE,andORoperateinthe
manneroutlinedinTable2.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwill
goHIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
theFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. ThismodeusestheEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary. Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe16,386th
wordfortheIDT72V275and 32,770thwordfortheIDT72V285,respectively
waswrittenintotheFIFO. ContinuingtowritedataintotheFIFOwillcausethe
PAFtogoLOW.Again,ifnoreadsareperformed, thePAFwillgoLOWafter
(32,769-m)writesfortheIDT72V275 and(65,537-m)writesfortheIDT72V285,
wheremisthefulloffsetvalue. Thedefaultsettingforthisvalueisstatedinthe
footnoteofTable2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
DwritestotheFIFO. D = 32,769writesfortheIDT72V275and65,537writes
fortheIDT72V285,respectively.NotethattheadditionalwordinFWFTmode
isduetothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAFand HFto go HIGH at the
conditionsdescribedinTable2.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
IDT STANDARD MODE
Inthismode,thestatusflags,FF,PAF,HF,PAE,andEFoperateinthe
manneroutlinedinTable1.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the 16,385th word for IDT72V275 and 32,769th word for IDT72V285
respectivelywaswrittenintotheFIFO. ContinuingtowritedataintotheFIFO
willcausetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifno
reads are performed, the PAF will go LOW after (32,768-m) writes for the
IDT72V275and(65,536-m)writesfortheIDT72V285. Theoffset“m”isthefull
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 32,768 writes for the IDT72V275 and 65,536 for the
IDT72V285,respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditionsdescribedinTable1.Iffurtherreadoperationsoccur,withoutwrite
operations, PAE will go LOW when there are n words in the FIFO, where n
is the empty offset value. Continuing read operations will cause the FIFO to
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,theEFwill
goLOWinhibitingfurtherreadoperations.RENisignoredwhentheFIFOis
empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure9,10and
12.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V275/
72V285hasinternalregistersfortheseoffsets.Defaultsettingsarestatedinthe
footnotesofTable1andTable2.OffsetvaluescanbeprogrammedintotheFIFO
inoneoftwoways;serialorparallelloadingmethod.Theselectionoftheloading
methodisdoneusingtheLD(Load)pin.DuringMasterReset,thestateofthe
LD input determines whether serial or parallel flag offset programming is
enabled. AHIGHonLDduringMasterResetselectsserialloadingofoffset
valuesandinaddition, setsadefaultPAEoffsetvalueof3FFH(athreshold
1,023wordsfromtheemptyboundary),andadefaultPAFoffsetvalueof3FFH
(athreshold1,023wordsfromthefullboundary). ALOWonLDduringMaster
Resetselectsparallelloadingofoffsetvalues,andinaddition,setsadefaultPAE
offset value of 07FH (a threshold 127 words from the empty boundary), and
a default PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
InadditiontoloadingoffsetvaluesintotheFIFO,italsopossibletoreadthe
currentoffsetvalues.It isonlypossibletoreadoffsetvaluesviaparallelread.
7
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Figure 4, Programmable Flag Offset Programming Sequence, summa-
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
rizesthecontrolpinsandsequenceforbothserialandparallelprogramming MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
modes. For a more detailed description, see discussion that follows. selected.
TABLE 1. STATUS FLAGS FOR IDT STANDARD MODE
72V275
72V285
FF PAF HF PAE EF
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
0
0
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m)(2) to 32,767
32,768
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m)(2) to 65,535
65,536
L
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2. STATUS FLAGS FOR FWFT MODE
72V275
72V285
IR PAF HF PAE OR
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+1(1)
1 to n+1(1)
(n+2) to 16,385
Number of
Words in
FIFO
(n+2) to 32,769
H
H
H
H
(2)
(2)
16,386 to (32,769-(m+1))
32,770 to (65,537-(m+1))
L
(32,769-m)
(65,537-m)
to 32,768
to 65,536
L
L
32,769
65,537
4512 drw 05
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
_
_
72V275 (32,768 x 18 BIT)
72V285 (65,536 x 18 BIT)
15 14
17
17
0
17
17
16 15
0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
0
0
15 14
16 15
FULL OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
03FFH if LD is HIGH at Master Reset
4512 drw 06
Figure 3. Offset Register Location and Default Values
72V275
72V285
LD WEN REN SEN
WCLK
X
RCLK
X
Parallel write to registers:
Empty Offset
0
0
0
1
1
0
1
1
0
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
30 bits for the 72V275
0
1
1
1
X
32 bits for the 72V285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
X
1
1
X
X
X
Write Memory
1
1
0
X
0
X
X
X
X
X
Read Memory
No Operation
1
1
1
X
X
4512 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
SERIAL PROGRAMMING MODE
writtentotheregister(s)pertainingtothatflag.MeasuringfromtherisingWCLK
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then edgethatachievestheabovecriteria;PAFwillbevalidaftertwomorerising
programming of PAE and PAF values can be achieved by using a WCLKedgesplustPAF,PAEwillbevalidafterthenexttworisingRCLKedges
combinationoftheLD,SEN,WCLKandSIinputpins.ProgrammingPAE plus tPAE plustSKEW2.
andPAFproceedsasfollows: whenLDandSENaresetLOW,dataonthe
The act of reading the offset registers employs a dedicated read offset
SIinputarewritten,onebitforeachWCLKrisingedge,startingwiththeEmpty registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
Offset LSB and ending with the Full Offset MSB. A total of 30 bits for the pinswhenLDissetLOWandRENissetLOW.DataarereadviaQnfromthe
IDT72V275and32bitsfortheIDT72V285.SeeFigure13,SerialLoadingof EmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.Uponthe
ProgrammableFlagRegisters,forthetimingdiagramforthismode.
secondLOW-to-HIGHtransitionofRCLK, dataarereadfromtheFullOffset
Using the serial method, individual registers cannot be programmed Register. ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffset
selectively. PAEandPAFcanshowavalidstatusonlyafterthecomplete Register.SeeFigure15, ParallelReadofProgrammableFlagRegisters,for
set of bits (for all offset registers) has been entered. The registers can be thetimingdiagramforthismode.
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
LDis LOW and SENis HIGH, no serial write to the registers can occur.
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
Write operations to the FIFO are allowed before and during the serial or both together. When RENand LDare restored to a LOW level, reading
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoes oftheoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
nothavetooccuratonce. AselectnumberofbitscanbewrittentotheSIinput betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
andthen,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemory the data word that was present on the output lines Qn will be overwritten.
via Dn bytogglingWEN. When WENisbroughtHIGHwithLDand SEN
Parallel reading of the offset registers is always permitted regardless of
restoredtoaLOW,thenextoffsetbitinsequenceiswrittentotheregistersvia which timing mode (IDT Standard or FWFT modes) has been selected.
SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. Once RETRANSMITOPERATION
LD and SENare both restored to a LOW level, serial offset programming
continues.
The Retransmit operation allows data that has already been read to be
accessedagain. Therearetwostages:first,asetupprocedurethatresetsthe
Fromthetimeserialprogramminghasbegun,neitherpartialflagwillbevalid readpointertothefirstlocationofmemory,thentheactualretransmit,which
until the full set of bits required to fill all the offset registers has been written. consistsofreadingoutthememorycontents,startingatthebeginningofmemory.
MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;PAF
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
will be valid after two more rising WCLK edges plus tPAF, PAEwill be valid RENandWENmustbeHIGHbeforebringingRTLOW. Atleastoneword,
after the next two rising RCLK edges plus tPAE plus tSKEW2.
Itisnotpossibletoreadtheflagoffsetvaluesinaserialmode.
butnomorethanD-2wordsshouldhavebeenwrittenintotheFIFObetween
Reset(MasterorPartial)andthetimeofRetransmitsetup. D = 32,768forthe
IDT72V275andD = 65,536fortheIDT72V285. InFWFTmode, D=32,769
for the IDT72V275 and D= 65,537 for the IDT72V285.
PARALLELMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
programming of PAE and PAF values can be achieved by using a RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
combinationoftheLD, WCLK,WENandDninputpins. ProgrammingPAE ifEFwasHIGHbeforesetup. Duringthisperiod,theinternalreadpointeris
and PAFproceeds as follows: when LDand WENare set LOW, data on initializedtothefirstlocationoftheRAMarray.
theinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-to-HIGH
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
transitionofWCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,data maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
arewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,once isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
again, to the Empty Offset Register. See Figure 14, Parallel Loading of requiresaLOWon RENtoenabletherisingedgeofRCLK. SeeFigure11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH.Duringthisperiod,theinternalreadpointerisset
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on RENto enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
ForeitherIDTStandardmodeorFWFTmode,updatingofthePAE,HF
andPAFflagsbeginwiththerisingedgeofRCLKthatRTissetup. PAEis
synchronized to RCLK, thus on the second rising edge of RCLK after RTis
setup,thePAEflagwillbeupdated. HFisasynchronous,thustherisingedge
ofRCLKthatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,thus
thesecondrisingedgeofWCLKthatoccurstSKEWaftertherisingedgeofRCLK
that RTis setup will update PAF. RTis synchronized to RCLK.
ProgrammableFlagRegisters,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer.Thetwopointersoperateindependently;however,areadandawrite
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
noeffectonthepositionofthesepointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregisters
doesnothavetooccuratonetime. One,twoormoreoffsetregisterscanbe
writtenandthenbybringingLDHIGH,writeoperationscanberedirectedto
theFIFOmemory. WhenLDissetLOWagain,andWENisLOW, thenext
offsetregisterinsequenceiswrittento.AsanalternativetoholdingWENLOW
andtogglingLD,parallelprogrammingcanalsobeinterruptedbysetting LD
LOWandtogglingWEN.
Notethatthestatusofapartialflag(PAEorPAF)outputisinvalidduring
theprogrammingprocess. Fromthetimeparallelprogramminghasbegun,a
partial flag output will not be valid until the appropriate offset word has been
10
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
RENand WENmust be HIGH before bringing RTLOW.
SIGNALDESCRIPTION
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read opera-
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on REN to enable the rising
edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for
the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting OR HIGH. During this period, the internal read pointer is set to
the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to
a LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array. PAE will go LOW, PAF will go HIGH, and
HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH.
IfFWFTisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold
127 words from the empty boundary and PAF is assigned a threshold 127 enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whetherornotthereareanywordspresentintheFIFOmemory. Italsouses
the Full Flag function (FF) to indicate whether or not the FIFO memory has
any free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
describing the LD pin for further details.)
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
beselected. ThismodeusesOutputReady(OR)toindicatewhetherornot
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges, REN = LOW is not necessary. Subse-
quent words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAEand
PAFoffsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array, PAEgoes LOW, PAFgoes HIGH, and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
orFirstWordFallThrough, thatmodewillremainselected. IftheIDTStandard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput. Datasetup
and hold times must be met with respect to the LOW-to-HIGH transition of
the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle,
theFF/IR, PAFandHFflagswillnotbeupdated. (NotethatWCLKisonly
capableofupdatingHFflagtoLOW.) TheWriteandReadClockscaneither
be independentorcoincident.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
WRITE ENABLE (WEN)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of the
memory.
When the WEN input is LOW, data may be loaded into the FIFO RAM
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
11
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
When WEN is HIGH, no new data is written in the RAM array on each flags,alongwiththemethodbywhichtheseoffsetregisterscanbeprogrammed,
WCLKcycle.
parallelorserial. AfterMasterReset,LDenableswriteoperationstoandread
To prevent data overflow in the IDT Standard mode, FF will go LOW, operationsfromtheoffsetregisters.Onlytheoffsetloadingmethodcurrently
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle, selectedcanbeusedtowritetotheregisters. Offsetregisterscanbereadonly
FFwill go HIGH allowing a write to occur. The FFis updated by two WCLK inparallel. ALOWonLDduringMasterResetselectsadefaultPAEoffset
cycles + tSKEW after the RCLK cycle.
valueof07FH(athreshold127wordsfromtheemptyboundary),adefaultPAF
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting offsetvalueof07FH(athreshold127wordsfromthefullboundary),andparallel
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo loadingofotheroffsetvalues. AHIGHon LDduringMasterResetselectsa
LOW allowing a write to occur. The IR flag is updated by two WCLK default PAEoffset value of 3FFH (a threshold 1,023 words from the empty
cycles + tSKEW afterthevalidRCLKcycle.
boundary),adefaultPAFoffsetvalueof3FFH(athreshold1,023wordsfrom
WEN is ignored when the FIFO is full in either FWFT or IDT Standard thefullboundary), andserialloadingofotheroffsetvalues.
mode.
READ CLOCK (RCLK)
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
of the flag offset values PAEand PAF. Pulling LDLOW will begin a serial
loadingorparallelloadorreadoftheseoffsetvalues.SeeFigure4, Program-
AreadcycleisinitiatedontherisingedgeoftheRCLKinput. Datacanbe mable Flag Offset Programming Sequence.
readontheoutputs, ontherisingedgeoftheRCLKinput. Itispermissibleto
stoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAEandHFflags
willnotbeupdated.(NotethatRCLKisonlycapableofupdatingtheHF flag
to HIGH.) The Write and Read Clocks can be independent or coincident.
OUTPUTS:
FULL FLAG (FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
functionisselected.WhentheFIFOisfull,FFwillgoLOW,inhibitingfurtherwrite
operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed
afterareset(eitherMRSorPRS),FFwillgoLOWafterDwritestotheFIFO
(D = 32,768fortheIDT72V275and 65,536fortheIDT72V285).SeeFigure
7,WriteCycleandFullFlagTiming(IDTStandardMode),fortherelevanttiming
information.
InFWFTmode,theInputReady(IR)functionisselected. IRgoesLOW
whenmemoryspaceisavailableforwritingindata. Whenthereisnolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
are performed after a reset (either MRS or PRS), IR will go HIGH after
D writes to the FIFO (D = 32,769 for the IDT72V275 and 65,537 for the
IDT72V285)SeeFigure9,WriteTiming(FWFTMode),fortherelevanttiming
information.
READ ENABLE (REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
and no new data is loaded into the output register. The data outputs Q0-Qn
maintainthepreviousdatavalue.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
furtherreadoperations. RENisignoredwhentheFIFOisempty.Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW
afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess
allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread
operations. RENis ignored when the FIFO is empty.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FFin IDT Standard mode.
FF/IRis synchronous and updated on the rising edge of WCLK. FF/IR
aredoubleregister-bufferedoutputs.
EMPTYFLAG(EF/OR)
SERIAL ENABLE (SEN)
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith
atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
LOWagain.SeeFigure10,ReadTiming(FWFTMode),fortherelevanttiming
information.
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofWCLK. (SeeFigure4.)
When SEN is HIGH, the programmable registers retains the previous
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
OUTPUTENABLE(OE)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.
EF/ORis synchronous and updated on the rising edge of RCLK.
InIDTStandardmode,EFisadoubleregister-bufferedoutput.InFWFT
mode,ORisatripleregister-bufferedoutput.
LOAD (LD)
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput
determinesoneoftwodefaultoffsetvalues(127or1,023)forthePAEandPAF
12
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PROGRAMMABLEALMOST-FULLFLAG(PAF)
SeeFigure17,ProgrammableAlmost-EmptyFlagTiming(IDTStandard
TheProgrammableAlmost-Fullflag(PAF)willgoLOWwhentheFIFO andFWFTMode),fortherelevanttiminginformation.
reaches the almost-full condition. In IDT Standard mode, if no reads are
PAE is synchronous and updated on the rising edge of RCLK.
performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(32,768-m)writesfortheIDT72V275 HALF-FULL FLAG (HF)
and (65,536-m)writesfortheIDT72V285.Theoffset“m”isthefulloffsetvalue.
ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference
In FWFT mode, the PAF will go LOW after (32,769-m) writes for the betweenthewriteandreadpointersbecomeslessthanorequaltohalfofthe
IDT72V275and(65,537-m)writesfortheIDT72V285,wheremisthefulloffset totaldepthofthedevice;therisingRCLKedgethataccomplishesthiscondition
value. ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
andFWFTMode),fortherelevanttiminginformation.
setsHFHIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HFwillgoLOWafter(D/2 + 1)writestotheFIFO, whereD=32,768
for the IDT72V275 and 65,536 for the IDT72V285.
PAFis synchronous and updated on the rising edge of WCLK.
InFWFTmode,ifnoreadsareperformedafterreset(MRSorPRS),HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 32,769 for the
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO IDT72V275 and 65,537 for the IDT72V285.
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
whentherearenwordsorlessintheFIFO. Theoffset“n”istheemptyoffset fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
WCLK,itisconsideredasynchronous.
InFWFTmode, thePAEwillgoLOWwhentherearen+1wordsorless
intheFIFO.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2. DATAOUTPUTS(Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
13
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
WEN
tRSS
tRSR
tRSR
tRSS
tRSR
t
FWFT
FWFT/SI
LD
tRSS
tRSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4512 drw 08
Figure 5. Master Reset Timing
14
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
t
RSS
RSS
t
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4512 drw 09
Figure 6. Partial Reset Timing
15
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tDH
tCLKH
NO WRITE
tCLKL
NO WRITE
2
1
WCLK
1
2
tSKEW1(1)
tSKEW1(1)
tDS
tDS
tDH
D
X
DX+1
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
tA
tA
DATA IN OUTPUT REGISTER
Q0 - Qn
DATA READ
NEXT DATA READ
4512 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising
edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENH
tENS
tENS
t
ENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
tOHZ
tOLZ
tOE
OE
t
SKEW3(1)
WCLK
tENS
tENH
tENH
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4512 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
16
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
17
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
18
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1
2
RCLK
t
ENH
t
ENS
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4512 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FFwill be HIGH throughout the Retransmit setup procedure. D = 32,768
for IDT72V275 and 65,536 for IDT72V285.
5. EF goes HIGH at 60ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
19
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
3
t
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENH
tRTS
REN
- Q
t
A
A
(4)
Q0
n
Wx
Wx+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
(5)
REF
t
tREF
t
PAE
PAE
tHF
HF
t
PAF
PAF
4512 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
tENH
t
ENS
tENH
tLDH
tDH
SEN
LD
tLDH
tLDS
tDS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4512 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 14 for the IDT72V275 and X = 15 for the IDT72V285.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
20
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
t
LDH
ENH
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAE
OFFSET
PAF
OFFSET
D0
- D15
4512 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
tCLKH
tCLKL
RCLK
tLDS
tLDH
tENH
tLDH
tENH
LD
tENS
REN
tA
tA
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
Q0
- Q15
4512 drw 18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
tPAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4512 drw 19
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode: D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
3.
t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
21
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
tPAE
tPAE
tSKEW2
1
2
1
2
RCLK
tENS
tENH
4512 drw 20
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
D-1
[
+ 2]
words in FIFO(2)
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4512 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
22
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
EFofeveryFIFO,andseparatelyANDingFFofeveryFIFO. InFWFTmode,
compositeflagscanbecreatedbyORingORofeveryFIFO,andseparately
ORing IR of every FIFO.
Figure19demonstratesawidthexpansionusingtwoIDT72V275/72V285
devices. D0 - D17 from each device form a 36-bit wide input bus and Q0-Q17
fromeachdeviceforma36-bitwideoutputbus.Anywordwidthcanbeattained
byaddingadditionalIDT72V275/72V285devices.
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. TheexceptionsaretheEFandFFfunctionsinIDTStandardmode
andtheIRandORfunctionsinFWFTmode. Becauseofvariationsinskew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/
ORassertion to vary by one cycle between FIFOs. In IDT Standard mode,
such problems can be avoided by creating composite flags, that is, ANDing
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72V275
72V285
PROGRAMMABLE (PAE)
72V275
72V285
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4512 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V275 can easily be adapted to applications requiring depths
greater than 32,768 and 65,536 for the IDT72V285 with an 18-bit bus width.
InFWFTmode,theFIFOscanbeconnectedinseries(thedataoutputsofone
FIFOconnectedtothedatainputsofthenext)withnoexternallogicnecessary.
Theresultingconfigurationprovidesatotaldepthequivalenttothesumofthe
depthsassociatedwitheachsingleFIFO. Figure20showsadepthexpansion
usingtwoIDT72V275/72V285devices.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW3
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain–no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device's ORline goes LOW,
enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
23
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
FWFT/SI
•
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
RCLK
WRITE CLOCK
WRITE ENABLE
•
WCLK
WEN
IR
RCLK
WCLK
READ ENABLE
OR
WEN
REN
IDT
72V275
72V285
IDT
72V275
72V285
INPUT READY
OUTPUT READY
REN
OR
IR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4512 drw 23
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is clock,fortheIRflag.
the sum of the delays for each individual FIFO:
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocationstothebeginningofthechain.
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
24
ORDERINGINFORMATION
XXXXX
Device Type
X
XX
X
X
X
X
Power Speed
Package
Process /
Temperature
Range
Tube or Tray
Tape and Reel
BLANK
8
Commercial (0OC to +70OC)
Industrial (-40OC to +85OC)
BLANK
I(1)
G
Green
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64)
Slim Thin Quad Flatpack (STQFP, PP64)
10
15
20
Commercial Only
Clock Cycle Time (tCLK
Com'l & Ind'l
)
Speed in Nanoseconds
Commercial Only
L
Low Power
72V275
72V285
32,768 x 18 3.3V — SuperSyncFIFO
65,635 x 18 3.3V — SuperSyncFIFO
4512 drw 24
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Green parts available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
04/24/2001
02/05/2009
10/16/2014
pgs. 1, 5, 6 and 25.
pgs. 1, and 25.
pgs. 1, 2 and 25.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
25
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