72V2105L20PF8 [IDT]
TQFP-64, Reel;
| 型号： | 72V2105L20PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-64, Reel |
| 文件： | 总26页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT HIGH DENSITY CMOS
SUPERSYNC FIFO™
131,072 x 18
IDT72V295
IDT72V2105
262,144 x 18
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP)
• High-performance submicron CMOS technology
FEATURES:
• Choose among the following memory organizations:
IDT72V295
IDT72V2105
⎯
⎯
131,072 x 18
262,144 x 18
• Pin-compatible with the IDT72V255/72V265 and the IDT72V275/
72V285 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• 5V input tolerant
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
DESCRIPTION:
The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These
FIFOsoffernumerousimprovementsoverpreviousSuperSyncFIFOs,includ-
ing the following:
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
• The limitationofthe frequencyofone clockinputwithrespecttothe other
has been removed. The Frequency Select pin (FS) has been removed,
• Program partial flags by either serial or parallel means
FUNCTIONAL BLOCK DIAGRAM
D0 -D17
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
131,072 x 18
262,144 x 18
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
4668 drw 01
Q0 -Q17
OE
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
OCTOBER 2008
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4668/4
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
The input port is controlled by a Write Clock (WCLK) input and a Write
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLKwhenWENis asserted.Theoutputportis controlledbyaReadClock
(RCLK) input and Read Enable (REN) input. Data is read from the FIFO on
every rising edge of RCLK when REN is asserted. An Output Enable (OE)
input is provided for three-state control of the outputs.
The frequencies ofboththe RCLKandthe WCLKsignals mayvaryfrom
0 to fMAX with complete independence. There are no restrictions on the
frequency of the one clock input with respect to the other.
DESCRIPTION (CONTINUED)
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period
found on previous SuperSync devices has been eliminated on this
SuperSync family.)
SuperSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to
buffer large amounts of data.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
DC(1)
Q17
Q16
GND
Q15
Q14
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
VCC
4
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
5
6
VCC
7
Q13
Q12
Q11
GND
Q10
Q9
8
9
10
11
12
13
14
15
16
Q8
Q7
D8
Q6
D7
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4668 drw 02
D
6
TQFP (PN64-1, order code: PF)
TOP VIEW
NOTE:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed.Areadoperation,whichconsists ofactivatingRENandenabling
a rising RCLK edge, will shift the word from internal memory to the data
output lines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequentwords writtentothe FIFOdorequire a LOWonREN foraccess.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions
are selectedinFWFTmode. HF, PAE andPAF arealways availableforuse,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be set
to switch at 127 or 1,023 locations from the empty boundary and the PAF
thresholdcanbesetat127or1,023locations fromthefullboundary. These
choices are made with the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn. REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and
write pointers are settothe firstlocationofthe FIFO. The FWFTpinselects
IDT Standard mode or FWFT mode. The LD pin selects either a partial flag
default setting of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are updated according
to the timing mode and default offsets selected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timingmodeandoffsets ineffect. PRSis usefulforresettingadeviceinmid-
operation, when reprogramming partial flags would be undesirable.
The Retransmitfunctionallows data tobe rereadfromthe FIFO. ALOW
on the RT input during a rising RCLK edge initiates a retransmit operation
by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72V295/72V2105 are fabricated using IDT’s high speed submi-
cron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (D
0
- Dn)
DATA OUT (Q0 - Qn)
IDT
72V295
72V2105
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
4668 drw 03
Figure 1. Block Diagram of Single 131,072 x 18 and 262,144 x 18 Synchronous FIFO
3
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
Data Inputs
I/O
I
Description
Data inputs for a 18-bit bus.
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
Write Clock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
RCLK
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN
OE
SEN
LD
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or
1,023) and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master
Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
Output Ready
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
Programmable
Almost-Full Flag
PAE
Programmable
Almost-Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF
Q0–Q17
Half-Full Flag
Data Outputs
Power
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 18-bit bus.
VCC
+3.3 Volt power supply pins.
GND
Ground
Ground pins.
4
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com’l & Ind’l
Unit
(2)
VTERM
TerminalVoltage
–0.5to+4.5
V
Symbol
Parameter
Min.
3.0
0
Typ. Max. Unit
with respect to GND
VCC
Supply Voltage (Com'l & Ind'l)
3.3
0
3.6
0
V
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND Supply Voltage (Com'l & Ind'l)
VIH
Input High Voltage (Com'l & Ind'l)
Input Low Voltage (Com'l & Ind'l)
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
2.0
—
0
—
—
—
—
5.5
0.8
+70
+85
V
DCOutputCurrent
mA
(1)
VIL
TA
V
NOTES:
°C
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
-40
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2. VCC terminal only.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C)
IDT72V295L
IDT72V2105L
Commercial and Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
1
µ A
µA
ILO(3)
–10
10
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
2.4
—
—
—
—
0.4
60
V
V
VOL
ICC1(4,5,6)
ICC2(4,7)
mA
mA
20
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT - VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 5 + fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C)
Commercial
IDT72V295L10
IDT72V2105L10
Com’l & Ind’l
IDT72V295L15
IDT72V2105L15
Commercial
IDT72V295L20
IDT72V2105L20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
66.7
10
Min.
Max.
50
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
—
2
—
2
tA
DataAccessTime
Clock Cycle Time
Clock High Time
12
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15
6
—
—
—
—
—
—
—
—
—
—
—
—
15
20
8
—
—
—
—
—
—
—
—
—
—
—
—
20
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tLDS
tLDH
tRS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
5
0.5
3
1
1
4
5
LoadHoldTime
0.5
10
15
10
—
0
1
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
—
—
—
6
—
—
—
8
—
—
—
10
3
4
5
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
0
0
0
2
2
2
(4)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
OutputEnabletoOutputinHighZ
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
2
6
2
8
2
10
—
—
—
—
—
8
6.5
6.5
6.5
6.5
16
—
—
—
—
—
9
10
—
—
—
—
—
10
12
10
12
10
12
Read Clock to PAE
10
12
Clock to HF
20
22
tSKEW1
Skew time between RCLK and WCLK
—
—
—
for EF/OR and FF/IR
tSKEW2
Skew time between RCLK and WCLK
12
—
14
—
15
—
ns
for PAE and PAF
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
3. Pulse widths less than minimum values are not allowed.
3.3V
4. Values guaranteed by design, not currently tested.
330Ω
D.U.T.
510Ω
AC TEST CONDITIONS
30pF*
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
4668 drw 04
1.5V
1.5V
Figure 2. Output Load
* Includes jig and scope capacitances.
See Figure 2
6
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where nis the emptyoffsetvalue. Continuingreadoperations willcause the
FIFO to become empty. When the last word has been read from the FIFO,
the EF will go LOW inhibiting further read operations. REN is ignored when
the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7, 8 and 11.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V295/72V2105 support two different timing modes of opera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by
the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whether or not there are any words present in the FIFO. It also uses the Full
Flag function (FF) to indicate whether or not the FIFO has any free space
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicatewhetherornottheFIFOhasanyfreespaceforwriting. IntheFWFT
mode, the first word written to an empty FIFO goes directly to Qn after three
RCLKrisingedges, REN =LOWis notnecessary. Subsequentwords must
be accessed using the Read Enable (REN) and RCLK.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
65,538thwordfortheIDT72V295and 131,074thwordfortheIDT72V2105,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF willgoLOWafter(131,073-m)writes fortheIDT72V295 and(262,145-
m) writes for the IDT72V2105, where m is the full offset value. The default
setting for this value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGHafterDwritestotheFIFO. D = 131,073writesfortheIDT72V295and
262,145 writes for the IDT72V2105, respectively. Note that the additional
word in FWFT mode is due to the capacity of the memory plus output
register.
IftheFIFOis full,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR willgoHIGHinhibitingfurtherreadoperations. REN is ignored
when the FIFO is empty.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable 1. Towrite data intotothe FIFO, Write Enable (WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The defaultsettingforthis value is statedinthe footnote ofTable 1. This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
oncethe65,537thwordfor IDT72V295and 131,073rdwordforIDT72V2105
respectively was written into the FIFO. Continuing to write data into the
FIFOwillcausetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,
if no reads are performed, the PAF will go LOW after (131,072-m) writes for
the IDT72V295and(262,144-m)writes forthe IDT72V2105. The offset“m”
is the full offset value. The default setting for this value is stated in the
footnoteofTable1.This parameteris alsouserprogrammable.Seesection
on Programmable Flag Offset Loading.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 131,072 writes for the IDT72V295 and
262,144 for the IDT72V2105, respectively.
7
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PROGRAMMING FLAG OFFSETS
07FH (a threshold 127 words from the empty boundary), and a default PAF
Full and Empty Flag offset values are user programmable. The offset value of 07FH (a threshold 127 words from the full boundary). See
IDT72V295/72V2105 has internal registers for these offsets. Default set- Figure 3, Offset Register Location and Default Values.
In addition to loading offset values into the FIFO, it also possible to read
the current offset values. It is only possible to read offset values via parallel
read.
Figure 4, Programmable Flag Offset Programming Sequence, summa-
rizesthecontrolpinsandsequenceforbothserialandparallelprogramming
modes. For a more detailed description, see discussion that follows.
The offsetregisters maybe programmed(andreprogrammed)anytime
after Master Reset, regardless of whether serial or parallel programming
has been selected.
tings are stated in the footnotes of Table 1 and Table 2. Offset values can
be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the LD (Load)
pin.DuringMasterReset,thestateoftheLDinputdetermineswhetherserial
orparallelflagoffsetprogrammingis enabled. AHIGHonLD duringMaster
Reset selects serial loading of offset values and in addition, sets a default
PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary), anda defaultPAF offsetvalue of3FFH(a threshold1,023words
from the full boundary). A LOW on LD during Master Reset selects parallel
loading of offset values, and in addition, sets a default PAE offset value of
TABLE I ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IDT72V295
IDT72V2105
FF PAF HF PAE EF
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
0
0
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
(n+1) to 65,536
(n+1) to 131,072
65,537 to (131,072-(m+1))
131,073 to (262,144-(m+1))
(262,144-m) (2) to 262,143
262,144
(2)
(131,072-m)
to 131,071
L
L
L
131,072
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE II ⎯ STATUS FLAGS FOR FWFT MODE
IDT72V295
IDT72V2105
0
IR PAF HF
OR
PAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+1(1)
1 to n+1(1)
Number of
Words in
H
H
H
H
(n+2) to 131,073
131,074 to (262,145-(m+1))
(262,145-m) to 262,144
262,145
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
(2)
(2)
1)
FIFO (
L
L
L
4668 drw 05
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT72V295 (131,072 x 18-BIT)
IDT72V2105 (262,144 x 18-BIT)
0
17
16 15
0
16 15
17
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
17
17
1
0
17
17
2 1
0
0
EMPTY OFFSET
(MSB) REGISTER
EMPTY OFFSET
(MSB) REGISTER
DEFAULT
0H
DEFAULT
0H
16 15
0
16
15
FULL OFFSET (LSB) REGISTER
DEFAULT VALUE
FULL OFFSET (LSB) REGISTER
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
17
1
0
2 1
0
17
FULL OFFSET
FULL OFFSET
(MSB) REGISTER
(MSB) REGISTER
DEFAULT
0H
DEFAULT
0H
4668 drw 06
Figure 3. Offset Register Location and Default Values
IDT72V295
IDT72V2105
LD WEN REN SEN
WCLK
RCLK
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
0
0
0
0
1
1
1
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
1
0
X
X
34 bits for the 72V295
36 bits for the 72V2105
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
1
1
1
X
X
X
No Operation
Write Memory
1
1
0
X
0
X
X
X
X
X
Read Memory
No Operation
1
1
1
X
X
4668 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SERIAL PROGRAMMING MODE
offset register in sequence is written to. As an alternative to holding WEN
IfSerialProgrammingmode has beenselected, as describedabove, then LOW and toggling LD, parallel programming can also be interrupted by
programming of PAE and PAF values can be achieved by using a combina- setting LD LOW and toggling WEN.
Note that the status of a partial flag (PAE or PAF) output is invalid during
the programmingprocess. Fromthe time parallelprogramminghas begun,
a partial flag output will not be valid until the appropriate offset word has
been written to the register(s) pertaining to that flag. Measuring from the
risingWCLKedgethatachievestheabovecriteria;PAFwillbevalidaftertwo
morerisingWCLKedges plus tPAF, PAE willbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-
Qn pins when LD is set LOW and REN is set LOW. For the IDT72V295/
72V2105, data are read via Qn from the Empty Offset LSB Register on the
first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH
transition of RCLK, data are read from the Empty Offset MSB Register.
UponthethirdLOW-to-HIGHtransitionofRCLK,dataarereadfromtheFull
Offset LSB Register. Upon the fourth LOW-to-HIGH transition of RCLK,
dataarereadfromtheFullOffsetMSBRegister. ThefifthtransitionofRCLK
reads, once again, from the Empty Offset LSB Register. See Figure 15,
Parallel Read of Programmable Flag Registers, for the timing diagram for
this mode.
tion of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF
proceeds as follows: when LD and SEN are set LOW, data on the SI input
are written, one bit for each WCLK rising edge, starting with the Empty
Offset LSB and ending with the Full Offset MSB. A total of 34 bits for the
IDT72V295 and 36 bits for the IDT72V2105. See Figure 13, Serial Loading
of Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
WhenLDisLOWandSENisHIGH,noserialwritetotheregisterscanoccur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing LD and SEN HIGH, data can be written to
FIFOmemoryvia Dn bytogglingWEN. WhenWEN is broughtHIGHwithLD
and SEN restored to a LOW, the next offset bit in sequence is written to the
registers via SI. If an interruption of serial programming is desired, it is
sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and
deactivate LD. Once LD and SEN are both restored to a LOW level, serial
offset programming continues.
Itis permissible tointerruptthe offsetregisterreadsequence withreads
orwritestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,
LD,orbothtogether.WhenRENandLDarerestoredtoaLOW level,reading
ofthe offsetregisters continues where itleftoff. Itshouldbe noted, andcare
should be taken from the fact that when a parallel read of the flag offsets is
performed, the data word that was present on the output lines Qn will be
overwritten.
From the time serial programming has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
Parallelreadingofthe offsetregisters is always permittedregardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
PARALLEL MODE
RETRANSMIT OPERATION
If Parallel Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and Dn input pins. For the ID72V295/
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
whichconsistsofreadingoutthememorycontents,startingatthebeginning
of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW. At least two
words, butnomorethanD-2 words, should have been written into the FIFO
and read from the FIFO between Reset (Master or Partial) and the time of
Retransmit setup. D = 131,072 for the IDT72V295 and D = 262,144 for the
IDT72V2105. In FWFT mode, D = 131,073 for the IDT72V295 and D =
262,145 for the IDT72V2105.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeableifEFwasHIGHbeforesetup. Duringthisperiod,theinternalread
pointer is initialized to the first location of the RAM array.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
RetransmitsetuprequiresaLOWonRENtoenabletherisingedgeofRCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
72V2105, programming PAE and PAF proceeds as follows: when LD and
WEN are set LOW, data on the inputs Dn are written into the Empty Offset
LSB Register on the first LOW-to-HIGH transition of WCLK. Upon the
second LOW-to-HIGH transition of WCLK, data are written into the Empty
Offset MSB Register. Upon the third LOW-to-HIGH transition of WCLK,
data are written into the Full Offset LSB Register. Upon the fourth LOW-to-
HIGHtransitionofWCLK,dataarewrittenintotheFullOffsetMSBRegister.
The fifth transition of WCLK writes, once again, to the Empty Offset LSB
Register.SeeFigure14, ParallelLoadingofProgrammableFlagRegisters,for
the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset
register pointer. The act of reading offsets employs a dedicated read offset
register pointer. The two pointers operate independently; however, a read
and a write should not be performed simultaneously to the offset registers.
A Master Reset initializes both pointers to the Empty Offset (LSB) register.
A Partial Reset has no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregisters
does not have to occur at one time. One, two or more offset registers can
bewrittenandthenbybringingLD HIGH,writeoperations canberedirected
tothe FIFOmemory. WhenLD is setLOWagain,andWEN is LOW,the next
10
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting OR HIGH. During this period, the internal read and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
pointer is set to the first location of the RAM array.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
synchronized to RCLK, thus on the second rising edge of RCLK after RT is
When OR goes LOW, Retransmit setup is complete; at the same time, setup, the PAE flag will be updated. HF is asynchronous, thus the rising
the contents of the first location appear on the outputs. Since FWFT mode edgeofRCLKthatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,
is selected, the first word appears on the outputs, no LOW on REN is thus thesecondrisingedgeofWCLKthatoccurs tSKEW aftertherisingedge
necessary. Reading all subsequent words requires a LOW on REN to of RCLK that RT is setup will update PAF. RT is synchronized to RCLK.
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
11
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeableifEFwasHIGHbeforesetup. Duringthisperiod,theinternalread
pointer is initialized to the first location of the RAM array.
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
RetransmitsetuprequiresaLOWonRENtoenabletherisingedgeofRCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting OR HIGH. During this period, the internal read pointer is set to
the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
CONTROLS:
MASTER RESET ( MRS )
A Master Reset is accomplished whenever the MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the
firstlocationofthe RAMarray. PAE will goLOW, PAF willgoHIGH, and HF
will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
IfLD is LOWduringMasterReset, then PAE is assigneda threshold127
words fromthe emptyboundaryandPAF is assigneda threshold127words
from the full boundary; 127 words corresponds to an offset value of 07FH.
Following Master Reset, parallel loading of the offsets is permitted, but not
serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section
describing the LD pin for further details.)
FIRST WORD FALL THROUGH/SERIAL IN ( FWFT/SI )
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whetherornotthereareanywordspresentintheFIFOmemory. Italsouses
the Full Flag function (FF) to indicate whether or not the FIFO memory has
anyfree space forwriting. InIDTStandardmode, everywordreadfromthe
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
PARTIAL RESET ( PRS
)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
mode is active, thenFF willgoHIGHandEF willgoLOW. Ifthe FirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
WRITE CLOCK ( WCLK )
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup
and hold times must be met with respect to the LOW-to-HIGH transition of
theWCLK.Itis permissibletostoptheWCLK. NotethatwhileWCLKis idle,
the FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capableofupdatingHFflagtoLOW.) TheWriteandReadClocks caneither
be independent or coincident.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT ( RT )
WRITE ENABLE ( WEN )
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of the
memory.
When the WEN input is LOW, data may be loaded into the FIFO RAM
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
12
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
When WEN is HIGH, no new data is written in the RAM array on each LOAD ( LD )
WCLK cycle.
This is a dual purpose pin. During Master Reset, the state of the LD input
To prevent data overflow in the IDT Standard mode, FF will go LOW, determines one of two default offset values (127 or 1,023) for the PAE and PAF
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle, flags, along with the method by which these offset registers can be pro-
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK grammed, parallel or serial. After Master Reset, LD enables write operations
cycles + tSKEW after the RCLK cycle.
to and read operations from the offset registers. Only the offset loading method
Topreventdata overflow inthe FWFTmode, IR willgoHIGH, inhibiting currently selected can be used to write to the registers. Offset registers can be
further write operations. Upon the completion of a valid read cycle, IR will read only in parallel. A LOW on LD during Master Reset selects a default PAE
go LOW allowing a write to occur. The IR flag is updated by two WCLK offsetvalueof07FH(athreshold127wordsfromtheemptyboundary),adefault
cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard parallel loading of other offset values. A HIGH on LD during Master Reset
mode.
PAF offset value of 07FH (a threshold 127 words from the full boundary), and
selects a default PAE offset value of 3FFH (a threshold 1,023 words from the
empty boundary), a default PAF offset value of 3FFH (a threshold 1,023 words
from the full boundary), and serial loading of other offset values.
READ CLOCK ( RCLK )
A read cycle is initiated on the rising edge of the RCLK input. Data can
After Master Reset, the LD pin is used to activate the programming
bereadontheoutputs,ontherisingedgeoftheRCLKinput. Itispermissible process of the flag offset values PAE and PAF. Pulling LD LOW will begin a
tostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAEandHFflags serial loading or parallel load or read of these offset values. See Figure 4,
willnotbe updated. (Note thatRCLKis onlycapable ofupdatingthe HF flag Programmable Flag Offset Programming Sequence.
to HIGH.) The Write and Read Clocks can be independent or coincident.
OUTPUTS:
READ ENABLE ( REN
)
FULL FLAG ( FF/IR )
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not
empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 131,072fortheIDT72V295and262,144fortheIDT72V2105).SeeFigure
7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant
timing information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger
any free space left, IR goes HIGH, inhibiting further write operations. If no
reads are performed after a reset (either MRS or PRS), IR will go HIGH after
D writes to the FIFO (D = 131,073 for the IDT72V295 and 262,145 for the
IDT72V2105) See Figure 9, Write Timing (FWFT Mode), for the relevant
timing information.
The IR status not only measures the contents of the FIFO memory, but
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
maintain the previous data value.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibiting further read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ tSKEW after the first write. REN does not need to be asserted LOW. In
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN =
LOW), inhibiting further read operations. REN is ignored when the FIFO is
empty.
SERIAL ENABLE ( SEN )
EMPTY FLAG ( EF/OR )
The SEN input is an enable used only for serial programming of the
offset registers. The serial programming method must be selected during
MasterReset. SENisalwaysusedinconjunctionwithLD. Whentheselines
are both LOW, data at the SI input can be loaded into the program register
one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
When SEN is HIGH, the programmable registers retains the previous
settings andnooffsets are loaded. SEN functions the same wayinbothIDT
Standard and FWFT modes.
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EF)functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibiting
further read operations. When EF is HIGH, the FIFO is not empty. See
Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT
Standard Mode), for the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes
LOW at the same time that the first word written to an empty FIFO appears
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing (FWFT
Mode), for the relevant timing information.
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Q
into a high impedance state.
n) goes
13
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
EF/OR is synchronous and updated on the rising edge of RCLK.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
InIDTStandardmode, EF is a double register-bufferedoutput. InFWFT intheFIFO.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable2.
mode, OR is a triple register-buffered output.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
dard and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are HALF-FULL FLAG ( HF )
performed after reset (MRS), PAF will go LOW after (D - m) words are written
This outputindicates ahalf-fullFIFO.TherisingWCLKedgethatfills the
to the FIFO. The PAF will go LOW after (131,072-m) writes for the IDT72V295 FIFO beyond half-full sets HF LOW. The flag remains LOW until the
and (262,144-m) writes for the IDT72V2105. The offset “m” is the full offset difference between the write and read pointers becomes less than or equal
value. The default setting for this value is stated in the footnote of Table 1.
to half of the total depth of the device; the rising RCLK edge that accom-
In FWFT mode, the PAF will go LOW after (131,073-m) writes for the plishes this condition sets HF HIGH.
IDT72V295and(262,145-m)writes forthe IDT72V2105, where mis the full
offset value. The default setting for this value is stated in the footnote of PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 131,072
Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
In IDT Standard mode, if no reads are performed after reset (MRS or
for the IDT72V295 and 262,144 for the IDT72V2105.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 131,073 for the
IDT72V295 and 262,145 for the IDT72V2105.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
The Programmable Almost-Empty flag (PAE) will go LOW when the and WCLK, it is considered asynchronous.
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will
goLOWwhentherearenwordsorlessintheFIFO.Theoffset“n”istheempty DATA OUTPUTS ( Q0-Q17 )
offsetvalue.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
(Q0 - Q17) are data outputs for 18-bit wide data.
14
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
tRS
MRS
REN
WEN
tRSS
tRSR
tRSR
tRSS
tRSR
t
FWFT
FWFT/SI
LD
tRSS
tRSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4668 drw 08
Figure 5. Master Reset Timing
15
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSS
tRSS
tRSS
tRSR
tRSR
WEN
RT
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
tRSF
EF/OR
tRSF
FF/IR
PAE
tRSF
tRSF
tRSF
PAF, HF
OE = HIGH
Q0 - Qn
4668 drw 09
OE = LOW
Figure 6. Partial Reset Timing
16
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
t
CLK
tCLKH
NO WRITE
t
CLKL
NO WRITE
WCLK
2
t
1
2
1
(1)
(1)
SKEW1
tSKEW1
t
DH
t
tDH
tDS
t
DS
DX
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
WFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
tA
tA
Q0
- Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4668 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising
edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENS
tENH
tENS
tENH
tENS
tENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
LAST WORD
D0
Q0
- Qn
LAST WORD
D1
tOLZ
tOLZ
tOHZ
tOE
OE
tSKEW1(1)
WCLK
tENH
tENS
tENH
tENS
WEN
tDHS
tDS
tDH
tDS
D0
- Dn
D0
D1
4668 drw 11
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
18
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
19
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
RCLK
1
2
tENH
tENS
tENS
tENH
t
RTS
REN
tA
tA
tA
(3)
(3)
Q0 - Qn
Wx
Wx+1
W1
W2
tSKEW2
1
2
WCLK
WEN
RT
t
RTS
t
ENS
t
ENH
t
REF
t
REF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4668 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 131,072 for IDT72V295 and 262,144 for IDT72V2105.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3
RCLK
1
2
4
tENH
tENS
tENH
tENS
tRTS
REN
tA
tA
tA
tA
W4
(4)
(4)
(4)
Q0 - Qn
Wx
Wx+1
W2
W1
W3
tSKEW2
1
2
WCLK
tRTS
tENS
WEN
tENH
tREF
RT
OR
tREF
tPAE
PAE
tHF
HF
tPAF
PAF
4668 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
tENH
tENS
tENH
SEN
LD
tLDH
tLDH
tLDS
t
DH
(1)
t
DS
(1)
BIT X
BIT 0
BIT 0
BIT X
SI
FULL OFFSET
EMPTY OFFSET
4668 drw 16
NOTE:
1. X = 16 for the IDT72V295 and X = 17 for the IDT72V2105.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
tCLK
tCLKH
tCLKL
WCLK
LD
tLDS
tLDH
tLDH
tENS
tENH
tENH
WEN
tDH
tDH
tDS
D0 - D15
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4668 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDS
tLDH
tLDH
LD
tENH
tENS
tENH
REN
tA
tA
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
DATA IN OUTPUT REGISTER
Q0
- Q15
4668 drw 18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
WEN
PAF
1
2
2
1
tENS
tENH
t
PAF
t
PAF
(2)
D - m words in FIFO
(2)
D - (m+1) words in FIFO
D-(m+1) words
(2)
in FIFO
(3)
SKEW2
t
RCLK
tENH
tENS
4668 drw 19
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 131,072 for the IDT72V295 and 262,144 for the IDT72V2105.
In FWFT mode: D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
3.
t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
22
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
(3)
(3)
(3)
n+1 words in FIFO
n+2 words in FIFO
,
n+1 words in FIFO
n+1 words in FIFO
(4)
t
PAE
t
PAE
tSKEW2
RCLK
1
2
1
2
tENS
tENH
4668 drw 20
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
2
D -1
2
[
+ 2
]
words in FIFO(2)
D-1
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4668 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 131,072 for the IDT72V295 and 262,144 for the IDT72V2105.
2. For FWFT mode: D = maximum FIFO depth. D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
problems can be avoided by creating composite flags, that is, ANDing EF
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags canbe createdbyORingOR ofeveryFIFO, andseparately
ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72V295/
72V2105 devices. D0-D17 from each device form a 36-bit wide input bus
andQ0-Q17 fromeachdevice forma 36-bitwide outputbus. Anywordwidth
can be attained by adding additional IDT72V295/72V2105 devices.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertiontovarybyonecyclebetweenFIFOs. InIDTStandardmode,such
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m
- Dm
n
m + n
D0
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
72V295
72V2105
IDT
72V295
72V2105
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR) #1
FULL FLAG/INPUT READY (FF/IR) #2
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
E
MPTY FLAG/OUTPUT READY (EF/OR) #2
GATE
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
n
Qm+1 - Qn m + n
FIFO
#2
FIFO
#1
DATA OUT
m
4668 drw 22
Q0
- Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 131,072 x 36 and 262,144 x 36 Width Expansion
24
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
OR
WEN
REN
IDT
72V295
72V2105
INPUT READY
IDT
72V295
72V2105
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
n
n
DATA OUT
DATA IN
Dn
Qn
Dn
4668 drw 23
Figure 20. Block Diagram of 262,144 x 18 and 524,288 x 18 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
tSKEW1 specificationis notmetbetweenWCLKandtransferclock, orRCLK
The IDT72V295 can easily be adapted to applications requiring depths and transfer clock, for the OR flag.
greater than 131,072 and 262,144 for the IDT72V2105 with an 18-bit bus
The "ripple down" delay is only noticeable for the first word written to an
width. In FWFT mode, the FIFOs can be connected in series (the data empty depth expansion configuration. There will be no delay evident for
outputs of one FIFO connected to the data inputs of the next) with no subsequent words written to the configuration.
externallogicnecessary. The resultingconfigurationprovides a totaldepth
The first free location created by reading from a full depth expansion
equivalent to the sum of the depths associated with each single FIFO. configuration will "bubble up" from the last FIFO to the previous one until it
Figure 24 shows a depth expansion using two IDT72V295/72V2105 de- finally moves into the first FIFO of the chain. Each time a free location is
vices.
createdinoneFIFOofthechain,thatFIFO's IRlinegoes LOW,enablingthe
Care should be taken to select FWFT mode during Master Reset for all preceding FIFO to write a word to fill it.
FIFOs in the depth expansion configuration. The first word written to an
Fora fullexpansionconfiguration, the amountoftime ittakes forIR ofthe
emptyconfigurationwillpass fromone FIFOtothe next("ripple down")until first FIFO in the chain to go LOW after a word has been read from the last
it finally appears at the outputs of the last FIFO in the chain–no read FIFO is the sum of the delays for each individual FIFO:
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
(N – 1)*(3*transfer clock) + 2 TWCLK
OR line goes LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR where N is the number of FIFOs in the expansion and TWCLK is the WCLK
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last period. Note that extra cycles should be added for the possibility that the
FIFO's outputs) after a word has been written to the first FIFO is the sum of tSKEW1 specificationis notmetbetweenRCLKandtransferclock, orWCLK
the delays for each individual FIFO:
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK possible, to the end of the chain and free locations to the beginning of the
period. Note that extra cycles should be added for the possibility that the chain.
25
ORDERING INFORMATION
XXXXX
X
XX
X
X
Pr ocess /
Temper atur e
Ra nge
Dev i ce Ty pe
Power
Speed
Package
Commer c i a l (0°C to +70°C)
Industr ial (- 40°C to +85°C)
BLANK
I(1)
PF
Thin Pl astic Quad F l atpack (TQF P, PN64- 1)
10
15
20
Commer c i a l Onl y
Cl ock Cy cl eTime (t CLK
Speed in Nanoseconds
)
Com' l & Ind' l
Commer c i a l Onl y
L
L ow P ower
131,072 x 18 ⎯ 3.3VSuper Sy ncF IF O
262,144 x 18 ⎯ 3.3VSuper Sy ncF IF O
72V295
72V2105
4668 dr w24
NOTE:
1. Industrial temperature range is available as a standard device for 15ns.
DATASHEETDOCUMENTHISTORY
9/12/2000
12/18/2000
03/27/2001
10/22/2008
pg. 5.
pgs. 5, 6 and 26.
pgs. 6 and 26.
pg. 26.
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26
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