72T3655L6-7BBG [IDT]
FIFO, 2KX36, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208;
| 型号： | 72T3655L6-7BBG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 2KX36, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总57页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
IDT72T36105, IDT72T36115, IDT72T36125
FEATURES:
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
• Choose among the following memory organizations:
IDT72T3645
IDT72T3655
IDT72T3665
IDT72T3675
IDT72T3685
IDT72T3695
IDT72T36105
IDT72T36115
IDT72T36125
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
65,536 x 36
131,072 x 36
262,144 x 36
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Read Enable & Read Clock Echo outputs aid high speed operation • JTAG port, provided for Boundary Scan function
• User selectable Asynchronous read and/or write port timing
• Mark & Retransmit, resets read pointer to user marked position
• Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)
• Write Chip Select (WCS) input enables/disables Write operations • Easily expandable in depth and width
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts are available, see ordering information
FUNCTIONALBLOCKDIAGRAM
D0
-Dn
(x36, x18 or x9)
LD SEN
SCLK
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
FLAG
LOGIC
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
262,144 x 36
WRITE POINTER
BE
CONTROL
LOGIC
READ POINTER
IP
BM
IW
OW
BUS
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
ASYR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
EREN
OE
5907 drw01
Q0 -Qn (x36, x18 or x9)
ERCLK
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheTeraSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
FEBRUARY 2009
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5907/20
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
PAF
EF
REN
RT
RCS
OE
WCLK
FWFT/SI
FSO
SHSTL
FSI
IP
RHSTL
BM
RCLK
MARK
Q35
WCS
SEN
VREF
D35
D33
D31
D29
D27
D24
D22
D20
D18
D16
D14
D11
D9
WEN
MRS
LD
PAE
SCLK
ASYW
IW
B
C
D
E
F
WHSTL
PFM
PRS
FF
HF
BE
ASYR
EREN
OW
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
V
DDQ
DDQ
D34
V
V
CC
CC
V
CC
GND
GND
GND
GND
GND
GND
V
CC
V
Q33
V
CC
Q34
Q32
Q30
D32
V
CC
Q31
V
CC
V
V
DDQ
CC
D30
V
V
CC
CC
GND
GND
GND
GND
GND
GND
GND
Q29
G
H
J
GND
GND
GND
Q27
D28
D26
D25
D23
D21
D19
D17
D15
D12
D10
GND
GND
GND
GND
GND
GND
GND
V
CC
Q28
Q26
Q24
Q21
Q19
Q17
V
V
V
V
V
V
V
CC
CC
GND
GND
GND
GND
GND
GND
GND
V
V
CC
CC
Q25
Q23
Q22
Q20
Q18
Q16
Q13
Q11
Q9
K
L
CC
GND
GND
GND
GND
VCC
CC
CC
V
V
CC
M
N
P
R
T
V
CC
V
CC
DDQ
CC
CC
V
CC
GND
V
CC
GND
GND
GND
GND
GND
V
V
CC
V
DDQ
V
DDQ
Q15
Q12
V
CC
V
CC
V
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q14
Q6
DDQ
D4
TDO
ERCLK
10
Q0
Q1
11
Q2
Q4
D13
D8
D6
D7
D2
D0
TMS
TCK
TDI
Q10
Q8
Q5
Q7
TRST
D5
D3
D1
Q3
1
2
3
4
5
6
7
8
9
12
13
14
15
16
5907 drw02
IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695Only
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
2
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINCONFIGURATION(CONTINUED)
A1 BALL PAD CORNER
A
V
V
V
CC
CC
CC
V
DDQ
V
V
DDQ
DDQ
V
V
DDQ
DDQ
VDDQ
V
V
V
V
V
V
CC
V
V
V
V
V
CC
V
V
V
V
V
V
CC
CC
V
V
V
CC
V
V
V
CC
WCLK
WEN
GND
GND
RCLK
V
V
DDQ
DDQ
PRS
MRS
LD
FF
PAF
HF
EREN
EF
OE
B
C
D
E
F
V
V
DDQ
DDQ
VDDQ
CC
CC
CC
CC
CC
CC
CC
CC
CC
REN
RCS
RT
CC
MARK
V
DDQ
V
DDQ
V
V
V
V
V
DDQ
DDQ
VDDQ
WCS
PAE
IP
GND
GND
OW
RHSTL
CC
CC
CC FWFT/SI
FS0
SHSTL
FS1
BM
PFM
GND
GND
GND
V
DDQ
V
V
V
DDQ
BE
ASYR
CC
CC
CC
CC
GND
GND
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
CC
G
H
J
DDQ
V
CC
SCLK WHSTL
V
DDQ
V
DDQ
SEN
V
CC
VCC
V
CC
GND
GND
GND
GND
GND
GND
GND
V
DDQ
V
V
DDQ
DDQ
V
V
V
DDQ
DDQ
ASYW
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
CC
V
V
CC
CC
V
V
CC
CC
VREF
VDDQ
K
L
V
IW
V
DDQ
V
DDQ
DDQ
D33
D30
D27
D24
D34
D31
D28
D25
D22
D20
D17
D35
D32
GND
GND
GND
GND
V
DDQ
Q35
Q32
Q29
Q26
Q34
Q31
Q28
Q25
M
N
P
R
T
Q33
Q30
Q27
D29
D26
GND
GND
GND
GND
Q2
GND
Q3
GND
Q8
D21
D19
D23
D13
GND
D10
D11
GND
D5
GND
D4
GND
D1
GND
TMS
GND
TDO
TDI
GND
Q0
GND
Q11
Q24
Q14
Q15
Q23
Q21
Q22
Q20
Q19
U
V
D18
D14
D7
D8
D2
Q1
Q6
Q5
Q9
Q12
Q18
TRST
V
CC
D16
D15
D0
ERCLK
Q4
Q7
Q10
Q13
Q17
V
DDQ
D12
D9
D6
D3
TCK
GND
Q16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5907 drw02A
IDT72T36105/72T36115/72T36125Only
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)
TOP VIEW
3
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
DESCRIPTION:
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are exceptionally deep, extrememly high
speed,CMOSFirst-In-First-Out(FIFO)memorieswithclockedreadandwrite
controlsandaflexibleBus-Matchingx36/x18/x9dataflow.TheseFIFOsoffer
severalkeyuserbenefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• AuserselectableMARKlocationforretransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translationonthereadorwriteports
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Highdensityofferingsupto9Mbit
Bus-MatchingTeraSyncFIFOs are particularlyappropriate fornetwork,
video,telecommunications,datacommunicationsandotherapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera36-bit, 18-bitora9-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe
tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.
Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation,
thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.
AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.
AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized
tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.Theseareoutputs fromthereadportoftheFIFOthatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respect to EREN and ERCLK, this is very useful when data is being read at
highspeed.TheERCLKandERENoutputsarenon-functionalwhentheRead
portissetupforAsynchronousmode.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
4
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
andD32,D33,D34andD35areignored. IPmodeisselectedduring Master
ResetbythestateoftheIPinputpin.
DESCRIPTION (CONTINUED)
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect
totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any
subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto
this‘marked’location.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedanceorLOWimpedance.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
BoundaryScanArchitecture.
TheTeraSyncFIFOhas thecapabilityofoperatingits ports (writeand/or
read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe
other.ThewriteportselectionismadeviaWHSTLandthereadportselection
via RHSTL. AnadditionalinputSHSTLis alsoprovided, this allows the user
toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe
write or read ports).
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Paritymode is selected, thenD8, D17andD26are assumedtobe validbits
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125arefabricatedusingIDT’shighspeedsub-
micronCMOStechnology.
5
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CHIP SELECT (WCS)
IDT
LOAD (LD)
READ CHIP SELECT (RCS)
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
(x36, x18, x9) DATA IN (D
0
- Dn)
(x36, x18, x9) DATA OUT (Q0 - Qn)
RCLK ECHO, ERCLK
REN ECHO, EREN
MARK
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5907 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x36
x36
x36
x18
x9
x36
x18
x9
x36
x36
NOTE:
1. Pin status during Master Reset.
6
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION
Symbol
Name
I/OTYPE
Description
(1)
ASYR Asynchronous
LVTTL
INPUT
AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ReadPort
(1)
ASYW Asynchronous
LVTTL
INPUT
AHIGHonthisinputduringMasterResetwillselectSynchronouswriteoperationfortheinputport.ALOW
willselectAsynchronousoperation.
WritePort
(1)
BE
Big-Endian/
Little-Endian
LVTTL
INPUT
DuringMasterReset, a LOWonBE willselectBig-Endianoperation. AHIGHon BE duringMasterReset
willselectLittle-Endianformat.
(1)
BM
Bus-Matching
LVTTL
INPUT
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
D0–D35 DataInputs
HSTL-LVTTL Datainputsfora36-,18-or9-bitbus.Whenin18-or9-bitmode,theunusedinputpinsshouldbetiedtoGND.
INPUT
EF/OR EmptyFlag/
HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
OUTPUT InFWFTmode,theORfunctionis selected.ORindicates whetherornotthereis validdataavailableatthe
outputs.
OutputReady
ERCLK RCLK Echo
HSTL-LVTTL ReadclockEchooutput, onlyavailable whenthe Readis setupforSynchronous mode.
OUTPUT
EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
Input Ready
HSTL-LVTTL Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis
OUTPUT full. Inthe FWFTmode, theIR functionis selected. IR indicates whetherornotthereis spaceavailablefor
writingtotheFIFOmemory.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
FWFT/ FirstWordFall
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
LVTTL
INPUT
HSTL-LVTTL DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,this pin
SI
Through/Serial In
Half-FullFlag
InterspersedParity
InputWidth
INPUT
functionsasaserialinputforloadingoffsetregisters.IfAsynchronousoperationofthereadporthasbeen
selectedthentheFIFOmustbeset-upinIDTStandardmode.
HF
IP(1)
HSTL-LVTTL HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
OUTPUT
LVTTL
INPUT
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode.
(1)
IW
LVTTL
INPUT
Thispin,alongwithOWandBM,selectsthebuswidthofthewriteport.SeeTable1forbussizeconfiguration.
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT
determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting
to and reading from the offset registers.THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
MARK MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit
INPUT operationwillresetthereadpointertothisposition.
MRS
MasterReset
HSTL-LVTTL MRSinitializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes.DuringMaster
INPUT
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,
Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,
serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,
interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OE
OutputEnable
OutputWidth
HSTL-LVTTL OEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn. DuringaMasterorPartialResetthe
INPUT
OEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.
(1)
OW
LVTTL
INPUT
Thispin,alongwithIWandBM,selectsthebuswidthofthereadport.SeeTable1forbussizeconfiguration.
PAE
PAF
Programmable
HSTL-LVTTL PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmpty
OUTPUT Offsetregister.PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn.
HSTL-LVTTL PAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstoredinthe
OUTPUT FullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequaltom.
Almost-EmptyFlag
Programmable
Almost-FullFlag
(1)
PFM
Programmable
Flag Mode
LVTTL DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon
INPUT
PFMwillselectSynchronousProgrammableflagtimingmode.
7
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
Description
PRS
PartialReset
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings
are allretained.
Q0–Q35 DataOutputs
RCLK/ ReadClock/
HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not
OUTPUT be connected.Outputsarenot5VtolerantregardlessofthestateofOEandRCS.
HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,whenenabledbyREN,therisingedgeofRCLK
RD
ReadStobe
INPUT
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevalues
loadedintotheoffsetregistersisoutputonarisingedgeofRCLK.IfAsynchronousoperationoftheread
port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN
shouldbetiedLOW.
RCS
REN
ReadChipSelect HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterResetorPartialResettheRCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance
regardless ofRCS.
ReadEnable
HSTL-LVTTL IfSynchronous operationofthereadporthas beenselected,RENenablesRCLKforreadingdatafromthe
INPUT
FIFOmemoryandoffsetregisters.IfAsynchronousoperationofthereadporthasbeenselected,theREN
inputshouldbetiedLOW.
(1)
RHSTL Read Port HSTL
Select
LVTTL
INPUT
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
required,thisinputmustbetiedHIGH.OtherwiseitshouldbetiedLOW.
RT
Retransmit
HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializestheREADpointertozero,setstheEFflagtoLOW(ORto
INPUT
HIGHinFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtimingmode
orprogrammableflagsettings.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwilljump
tothe‘mark’location.
SCLK SerialClock
SEN SerialEnable
HSTL-LVTTL ArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovidingthat
INPUT SEN is enabled.
HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL SystemHSTL
Select
LVTTL
INPUT
AllinputsnotassociatedwiththewriteorreadportcanbeselectedforHSTLoperationviatheSHSTLinput.
(2)
TCK
JTAGClock
HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperations
INPUT
ofthedevicearesynchronous toTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKand
outputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneedstobetiedtoGND.
(2)
TDI
JTAGTestData
Input
HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
INPUT
testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister
andBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
OUTPUT testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,ID
RegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whileinSHIFT-DRand
SHIFT-IRcontrollerstates.
TMS(2) JTAGMode
Select
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
INPUT
thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST JTAGReset
HSTL-LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT
resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAG
functionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetiedwithMRStoensureproper
FIFOoperation.IftheJTAGfunctionis notusedthenthis signalneeds tobetiedtoGND.
WEN
WCS
WriteEnable
HSTL-LVTTL WhenSynchronousoperationofthewriteporthasbeenselected,WENenablesWCLKforwritingdatainto
INPUT
theFIFOmemoryandoffsetregisters.IfAsynchronousoperationofthewriteporthasbeenselected,the
WENinputshouldbetiedLOW.
WriteChipSelect HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WCLK/ WriteClock/
WR WriteStrobe
HSTL-LVTTL IfSynchronousoperationofthewriteporthasbeenselected,whenenabledbyWEN,therisingedgeofWCLK
INPUT
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdatainto
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
8
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
Description
(1)
WHSTL WritePortHSTL
Select
LVTTL
INPUT
ThispinisusedtoselectHSTLor2.5VLVTTLinputsfortheFIFO.IfHSTLinputsarerequired,thisinputmust
betiedHIGH.OtherwiseitshouldbetiedLOW.
Vcc
GND
Vref
+2.5v Supply
GroundPin
Reference
Voltage
I
I
I
These are Vccsupplyinputs andmustbe connectedtothe 2.5Vsupplyrail.
These are Ground pins an dmust be connected to the GND rail.
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable,
“RecommendedDCOperatingConditions”.This provides thereferencevoltagewhenusingHSTLclass
inputs.IfHSTLclass inputs arenotbeingused,this pinshouldbetiedLOW.
VDDQ
O/PRailVoltage
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 31-34 and Figures 6-8.
9
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions
Max.
Unit
Symbol
Rating
Commercial
Unit
Symbol
VTERM
TerminalVoltage
with respect to GND
–0.5to+3.6(2)
V
(2,3)
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
(1,2)
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
COUT
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
VCC
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
VDDQ+0.3
VDDQ+0.3
V
V
V
VIL
InputLowVoltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
-0.3
-0.3
-0.3
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF(1)
TA
VoltageReferenceInput ⎯ eHSTL
⎯ HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
TA
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
10
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
ILI
Parameter
Min.
–10
Max.
10
Unit
µA
µA
V
V
V
InputLeakageCurrent
ILO
OutputLeakageCurrent
OutputLogic“1”Voltage,
–10
10
(5)
VOH
IOH = –8 mA @VDDQ = 2.5V 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V 0.1V (eHSTL)
IOH = –8 mA @VDDQ = 1.5V 0.1V (HSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
VOL
OutputLogic“0”Voltage,
IOL = 8 mA @VDDQ = 2.5V 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V 0.1V (eHSTL)
IOL = 8 mA @VDDQ = 1.5V 0.1V (HSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
40
70
70
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
10
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
IDT72T36105/72T36115/72T36125
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
60
90
90
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
20
70
70
mA
mA
mA
I/O = HSTL
I/O = eHSTL
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. For the IDT72T36105/72T36115/72T36125, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 1.3 x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.3 x fs), fs = WCLK = RCLK frequency (in MHz)
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).
3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)
with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,
N = Number of outputs switching.
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
11
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS(1)—SYNCHRONOUSTIMING
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
Commercial
IDT72T3645L6-7
IDT72T3655L6-7
IDT72T3665L6-7
IDT72T3675L6-7
IDT72T3685L6-7
IDT72T3695L6-7
IDT72T3645L4-4
IDT72T3655L4-4
IDT72T3665L4-4
IDT72T3675L4-4
IDT72T3685L4-4
IDT72T3695L4-4
IDT72T3645L5
IDT72T3655L5
IDT72T3665L5
IDT72T3675L5
IDT72T3685L5
IDT72T3695L5
IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10
IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10
IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10
Symbol
fC
Parameter
Clock Cycle Frequency (Synchronous)
DataAccessTime
Min.
—
0.6
4.44
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
Max.
225
3.4
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
5
Max.
200
3.6
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
Max.
150
3.8
—
—
—
—
—
—
—
—
—
—
—
10
Min.
Max.
100
4.5
—
—
—
—
—
—
—
—
—
—
—
10
Unit
MHz
ns
tA
0.6
10
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
tCLK
Clock Cycle Time
ns
tCLKH
tCLKL
tDS
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
ns
Clock Low Time
ns
DataSetupTime
ns
tDH
DataHoldTime
ns
tENS
EnableSetupTime
ns
tENH
tLDS
EnableHoldTime
ns
LoadSetupTime
ns
tLDH
LoadHoldTime
ns
tWCSS
tWCSH
fS
WCSsetuptime
WCSholdtime
Clock Cycle Frequency (SCLK)
ns
ns
MHz
ns
tSCLK
tSCKH
tSCKL
tSDS
Serial Clock Cycle
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
15
Serial Clock High
ns
Serial Clock Low
45
45
ns
SerialDataInSetup
15
15
ns
tSDH
tSENS
tSENH
tRS
Serial Data In Hold
5
5
ns
SerialEnableSetup
5
5
5
5
ns
SerialEnableHold
ResetPulseWidth(2)
5
5
5
5
ns
30
30
15
4
30
30
15
4
ns
tRSS
ResetSetupTime
15
15
ns
tHRSS
tRSR
HSTLResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
Write Clock to FF or IR
Read Clock to EF or OR
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
RCLK to Echo RCLK output
RCLK to Echo REN output
4
4
µs
ns
10
10
—
—
—
—
—
—
—
—
—
4
10
10
—
—
—
—
—
—
—
—
—
7
tRSF
—
—
—
—
—
—
—
—
—
3.5
4
—
—
—
—
—
—
—
—
—
5
ns
tWFF
tREF
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
—
—
3.6
3.6
3.6
3.6
4
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
4.5
4.5
4.5
4.5
5
ns
ns
tPAFS
tPAES
tERCLK
tCLKEN
tRCSLZ
ns
ns
ns
3.6
3.6
3.6
—
—
4.5
4.5
4.5
—
—
ns
(3)
RCLK to Active from High-Z
ns
(3)
tRCSHZ RCLK to High-Z
ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF
ns
5
6
8
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
12
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS—ASYNCHRONOUSTIMING
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
Commercial
IDT72T3645L6-7
IDT72T3655L6-7
IDT72T3665L6-7
IDT72T3675L6-7
IDT72T3685L6-7
IDT72T3695L6-7
IDT72T3645L4-4
IDT72T3655L4-4
IDT72T3665L4-4
IDT72T3675L4-4
IDT72T3685L4-4
IDT72T3695L4-4
IDT72T3645L5
IDT72T3655L5
IDT72T3665L5
IDT72T3675L5
IDT72T3685L5
IDT72T3695L5
IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10
IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10
IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10
Symbol
fA
Parameter
Cycle Frequency (Asynchronous)
DataAccessTime
Min.
—
0.6
10
Max.
100
8
Min.
—
0.6
12
5
Max.
83
Min.
—
0.6
15
7
Max.
66
Min.
—
0.6
20
8
Max. Unit
50
14
—
—
—
—
14
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
10
12
tCYC
tCYH
tCYL
tRPE
tFFA
tEFA
tPAFA
tPAEA
tOLZ
tOE
Cycle Time
—
—
—
—
8
—
—
—
—
10
—
—
—
—
12
Cycle HIGH Time
4.5
4.5
8
Cycle LOW Time
5
7
8
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
10
—
—
—
—
0
12
—
—
—
—
0
14
—
—
—
—
0
—
—
—
—
0
8
10
12
14
8
10
12
14
8
10
12
14
(1)
OutputEnabletoOutputinLowZ
—
3.4
3.4
8
—
3.6
3.6
10
—
3.8
3.8
12
—
4.5
4.5
14
OutputEnabletoOutputValid
—
—
—
—
—
—
—
—
—
—
—
—
(1)
tOHZ
tHF
OutputEnabletoOutputinHighZ
Clock to HF
NOTES:
1. Values guaranteed by design, not currently tested.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
13
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
VDDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
50
Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
I/O
VDDQ/2
5907 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
200
Capacitance (pF)
5907 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5VLVTTL
2.5V AC TEST CONDITIONS
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
14
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
V
2
CC
Output
Normally
LOW
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
5907 drw04b
NOTES:
1. REN is HIGH.
2. RCS is LOW.
READ CHIP SELECT ENABLE & DISABLE TIMING
VIH
tENH
RCS
VIL
tENS
RCLK
tRCSHZ
tRCSLZ
Output
Normally
LOW
VCC
2
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
5907 drw04c
NOTES:
1. REN is HIGH.
2. OE is LOW.
15
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
writesfortheIDT72T36125,respectively.
FUNCTIONALDESCRIPTION
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
TheIDT72T3645/55/65/75/85/95/105/115/125supporttwodifferenttim-
ing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT)mode.Theselectionofwhichmodewilloperateisdeterminedduring
MasterReset,bythestateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornot
thereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction(FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whetherornottheFIFOhasanyfreespaceforwriting.IntheFWFTmode,the
firstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges, REN=LOWis notnecessary.Subsequentwords mustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.Thedefaultsettingforthesevalues arestatedinthefootnoteof
Table2.Thisparameterisalsouserprogrammable.SeesectiononProgram-
mableFlagOffsetLoading.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe514thword
fortheIDT72T3645,1,026thwordfortheIDT72T3655,2,050thwordforthe
IDT72T3665, 4,098th word for the IDT72T3675, 8,194th word for the
IDT72T3685, 16,386th word for the IDT72T3695, 32,770th word for the
IDT72T36105, 65,538thwordforthe IDT72T36115and131,074thwordfor
theIDT72T36125,respectivelywaswrittenintotheFIFO.Continuingtowrite
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will goLOW after (1,025-m) writes for the IDT72T3645,
(2,049-m) writes for the IDT72T3655, (4,097-m) writes for the IDT72T3665
and(8,193-m)writesfortheIDT72T3675,(16,385-m)writesfortheIDT72T3685,
(32,769-m)writesfortheIDT72T3695,(65,537-m)writesfortheIDT72T36105,
(131,073-m) writes for the IDT72T36115 and (262,145-m) writes for the
IDT72T36125,wheremisthefulloffsetvalue.Thedefaultsettingforthesevalues
arestatedinthefootnoteofTable2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
D writes to the FIFO. D = 1,025 writes for the IDT72T3645, 2,049 writes for
the IDT72T3655, 4,097 writes for the IDT72T3665 and 8,193 writes for the
IDT72T3675,16,385 writes for the IDT72T3685, 32,769 writes for the
IDT72T3695, 65,537 writes for the IDT72T36105, 131,073 writes for the
IDT72T36115 and 262,145 writes for the IDT72T36125, respectively. Note
thattheadditionalwordinFWFTmodeisduetothecapacityofthememoryplus
outputregister.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the513rdwordforIDT72T3645,1,025thwordforIDT72T3655,2,049thword
for IDT72T3665, 4,097th word for IDT72T3675, 8,193th word for the
IDT72T3685, 16,385th word for the IDT72T3695, 32,769th word for the
IDT72T36105, 65,537thwordforthe IDT72T36115and131,073rdwordfor
theIDT72T36125,respectivelywaswrittenintotheFIFO.Continuingtowrite
dataintotheFIFOwillcausetheProgrammableAlmost-Fullflag(PAF)togo
LOW.Again,ifnoreadsareperformed,thePAFwillgoLOWafter(1,024-m)
writes fortheIDT72T3645,(2,048-m)writes fortheIDT72T3655,(4,096-m)
writesfortheIDT72T3665,(8,192-m)writesfortheIDT72T3675,(16,384-m)
writesfortheIDT72T3685,(32,768-m)writesfortheIDT72T3695,(65,536-m)
writes for the IDT72T36105, (131,072-m) writes for the IDT72T36115 and
(262,144-m)writesfortheIDT72T36125.Theoffset“m”isthefulloffsetvalue.
ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 1,024 writes for the IDT72T3645, 2,048 writes for the
IDT72T3655,4,096writesfortheIDT72T3665,8,192writesfortheIDT72T3675,
16,384writesfortheIDT72T3685,32,768writesfortheIDT72T3695, 65,536
writesfortheIDT72T36105,131,072writesfortheIDT72T36115and262,144
Relevanttimingdiagrams forFWFTmodecanbefoundinFigure14,15,
16 and 19.
16
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS
TABLE 2 — DEFAULT PROGRAMMABLE
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125haveinternalregistersfortheseoffsets.Thereareeightdefaultoffset
valuesselectableduringMasterReset.TheseoffsetvaluesareshowninTable
2.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwoways;serial
orparallelloadingmethod.Theselectionoftheloadingmethodisdoneusing
theLD(Load)pin.DuringMasterReset,thestateoftheLDinputdetermines
whetherserialorparallelflagoffsetprogrammingis enabled.AHIGHonLD
duringMasterResetselectsserialloadingofoffsetvalues.ALOWonLDduring
MasterResetselectsparallelloadingofoffsetvalues.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
FLAG OFFSETS
IDT72T3645, 72T3655
*LD
L
L
L
L
H
H
H
H
FSEL1
FSEL0
Offsets n,m
H
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
511
255
127
63
31
15
7
3
*LD
H
FSEL1
FSEL0
Program Mode
(3)
X
X
Serial
(4)
L
X
X
Parallel
IDT72T3665,72T3675,72T3685,72T3695, 72T36105,
72T36115, 72T36125
The offsetregisters maybe programmed(andreprogrammed)anytime
afterMasterReset,regardlessofwhetherserialorparallelprogramminghas
beenselected. Validprogrammingranges are from0toD-1.
*LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
L
H
L
L
L
H
L
H
L
H
H
1,023
511
255
127
63
31
15
7
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125canbeconfiguredduringtheMasterReset
cyclewitheithersynchronousorasynchronoustimingforPAFandPAEflags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK.Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure23forsynchronous
PAFtimingandFigure24forsynchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure25forasynchronousPAFtimingandFigure26forasynchronousPAE
timing.
L
L
H
H
L
H
H
H
H
*LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
(4)
Parallel
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
17
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IDT72T3675
IDT72T3685
FF PAF
PAE EF
HF
IDT72T3645
IDT72T3655
IDT72T3665
0
H
H
H
L
L
L
0
0
0
0
H
H
H
H
H
H
H
H
L
1 to n (1)
1 to n (1)
1 to n(1)
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
L
H
H
H
H
H
(n+1) to 1,024
(n+1) to 512
(n+1) to 2,048
H
H
H
H
(n+1) to 4,096
4,097 to (8,192-(m+1))
(n+1) to 8,192
8,193 to (16,384-(m+1))
513 to (1,024-(m+1))
1,025 to (2048-(m+1))
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
(1024-m)
to 1,023
(2048-m)
to 2,047
(8,192-m)
to 8,191
to 16,383
H
L
L
(16,384-m)
L
1,024
2,048
L
8,192
16,384
IDT72T36115
IDT72T36125
FF PAF
PAE EF
IDT72T36105
HF
IDT72T3695
0
0
H
H
H
L
L
L
L
0
0
H
H
H
H
H
H
H
H
L
1 to n (1)
1 to n(1)
1 to n (1)
(1)
Number of
Words in
FIFO
1 to n
H
H
H
H
H
(n+1) to 32,768
(n+1) to 16,384
(n+1) to 65,536
H
H
H
H
(n+1) to 131,072
131,073 to (262,144-(m+1))
(262,144-m) to 262,143
262,144
32,769 to (65,536-(m+1))
16,385 to (32,768-(m+1))
65,537 to (131,072-(m+1))
(32,768-m) to 32,767
32,768
(65,536-m) to 65,535
65,536
H
L
L
(131,072-m) to 131,071
131,072
L
L
NOTE:
1. See table 2 for values for n, m.
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
IDT72T3685
HF
PAE OR
IDT72T3675
IR PAF
IDT72T3645
IDT72T3655
IDT72T3665
0
0
0
0
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
0
1 to n+1
1 to n+1
Number of
Words in
FIFO
1 to n+1
1 to n+1
1 to n+1
(n+2) to 1,025
(n+2) to 2,049
(n+2) to 4,097
(n+2) to 8,193
H
H
L
(n+2) to 513
L
514 to (1,025-(m+1))
2,050 to (4,097-(m+1))
8,194 to (16,385-(m+1))
to 16,384
1,026 to (2,049-(m+1))
(2,049-m) to 2,048
2,049
4,098 to (8,193-(m+1))
L
L
H
H
L
L
L
L
(1,025-m)
to 4,096
to 8,192
to 1,024
(16,385-m)
16,385
(4,097-m)
(8,193-m)
1,025
4,097
8,193
IDT72T36115
IDT72T36125
HF
PAE OR
IDT72T3695
IR PAF
IDT72T36105
0
0
0
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
0
Number of
Words in
FIFO
1 to n+1
1 to n+1
1 to n+1
1 to n+1
H
H
L
(n+2) to 32,769
32,770 to (65,537-(m+1))
(n+2) to 16,385
(n+2) to 65,537
(n+2) to 131,073
131,074 to (262,145-(m+1))
(262,145-m) to 262,144
262,145
L
65,538 to (131,073-(m+1))
16,386 to (32,769-(m+1))
L
L
H
H
L
L
L
L
(32,769-m)
to 32,768
(65,537-m) to 65,536
65,537
(131,073-m) to 131,072
131,073
32,769
5907 drw05
NOTE:
1. See table 2 for values for n, m.
18
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645, IDT72T3655
IDT72T3665, IDT72T3675
IDT72T3685, IDT72T3695
IDT72T36105, IDT72T36115
IDT72T36125
WCLK RCLK
SCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
0
1
1
0
X
Full Offset (MSB)
Serial shift into registers:
X
X
20 bits for the IDT72T3645
22 bits for the IDT72T3655
24 bits for the IDT72T3665
26 bits for the IDT72T3675
28 bits for the IDT72T3685
30 bits for the IDT72T3695
32 bits for the IDT72T36105
34 bits for the IDT72T36115
36 bits for the IDT72T36125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
X
1
1
1
No Operation
Write Memory
X
1
1
1
0
X
1
X
0
1
X
X
X
X
X
X
X
Read Memory
X
No Operation
5907 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
19
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
18
15 14
14
9
17 16
16 15
13 12 11 10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
# of Bits Used:
Interspersed
Parity
18 17
13 12 11 10 9
10 bits for the IDT72T3645
11 bits for the IDT72T3655
12 bits for the IDT72T3665
13 bits for the IDT72T3675
14 bits for the IDT72T3685
15 bits for the IDT72T3695
16 bits for the IDT72T36105
17 bits for the IDT72T36115
18 bits for the IDT72T36125
Note: All unused bits of the
LSB & MSB are don’t care
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
15 14
14
9
18 17 16
15
13 12 11 10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
Interspersed
Parity
17
13 12 11 10 9
18
16
# of Bits Used
IDT72T3645/55/65/75/85/95/105/115/125 ⎯ x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
1st Parallel Offset Write/Read Cycle
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
D/Q17
Data Inputs/Outputs
4
4
3
3
2
2
1
1
16 15 14 13 12 11 10
15 14 11
9
8
8
7
7
6
6
5
5
D/Q0
D/Q16
Interspersed
Parity
9
10
16
13 12
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
D/Q8
# of Bits Used
16 15 14 13 1211 10
13 12 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2nd Parallel Offset Write/Read Cycle
16
Interspersed
Parity
15 14
11
9
D/Q17
D/Q8
D/Q16
# of Bits Used
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (MSB) REGISTER (PAE)
18
18
17
17
2nd Parallel Offset Write/Read Cycle
D/Q17
3rd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14
12 11
13
14 13 12 11 10
10
9
9
8
7
7
6
6
5
5
4
4
3
2
2
1
16 15 14
12 11
13
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
16 15
1
8
3
16 15
14 13 12 11 10
D/Q8
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (MSB) REGISTER (PAF)
18 17
18 17
IDT72T3645/55/65/75/85/95/105 ⎯ x18 Bus Width
IDT72T36115/72T36125 ⎯ x18 Bus Width
1st Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
1
D/Q0
1
D/Q8
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
8
8
7
6
5
4
3
2
10
2
7
6
5
4
3
2
10
18
2
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
EMPTY OFFSET REGISTER (PAE)
2nd Parallel Offset Write/Read Cycle
D/Q8
15 13
16
14
12
11
D/Q0
9
EMPTY OFFSET REGISTER (PAE)
15 13
3rd Parallel Offset Write/Read Cycle
D/Q8
16
14
12
11
D/Q0
17
EMPTY OFFSET REGISTER (PAE)
3rd Parallel Offset Write/Read Cycle
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
1
D/Q0
1
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
8
7
6
4
3
5
8
7
6
4
3
5
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
FULL OFFSET REGISTER (PAF)
4th Parallel Offset Write/Read Cycle
D/Q8
15 13
16
14
12
11
10
D/Q0
9
FULL OFFSET REGISTER (PAF)
6th Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
17
FULL OFFSET REGISTER (PAF)
18
IDT72T3645/55/65/75/85/95/105 ⎯ x9 Bus Width
IDT72T36115/72T36125 ⎯ x9 Bus Width
5907 drw07
NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
20
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
the2nd LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewritteninto
rd
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then theEmptyOffsetRegisterMSB.Uponthe3 LOW-to-HIGHtransitionofWCLK
th
programmingofPAEandPAFvaluescanbeachievedbyusingacombination dataontheinputsDnarewrittenintotheFullOffsetRegisterLSB.Uponthe4
oftheLD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheFull
th
asfollows:whenLDandSENaresetLOW,dataontheSIinputarewritten,one OffsetRegisterMSB.The5 LOW-to-HIGHtransitionofWCLKdataontheinputs
bitforeachSCLKrisingedge,startingwiththeEmptyOffsetLSBandending DnareonceagainwrittenintotheEmptyOffsetRegisterLSB.
withtheFullOffsetMSB.Atotalof20bits fortheIDT72T3645,22bits forthe
IDT72T3655,24bitsfortheIDT72T3665,26bitsfortheIDT72T3675,28bits
When a 9 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
fortheIDT72T3685,30bitsfortheIDT72T3695,32bitsfortheIDT72T36105, 72T36105,4enabledwritecyclesarerequiredtoloadtheoffsetregisters,(2
34bitsfortheIDT72T36115and36bitsfortheIDT72T36125.SeeFigure20, peroffset).DataontheinputsDnarewrittenintotheEmptyOffsetRegisterLSB
SerialLoadingofProgrammableFlagRegisters,forthetimingdiagramforthis on the first LOW-to-HIGH transition of WCLK. Upon the 2nd LOW-to-HIGH
mode.
transitionofWCLKdataontheinputsDnarewrittenintotheEmptyOffsetRegister
Using the serial method, individual registers cannot be programmed MSB.Uponthe3rd LOW-to-HIGHtransitionofWCLKdataontheinputsDnare
selectively.PAEandPAFcanshowavalidstatusonlyafterthecompleteset writtenintotheFullOffsetRegisterLSB.Uponthe4th LOW-to-HIGHtransition
of bits (for all offset registers) has been entered. The registers can be ofWCLKdataontheinputsDnarewrittenintotheFullOffsetRegisterMSB.The
th
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When 5 LOW-to-HIGHtransitionofWCLKdataontheinputsDnareonceagainwritten
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
intotheEmptyOffsetRegisterLSB.
Write operations to the FIFO are allowed before and during the serial
Forthe IDT72T36115/72T36125, 6enabledwrite cycles are requiredto
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot loadtheoffsetregisters,(3peroffset).DataontheinputsDnarewrittenintothe
havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand EmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Upon
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia the3rd LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewritteninto
th
DnbytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored theEmptyOffsetRegisterMSB.Uponthe4 LOW-to-HIGHtransitionofWCLK
th
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan dataontheinputsDnarewrittenintotheFullOffsetRegisterLSB.Uponthe6
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheFull
th
anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN OffsetRegisterMSB.The7 LOW-to-HIGHtransitionofWCLKdataontheinputs
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
DnareonceagainwrittenintotheEmptyOffsetRegisterLSB.SeeFigure3,
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag ProgrammableFlagOffsetProgrammingSequence.SeeFigure21,Parallel
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen LoadingofProgrammableFlagRegisters,forthetimingdiagramforthismode.
written. MeasuringfromtherisingSCLKedgethatachievestheabovecriteria;
PAFwillbevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalid pointer. The act of reading offsets employs a dedicated read offset register
afterthe nextthree risingRCLKedges plus tPAE. pointer.Thetwopointersoperateindependently;however,areadandawrite
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn. shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
PARALLELMODE
noeffectonthepositionofthesepointers.
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
Write operations to the FIFO are allowed before and during the parallel
programmingofPAEandPAFvaluescanbeachievedbyusingacombination programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten
proceedsasfollows: LDandWENmustbesetLOW.Whenprogrammingthe andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO
OffsetRegistersoftheTeraSyncFIFO’sthenumberofprogrammingcycleswill memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister
be based on the bus width, the following rules apply:
insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
When a 36 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/ togglingWEN.
72T36105/72T36115/72T36125, 2 enabled write cycles are required to
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
programtheoffsetregisters,(1peroffset).DataontheinputsDnarewritteninto during the programming process. From the time parallel programming has
theEmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionofWCLK.Upon begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
thesecondLOW-to-HIGHtransitionofWCLK,dataarewrittenintotheFullOffset wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
Register.ThethirdtransitionofWCLKwrites,onceagain,totheEmptyOffset therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
Register.
When an 18 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
72T36105,2enabledwritecyclesarerequiredtoprogramtheoffsetregisters, registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
(1peroffset).DataontheinputsDnarewrittenintotheEmptyOffsetRegister pins when LD is set LOW and REN is set LOW. It is important to note that
onthefirstLOW-to-HIGHtransitionofWCLK.UponthesecondLOW-to-HIGH consecutivereadsoftheoffsetregistersisnotpermitted.Thereadoperationmust
transition of WCLK, data are written into the Full Offset Register. The third be disabled for a minimum of one RCLK cycle in between offset register
transitionofWCLKwrites,onceagain,totheEmptyOffsetRegister.
accesses. When reading the Offset Registers of the TeraSync FIFO’s the
Forthe IDT72T36115/72T36125, 4enabledwrite cycles are requiredto number of reading cycles will be based on the bus width, the following rules
loadtheoffsetregisters,(2peroffset).DataontheinputsDnarewrittenintothe apply:
EmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Upon
21
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
When a 36 bit output bus width is used:
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/ writeoperationsfromover-writingretransmitdata.Theretransmitdatacanbe
72T36105/72T36115/72T36125,2enabledreadcyclesarerequiredtoread readrepeatedlyanynumberoftimesfromthe‘marked’position.TheFIFOcan
theoffsetregisters,(1peroffset).DataontheoutputsQnarereadfromtheEmpty betakenoutofretransmitmodeatanytimetoallownormaldeviceoperation.
OffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.Uponthesecond The‘mark’positioncanbeselectedanynumberoftimes,eachselectionover-
LOW-to-HIGHtransitionofRCLK,dataarereadfromtheFullOffsetRegister. writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT
ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffsetRegister. standardandFWFTmodes.
When an 18 bit output bus width is used:
DuringIDTstandardmodetheFIFOisputintoretransmitmodebyaLow-
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/ to-HightransitiononRCLKwhenthe‘MARK’inputis HIGHandEFis HIGH.
72T36105,2enabledreadcyclesarerequiredtoreadtheoffsetregisters,(1 TherisingRCLKedge‘marks’thedatapresentintheFIFOoutputregisteras
peroffset).DataontheoutputsQnarereadfromtheEmptyOffsetRegisteron thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge
the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH on RCLK occurs while MARK is LOW.
transitionofRCLK,dataarereadfromtheFullOffsetRegister.Thethirdtransition
ofRCLKreads,onceagain,fromtheEmptyOffsetRegister.
Oncea‘marked’locationhasbeenset(andthedeviceisstillinretransmit
mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingedgeonRCLK
For the IDT72T36115/72T36125, 4 enabled read cycles are required to whiletheretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)
readtheoffsetregisters,(2peroffset).DataontheoutputsQnarereadfrom beforebringingRTLOW.Thedeviceindicatesthestartofretransmitsetupby
theEmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofRCLK. settingEFLOW,alsopreventingreads.WhenEFgoesHIGH,retransmitsetup
Uponthe2nd LOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread iscompleteandreadoperationsmaybeginstartingwiththefirstdataattheMARK
fromtheEmptyOffsetRegisterMSB.Uponthe3rd LOW-to-HIGHtransitionof location.SinceIDTstandardmodeisselected,everywordreadincludingthe
RCLKdataontheoutputsQnarereadfromtheFullOffsetRegisterLSB.Upon first‘marked’wordfollowingaretransmitsetuprequiresaLOWonREN(read
th
the4 LOW-to-HIGHtransitionofRCLKdataontheoutputsQnarereadfrom enabled).
th
theFullOffsetRegisterMSB.The5 LOW-to-HIGHtransitionofRCLKdataon
theoutputsQnareonceagainreadfromtheEmptyOffsetRegisterLSB.
When a 9 bit output bus width is used:
Note, write operations may continue as normal during all retransmit
functions,howeverwriteoperationstothe‘marked’locationwillbeprevented.
See Figure 18,RetransmitfromMark(IDTstandardmode), forthe relevant
For the IDT72T36115/72T36125, 4 enabled read cycles are required to timingdiagram.
readtheoffsetregisters,(2peroffset).DataontheoutputsQnarereadfrom
DuringFWFTmodetheFIFOisputintoretransmitmodebyarisingRCLK
theEmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofRCLK. edgewhenthe‘MARK’inputisHIGHandORisLOW.TherisingRCLKedge
Uponthe2nd LOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread ‘marks’thedatapresentintheFIFOoutputregisterasthefirstretransmitdata.
fromtheEmptyOffsetRegisterMSB.Uponthe3rd LOW-to-HIGHtransitionof TheFIFOremains inretransmitmodeuntilarisingRCLKedgeoccurs while
RCLKdataontheoutputsQnarereadfromtheFullOffsetRegisterLSB.Upon MARKisLOW.
th
the4 LOW-to-HIGHtransitionofRCLKdataontheoutputsQnarereadfrom
Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmit
th
theFullOffsetRegisterMSB.The5 LOW-to-HIGHtransitionofRCLKdataon mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhile
theoutputsQnareonceagainreadfromtheEmptyOffsetRegisterLSB. theretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)before
For the IDT72T36115/72T36125, 6 enabled read cycles are required to bringingRTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting
readtheoffsetregisters,(3peroffset).DataontheoutputsQnarereadfrom OR HIGH.
theEmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofRCLK.
WhenORgoesLOW,retransmitsetupiscompleteandonthenextrising
Uponthe3rd LOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread RCLKedgeafterretransmitsetupiscomplete,(RTgoesHIGH),thecontents
th
fromtheEmptyOffsetRegisterMSB.Uponthe4 LOW-to-HIGHtransitionof ofthefirstretransmitlocationareloadedontotheoutputregister.SinceFWFT
RCLKdataontheoutputsQnarereadfromtheFullOffsetRegisterLSB.Upon modeisselected,thefirstwordappearsontheoutputsregardlessofREN,a
th
the6 LOW-to-HIGHtransitionofRCLKdataontheoutputsQnarereadfrom LOWonRENisnotrequiredforthefirstword.Readingallsubsequentwords
th
theFullOffsetRegisterMSB.The7 LOW-to-HIGHtransitionofRCLKdataon requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
theoutputsQnareonceagainreadfromtheEmptyOffsetRegisterLSB.See RetransmitfromMarktiming(FWFTmode),fortherelevanttimingdiagram.
Figure 3, Programmable Flag Offset Programming Sequence. See Figure
Note,theremustbeaminimumof32bytesofdatabetweenthewritepointer
22, ParallelReadofProgrammableFlagRegisters,forthetimingdiagramfor and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words).Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe
“marked”locationuntiltheMARKisdeasserted.Thisprevents“overwriting”
ofretransmitdata.
thismode.
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
orbothtogether.WhenRENandLDarerestoredtoaLOW level,readingof
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
Parallelreadingofthe offsetregisters is always permittedregardless of
whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
controlpins are selectable via SHSTL, see Table 5fordetails ofgroupings.
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce
thepowerconsumption(instand-bymodebyutilizingtheWCSinput).
All“StaticPins”mustbetiedtoVCC orGND.Thesepins areLVTTLonly,
andare purelydevice configurationpins.
RETRANSMITFROMMARKOPERATION
TheRetransmitfromMarkfeatureallowsFIFOdatatobereadrepeatedly
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat
22
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 5 — I/O CONFIGURATION
WHSTL SELECT
RHSTL SELECT
SHSTL SELECT
STATIC PINS
WHSTL: HIGH = HSTL
LOW = LVTTL
RHSTL: HIGH = HSTL
LOW = LVTTL
SHSTL: HIGH = HSTL
LOW = LVTTL
LVTTL ONLY
Dn (I/P)
RCLK/RD (I/P)
RCS (I/P)
MARK (I/P)
REN (I/P)
OE (I/P)
EF/OR (O/P)
SCLK (I/P)
LD (I/P)
MRS (I/P)
TCK (I/P)
TMS (I/P)
SEN (I/P)
FWFT/SI (I/P)
PRS (I/P)
IW (I/P)
BM (I/P)
OW (I/P)
ASYW (I/P)
BE (I/P)
FSEL0 (I/P)
PFM (I/P)
WHSTL (I/P)
WCLK/WR (I/P)
WEN (I/P)
WCS (I/P)
PAF (O/P)
EREN (O/P)
PAE (O/P)
FF/IR (O/P)
HF (O/P)
TRST (I/P)
TDI (I/P)
ASYR (I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
RT (I/P)
Qn (O/P)
ERCLK (O/P)
TDO (O/P)
23
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Asynchronous operationofthereadportwillbeselected.DuringAsynchro-
nousoperationofthereadporttheRCLKinputbecomesRDinput,thisisthe
Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.(RCS,providesthree-statecontrolofthereadportin
Synchronousmode).
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
andawriteoperation.Refertofigures32,33,34and35forrelevanttimingand
operationalwaveforms.
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Datainputsfor36-bitwidedata(D0-D35),datainputsfor18-bitwidedata
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
CONTROLS:
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined
duringtheMasterResetcycle.
RETRANSMIT (RT)
The Retransmit (RT) input is used in conjunction with the MARK input,
togethertheyprovideameansbywhichdatapreviouslyreadoutoftheFIFO
canberereadanynumberoftimes.Ifretransmitoperationhasbeenselected
(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhileRTisLOWwillreset
thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.
IfIDTstandardmodehasbeenselectedtheEFflagwillgoLOWandremain
LOWforthe time thatRT is heldLOW. RT canbe heldLOWforanynumber
ofRCLKcycles,thereadpointerbeingresettothemarkedlocation.Thenext
risingedge ofRCLKafterRT has returnedHIGH, willcause EF togoHIGH,
allowingreadoperationstobeperformedontheFIFO.Thenextreadoperation
willaccessdatafromthe‘marked’memorylocation.
Subsequentretransmitoperationsmaybeperformed,eachtimetheread
pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark
(IDTStandardmode)forthe relevanttimingdiagram.
IfFWFTmodehasbeenselectedtheORflagwillgoHIGHandremainHIGH
forthetimethatRTisheldLOW.RTcanbeheldLOWforanynumberofRCLK
cycles,thereadpointerbeingresettothe‘marked’location.ThenextRCLK
risingedgeafterRThasreturnedHIGH,willcauseORtogoLOWanddueto
FWFToperation,thecontentsofthemarkedmemorylocationwillbeloadedonto
the output register, a read operation being required for all subsequent data
reads.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 9, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
Subsequentretransmitoperationsmaybeperformedeachtimetheread
pointerreturningtothe‘marked’location.SeeFigure19,RetransmitfromMark
(FWFTmode)forthe relevanttimingdiagram.
See Figure 10, PartialResetTiming, forthe relevanttimingdiagram.
MARK
ASYNCHRONOUS WRITE (ASYW)
TheMARKinputisusedtoselectRetransmitmodeofoperation.AnRCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmit mode. Note, for the IDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695theremustbeaminimumof32bytesofdatabetweenthe
writepointerandreadpointerwhentheMARKisasserted.FortheIDT72T36105/
72T36115 there must be a minimum of 128 bytes, for the IDT72T36125 a
minimumof256bytes.Remember,4(x9)bytes=2(x18)words=1(x36)word.
Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe“marked”
locationuntiltheMARKisdeasserted.Thisprevents“overwriting”ofretransmit
data.
TheMARKinputmustremainHIGHduringthewholeperiodofretransmit
mode,afallingedgeofRCLKwhileMARKis LOWwilltakethedeviceoutof
retransmitmodeandintonormalmode.AnynumberofMARKlocationscanbe
setduringFIFOoperation,onlythelastmarkedlocationtakingeffect.Oncea
marklocationhasbeensetthewritepointercannotbeincrementedpastthis
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchro-
nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
based in both a write operation and read operation. Note, if Asynchronous
modeis selected,FWFTis notpermissable.RefertoFigures 30,31,34and
35forrelevanttimingandoperationalwaveforms.
ASYNCHRONOUS READ (ASYR)
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
24
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
markedlocation.Duringretransmitmodewriteoperationstothedevicemay READ STROBE & READ CLOCK (RD/RCLK)
continuewithouthindrance.
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
First Word Fall Through (FWFT) mode.
the HF flag to HIGH). The Write and Read Clocks can be independent or
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode coincident.
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
If Asynchronous operation has been selected this input is RD (Read
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag Strobe) . Data is Asynchronouslyreadfromthe FIFOvia the outputregister
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace wheneverthereisarisingedgeonRD.InthismodetheRENandRCSinputs
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including mustbetiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthe
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
three-stateQnoutputs.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere WRITE CHIP SELECT (WCS)
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT performnormaloperationsonthewriteport,theWCSmustbeenabled,held
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK LOW.
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
READ ENABLE (REN)
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
When Read Enable is LOW, data is loaded from the RAM array into the
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
StandardandFWFTmodes.
maintainthepreviousdatavalue.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
wordwrittentoanemptyFIFO, mustbe requestedusingREN providedthat
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag
inputbehavesasWCLK.
(EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup FIFOisempty.Onceawriteisperformed,EFwillgoHIGHallowingareadto
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe occur. TheEFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ cycle.BothRCSandRENmustbeactive,LOWfordatatobereadoutonthe
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof rising edge of RCLK.
updating HF flag to LOW). The Write and Read Clocks can either be
independentorcoincident.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). afterthefirstwrite. RENandRCSdonotneedtobeassertedLOW fortheFirst
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere Wordtofallthroughtotheoutputregister.Inordertoaccess allotherwords,
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
a read must be executed using REN and RCS. The RCLK LOW-to-HIGH
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN=LOW;RCS=LOW),inhibiting
further read operations. REN is ignored when the FIFO is empty.
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
mustbeheldactive,(tiedLOW).
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serialprogrammingmethodmustbe selectedduringMaster
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofSCLK.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
When SEN is HIGH, the programmable registers retains the previous
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN
mustbeheldactive,(tiedLOW).
OUTPUT ENABLE (OE )
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
25
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
intoahighimpedancestate.DuringMasteroraPartialResettheOEistheonly LOAD (LD)
inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe
RCS inputcanbe HIGHorLOW, ithas noeffectonthe Qnoutputs.
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,LD
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
outputport. WhenRCSgoesLOW,thenextrisingedgeofRCLKcausesthe theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
QnoutputstogototheLow-Impedancestate. WhenRCSgoesHIGH,thenext Offsetregisters canbereadonlyinparallel.
RCLKrisingedgecausestheQnoutputstoreturntoHIGHZ.DuringaMaster
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
orPartialResettheRCSinputhasnoeffectontheQnoutputbus,OEistheonly oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.IfOEisLOWthe or parallel load or read of these offset values. THIS PIN MUST BE HIGH
QndataoutputswillbeLow-ImpedanceregardlessofRCSuntilthefirstrising AFTERMASTERRESETTOWRITEORREADDATATO/FROMTHEFIFO
edgeofRCLKafteraResetiscomplete.ThenifRCSisHIGHthedataoutputs MEMORY.
willgotoHigh-Impedance.
TheRCSinputdoesnoteffecttheoperationoftheflags. Forexample,when BUS-MATCHING (BM, IW, OW)
thefirstwordiswrittentoanemptyFIFO,theEFwillstillgofromLOWtoHIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
Also,whenoperatingtheFIFOinFWFTmodethefirstwordwrittentoan sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte
emptyFIFOwillstillbeclockedthroughtotheoutputregisterbasedonRCLK, sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure5forBus-
regardlessofthestateofRCS.Forthisreasontheusermusttakecarewhen MatchingByteArrangement.
adatawordiswrittentoanemptyFIFOinFWFTmode.IfRCSisdisabledwhen
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister, BIG-ENDIAN/LITTLE-ENDIAN ( BE )
butwillnotbeavailableontheQnoutputswhichareinHIGH-Z.Theusermust
During Master Reset, a LOW on BE will select Big-Endian operation. A
takeRCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z. HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW. isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x36to
ArisingedgeofRCLKwithRCSandREN activeLOW,willreadoutthenext x18,x36tox9,x18tox36andx9tox36.IfBig-Endianmodeisselected,then
word. Care mustbe takensoas nottolose the firstwordwrittentoanempty themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
FIFOwhenRCSisHIGH.RefertoFigure17,RCSandRENReadOperation outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO
aRetransmit. SeeFigure13forReadCycleandReadChipSelectTiming(IDT willbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
StandardMode). SeeFigure16forReadCycleandReadChipSelectTiming isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
(First Word Fall Through Mode).
Figure 5 for Bus-Matching Byte Arrangement.
IfAsynchronousoperationoftheReadporthasbeenselected,thenRCS
mustbeheldactive,(tiedLOW).OEprovidesthree-statecontrolofQn.
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
mable flagtimingmode. AHIGHonPFMwillselectSynchronous Program-
WRITE PORT HSTL SELECT (WHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport mableflagtimingmode.IfasynchronousPAF/PAEconfigurationisselected
canbesetuptobeeitherHSTLorLVTTL.IfWHSTLisHIGHduringtheMaster (PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of
atMasterReset,thenLVTTLwillbeselected.
WCLK.Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionof
TheinputsandoutputsassociatedwiththewriteportarelistedinTable5. WCLKandPAFis resettoHIGHontheLOW-to-HIGHtransitionofRCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
READ PORT HSTL SELECT (RHSTL)
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
canbesetuptobeeitherHSTLorLVTTL.IfRHSTLisHIGHduringtheMaster only and not RCLK. The mode desired is configured during master reset by
Reset,thenHSTLoperationofthereadportwillbeselected.IfRHSTLisLOW thestateoftheProgrammableFlagMode(PFM)pin.
atMasterReset,thenLVTTLwillbeselectedforthereadport,thenechoclock
and echo read enable will not be provided.
INTERSPERSED PARITY (IP)
TheinputsandoutputsassociatedwiththereadportarelistedinTable5.
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode.A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallows
theusertoselecttheparitybitinthewordloadedintotheparallelport(D0-Dn)
SYSTEM HSTL SELECT (SHSTL)
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither whenprogrammingtheflagoffsets.IfInterspersedParitymodeisselected,then
HSTLorLVTTL.IfSHSTLisHIGHduringMasterReset,thenHSTLoperation theFIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26
ofalltheinputsnotassociatedwiththewriteandreadportwillbeselected.If andD35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs Paritymodeisselected,thenD8,D17andD28areisassumedtobevalidbits
associatedwithSHSTLare listedinTable 5.
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
ResetbythestateoftheIPinputpin.
26
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36125.Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthis
valueisstatedinthefootnoteofTable3.
OUTPUTS:
FULL FLAG ( FF/IR )
In FWFT mode, the PAF will go LOW after (1,025-m) writes for the
IDT72T3645,(2,049-m)writes fortheIDT72T3655,(4,097-m)writes forthe
IDT72T3665and(8,193-m)writesfortheIDT72T3675,(16,385-m)writesfor
theIDT72T3685,(32,769-m)writesfortheIDT72T3695,(65,537-m)writesfor
theIDT72T36105,(131,073-m)writesfortheIDT72T36115and(262,145-m)
writesfortheIDT72T36125,wheremisthefulloffsetvalue.Thedefaultsetting
for this value is stated in Table 4.
SeeFigure23,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See
Figure25,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT
Mode).
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed
after a reset (eitherMRS orPRS), FF willgoLOWafterDwrites tothe FIFO
(D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the
IDT72T3665,8,192fortheIDT72T3675,16,384fortheIDT72T3685,32,768
fortheIDT72T3695,65,536fortheIDT72T36105,131,072fortheIDT72T36115
and262,144fortheIDT72T36125).SeeFigure11,WriteCycleandFullFlag
Timing(IDTStandardMode),fortherelevanttiminginformation.
InFWFTmode, the InputReady(IR)functionis selected. IRgoes LOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
totheFIFO(D = 1,025fortheIDT72T3645,2,049fortheIDT72T3655,4,097
fortheIDT72T3665,8,193fortheIDT72T3675,16,385fortheIDT72T3685,
32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the
IDT72T36115 and 262,145 for the IDT72T36125). See Figure 14, Write
Timing(FWFTMode),fortherelevanttiminginformation.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
doubleregister-bufferedoutputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
SeeFigure24, Synchronous ProgrammableAlmost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE
configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
EMPTY FLAG ( EF/OR )
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle,EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith
atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
LOWagain.SeeFigure15,ReadTiming(FWFTMode),fortherelevanttiming
information.
HALF-FULL FLAG ( HF )
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192
fortheIDT72T3675,16,384fortheIDT72T3685,32,768fortheIDT72T3695,
65,536fortheIDT72T36105,131,072fortheIDT72T36115and262,144for
the IDT72T36125.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
IDT72T3645,2,049fortheIDT72T3655,4,097fortheIDT72T3665,8,193for
the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537fortheIDT72T36105,131,073fortheIDT72T36115and262,145for
the IDT72T36125.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
WCLK,itisconsideredasynchronous.
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EF is a double register-bufferedoutput. InFWFT
mode,ORisatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(1,024-m)writesfortheIDT72T3645,
(2,048-m)writes fortheIDT72T3655,(4,096-m)writes fortheIDT72T3665,
(8,192-m)writesfortheIDT72T3675,(16,384-m)writesfortheIDT72T3685,
(32,768-m)writesfortheIDT72T3695,(65,536-m)writesfortheIDT72T36105,
(131,072-m) writes for the IDT72T36115 and (262,144-m) writes for the
27
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™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ECHO READ CLOCK (ERCLK)
ECHO READ ENABLE (EREN)
TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaRHSTL.TheERCLKisafree-runningclockoutput,itwillalways
follow the RCLK input regardless ofREN and RCS.
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaRHSTL.
The EREN output is provided to be used in conjunction with the ERCLK
outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby
internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe
RCLKcycle thata newwordis readoutofthe FIFO. Thatis, a risingedge of
RCLKwillcauseERENtogoactive,LOWifbothRENandRCSareactive,LOW
and the FIFO is NOT empty.
TheERCLKoutputfollowstheRCLKinputwithanassociateddelay. This
delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading
data from the Qn outputs. This is especially helpful at high speeds when
variableswithinthedevicemaycausechangesinthedataaccesstimes. These
variations in access time maybe caused by ambient temperature, supply
voltage,devicecharacteristics.TheERCLKoutputalsocompensatesforany
tracelengthdelaysbetweentheQndataoutputsandreceivingdevicesinputs.
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding
effectontheERCLKoutputproducedbytheFIFOdevice,thereforetheERCLK
outputleveltransitionsshouldalwaysbeatthesamepositionintimerelativeto
thedataoutputs.Note,thatERCLKisguaranteedbydesigntobeslowerthan
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
OutputRelationship,Figure28,EchoReadClock&ReadEnableOperation
and Figure 29, Echo RCLK & Echo REN Operation for timing information.
SERIAL CLOCK (SCLK)
Duringserialloadingoftheprogrammingflagoffsetregisters,arisingedge
ontheSCLKinputisusedtoloadserialdatapresentontheSIinputprovided
thattheSENinputisLOW.
DATAOUTPUTS(Q0-Qn)
(Q0-Q35)aredataoutputsfor36-bitwidedata,(Q0-Q17)aredataoutputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
RCLK
tERCLK
tERCLK
ERCLK
tD
tA
Q
SLOWEST(3)
5907 drw08
NOTES:
1. REN is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 4. Echo Read Clock and Data Output Relationship
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™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON OUTPUT PORT:
Write to FIFO
A
B
C
D
Q17-Q9
Q35-Q27
Q26-Q18
Q8-Q0
BE BM IW
OW
L
A
B
C
D
Read from FIFO
X
L
L
(a) x36 INPUT to x36 OUTPUT
Q17-Q9
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
A
B
L
H
L
Q17-Q9
Q8-Q0
C
D
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
Q17-Q9
Q35-Q27
Q26-Q18
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
H
L
Q17-Q9
Q35-Q27
Q26-Q18
Q8-Q0
A
B
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
Q17-Q9
Q35-Q27
Q26-Q18
Q8-Q0
BE BM IW
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
H
L
Q35-Q27
Q35-Q27
Q17-Q9
Q17-Q9
Q26-Q18
Q26-Q18
Q8-Q0
B
Q8-Q0
C
3rd: Read from FIFO
4th: Read from FIFO
Q35-Q27
Q17-Q9
Q26-Q18
Q8-Q0
D
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Q35-Q27
Q8-Q0
Q26-Q18
Q26-Q18
Q26-Q18
Q26-Q18
Q17-Q9
BE BM IW
OW
H
D
1st: Read from FIFO
H
H
L
Q35-Q27
Q35-Q27
Q17-Q9
Q17-Q9
Q17-Q9
Q8-Q0
C
2nd: Read from FIFO
3rd: Read from FIFO
Q8-Q0
B
Q35-Q27
Q8-Q0
A
4th: Read from FIFO
5907 drw09
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
Figure 5. Bus-Matching Byte Arrangement
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™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYTE ORDER ON INPUT PORT:
D8-D0
D35-D27
D35-D27
D26-D18
D26-D18
D17-D9
1st: Write to FIFO
2nd: Write to FIFO
A
B
D8-D0
D17-D9
C
D
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q35-Q27
Q26-Q18
Q8-Q0
BM IW
OW
L
BE
B
D
Read from FIFO
Read from FIFO
A
C
L
H
H
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
BM IW
OW
L
BE
D
B
C
A
H
H
H
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
D8-D0
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D35-D27
A
1st: Write to FIFO
2nd: Write to FIFO
D8-D0
D35-D27
D35-D27
B
D8-D0
3rd: Write to FIFO
4th: Write to FIFO
C
D35-D27
D8-D0
D
Q17-Q9
Q26-Q18
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
Q35-Q27
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
Q17-Q9
Q26-Q18
Q35-Q27
Q8-Q0
BM IW
OW
H
BE
C
A
Read from FIFO
D
B
H
H
H
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
5907 drw10
Figure 5. Bus-Matching Byte Arrangement (Continued)
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™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAGTIMINGSPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5907 drw11
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 6. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
SYSTEMINTERFACEPARAMETERS
(vcc = 2.5V 5%; Tcase = 0°C to +85°C)
IDT72T3645
IDT72T3655
IDT72T3665
IDT72T3675
IDT72T3685
IDT72T3695
IDT72T36105
IDT72T36115
IDT72T36125
Parameter
Symbol
Test
Conditions
Min. Max. Units
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
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™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T3645/72T3655/
72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125in-
corporatesthenecessarytapcontrollerandmodifiedpadcellstoimplementthe
JTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5907 drw12
Figure 7. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
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™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
Test-Logic
Reset
0
1
Select-
IR-Scan
0
1
1
Run-Test/
Idle
Select-
DR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
5907 drw13
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 8. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetails onTAPcontrollerreset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
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™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
THE INSTRUCTION REGISTER
31(MSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
28 27
12 11
1 0(LSB)
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
1
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
IDT72T3645/55/65/75/85/95/105/115/125JTAGDeviceIdentificationRegister
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
TESTDATAREGISTER
•
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16
differentpossibleinstructions. Instructionsaredecodedasfollows.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
Hex
Instruction
Function
Value
0x00
0x02
0x01
0x03
0x0F
EXTEST
IDCODE
SAMPLE/PRELOAD
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SelectBoundaryScanRegister
JTAG
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
SelectBypassRegister
JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
EXTEST
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
THE DEVICE IDENTIFICATION REGISTER
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125,thePartNumberfieldcontainsthefollowing
values:
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
Device
Part# Field
0405
IDT72T3645
IDT72T3655
IDT72T3665
IDT72T3675
IDT72T3685
IDT72T3695
IDT72T36105
IDT72T36115
IDT72T36125
0404
0403
0402
0401
0400
0416
0415
0414
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
theboundary-scanregisterbeforeloadinganEXTESTinstruction.
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™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
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™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
REN
t
RSR
RSR
t
RSS
RSS
t
t
WEN
tRSS
tRSR
FWFT/SI
tRSS
tRSR
LD
t
RSS
RSS
FSEL0,
FSEL1
t
OW,
IW, BM
t
t
t
HRSS
WHSTL
RHSTL
HRSS
HRSS
SHSTL
BE
t
RSS
RSS
RSS
t
t
PFM
IP
RT
t
RSS
RSS
t
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
PAE
t
t
RSF
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
5907 drw14
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 9. Master Reset Timing
36
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
5907 drw15
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 10. Partial Reset Timing
37
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLK
t
CLKH
t
CLKL
NO WRITE
NO WRITE
WCLK
2
1
(1)
1
(1)
2
t
SKEW1
t
DH
t
SKEW1
tDS
t
DH
tDS
DX+1
DX
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
t
ENH
tENH
REN
RCS
tENS
tA
tA
Q0
- Qn
NEXT DATA READ
DATA READ
5907 drw16
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
tOHZ
t
OLZ
tOE
OE
WCLK
WEN
t
SKEW1(1)
tENS
tENH
tENH
tENS
tWCSS
tWCSH
WCS
tDS
tDH
tDH
tDS
D0
D1
D0 - Dn
5907 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
38
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
1
RCLK
tENS
REN
RCS
tENS
tENS
tENS
tENH
tREF
tREF
EF
tRCSHZ
tRCSHZ
tA
tA
tRCSLZ
tRCSLZ
LAST DATA-1
LAST DATA
Q0 - Qn
t
SKEW1(1)
WCLK
tENS
tENH
WEN
tDS
tDH
Dn
Dx
5907 drw 18
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE is LOW.
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
39
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
40
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
41
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
42
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RNE
ERN RNE
REN ERN
RSC
CRS RSC
RCS CRS
43
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
44
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
45
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SEN
LD
tLDS
tLDS
tLDH
t
SDH
t
SDS
BIT 1
BIT X(1)
BIT X(1)
BIT 1
SI
5907 drw25
FULL OFFSET
EMPTY OFFSET
NOTE:
1. X = 10 for the IDT72T3645, X = 11 for the IDT72T3655, X = 12 for the IDT72T3665, X = 13 for the IDT72T3675, X = 14 for the IDT72T3685, X = 15 for the IDT72T3695, X = 16
for the IDT72T36105, X = 17 for the IDT72T36115 and X = 18 for the IDT72T36125.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
WCLK
LD
tLDH
tLDS
tLDH
tENH
t
ENS
tENH
WEN
t
DS
tDH
t
DH
PAF
OFFSET
PAE
OFFSET
D0 - Dn
5907 drw26
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDH
tLDH
tLDH
tLDS
tLDS
tLDS
LD
tENH
tENH
tENH
t
ENS
t
ENS
tENS
REN
t
A
t
A
tA
DATA IN OUTPUT REGISTER
PAE OFFSET VALUE
PAF OFFSET VALUE
PAE OFFSET
Q0 - Qn
5907 drw27
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
46
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
2
1
t
ENS
tENH
t
PAFS
tPAFS
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
D - (m +1) words in FIFO(2)
t
SKEW2(3)
RCLK
tENH
t
ENS
5907 drw28
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665 and 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT mode: D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
t
ENS
tENH
WEN
PAE
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
SKEW2(4)
t
PAES
t
PAES
t
1
2
1
2
RCLK
REN
t
ENS
tENH
5907 drw29
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
47
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
5907 drw30
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D=1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT Mode: D=1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
n + 1 words in FIFO
n + 2 words in FIFO
,
(3)
PAE
RCLK
REN
(3)
n + 1 words in FIFO
n + 1 words in FIFO
(3)
tPAEA
tENS
5907 drw31
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
48
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
[
+ 2]
words in FIFO(2)
D-1
2
2
D-1
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
2
tHF
RCLK
tENS
REN
5907 drw32
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the
IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the
IDT72T3685, 32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. RCS = LOW.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
49
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
50
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tENS
tENH
WEN
tDS
t
DH
tDS
t
DH
tDS
tDH
Wn+1
Wn+2
Wn+3
D0 - Dn
tSKEW1
1
2
RCLK
b
e
h
a
d
g
c
i
f
tERCLK
ERCLK
tENS
tENH
REN
RCS
tENS
tCLKEN
tCLKEN
tCLKEN
tCLKEN
EREN
Qn
tA
tA
t
RCSLZ
HIGH-Z
Wn+1
Wn+2
Wn+3
tREF
tREF
OR
tA
tA
tA
O/P
Reg.
Wn
Last Word
Wn+1
Wn+2
Wn+3
5907 drw34
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
d.
e.
f.
g.
h.
i.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
Figure 29. Echo RCLK and Echo REN Operation (FWFT Mode Only)
51
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tENS
tENH
REN
Qn
tA
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
Dn
WD
WD+1
5907 drw35
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
REN
tA
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
WR
tCYH
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
5907 drw36
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
52
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
No Write
1
WCLK
WEN
Dn
2
DF+1
tWFF
DF
tWFF
FF
tCYC
tSKEW
tAA
tCYL
tCYH
RD
Qn
tAA
Last Word
WX
WX+1
5907 drw37
NOTE:
1. OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 32. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK
WEN
Dn
tENS
tDS
tENH
tDH
W0
tEFA
EF
tEFA
tRPE
RD
tCYH
tAA
Qn
Last Word in Output Register
W0
5907 drw38
NOTE:
1. OE = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
53
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W0
W1
RD
Qn
tAA
tAA
W1
W0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
5907 drw39
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
tDS
Wy+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
5907 drw40
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
54
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™
36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
separately ANDingFF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Figure 36 demonstrates a width expansion using two IDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125devices.D0-D35fromeachdeviceforma72-bitwideinputbusand
Q0-Q35 fromeachdeviceforma 72-bitwideoutputbus.Anywordwidthcan
beattainedbyaddingadditionalIDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695/72T36105/72T36115/72T36125devices.
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
#1
FULL FLAG/INPUT READY (FF/IR)
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
FIFO
#2
m + n
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
n
FIFO
#1
Qm+1 - Qn
DATA OUT
m
5907 drw41
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72
Width Expansion
55
FEBRUARY4,2009
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
™ 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
WRITE CLOCK
READ CLOCK
READ CHIP SELECT
READ ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
RCS
REN
IDT
IDT
WRITE ENABLE
INPUT READY
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
OR
WEN
REN
RCS
OUTPUT READY
IR
OR
OE
OUTPUT ENABLE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
5907 drw42
Figure 37. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36, 262,144 x 36 and 524,288 x 36
Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T3645caneasilybe adaptedtoapplications requiringdepths
greater than 1,024, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665,
8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115
and262,144fortheIDT72T36125withan18-bitbuswidth.InFWFTmode,
theFIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnected
tothedatainputsofthenext)withnoexternallogicnecessary. Theresulting
configuration provides a total depth equivalent to the sum of the depths
associatedwitheachsingleFIFO. Figure37showsadepthexpansionusing
two IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethe
datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,
enabling a write to the next FIFO in line.
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towriteawordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
56
FEBRUARY4,2009
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type
Power
Speed Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
Plastic Ball Grid Array, PBGA BB208-1 (72T3645/55/65/75/85/95 Only)
Plastic Ball Grid Array, PBGA BB240-1 (72T36105/115/125 Only)
BB
BB
Commercial Only
Commercial and Industrial
4-4
5
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commercial Only
Commercial Only
6-7
10(3)
L
Low Power
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
2.5V TeraSync™ FIFO
72T36105 65,536 x 36
72T36115 131,072 x 36 ⎯ 2.5V TeraSync™ FIFO
72T36125 262,144 x 36 ⎯ 2.5V TeraSync™ FIFO
5907 drw43
NOTES:
1. Industrial temperature range product for 5ns speed is available as a standard device. All other speed grades are available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
3. Available for IDT72T36105/72T36115/72T36125 only.
DATASHEETDOCUMENTHISTORY
05/30/2001
07/09/2001
09/07/2001
09/11/2001
11/19/2001
11/29/2001
01/15/2002
03/04/2002
06/05/2002
02/11/2003
03/03/2003
09/02/2003
01/11/2007
02/04/2009
pgs. 17, and 18.
pgs. 1, 7, 8, 19, and 51.
pgs. 1-53.
pg. 8.
pgs. 1, 9, 12, 40, and 41.
pgs. 1, 40, and 41.
pg. 42.
pgs. 9, 10, and 29.
pgs. 9, 10, and 14.
pgs. 8, 9, and 33.
pgs. 1, 11-13, 31, and 33-35.
pgs. 7, 17, and 26.
pgs. 1, 12, 13, and 57.
pg. 57.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
57
相关型号：
72T3665L5BBG
FIFO, 4KX36, 3.6ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208
IDT
72T3665L5BBGI
FIFO, 4KX36, 3.6ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208
IDT
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