728981PG [IDT]
Digital Time Switch;
| 型号： | 728981PG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT728981
TIME SLOT INTERCHANGE
DIGITAL SWITCH
128 x 128
outputs,eachofwhichconsistsof32channels(64Kbit/sperchannel)toform
amultiplexed2.048Mb/sstream.
FEATURES:
•
•
•
•
•
•
•
•
128 x 128 channel non-blocking switch
Serial Telecom Bus Compatible (ST-BUS®)
4 RX inputs—32 channels at 64 Kbit/s per serial line
4 TX output—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
5V Power Supply
FUNCTIONALDESCRIPTION
AfunctionalblockdiagramoftheIDT728981deviceisshownbelow. The
serial streamsoperatecontinuouslyat2.048Mb/sandarearrangedin125μs
wideframeseachcontaining32,8-bitchannels. Fourinput(RX0-3)andfour
output(TX0-3)serialstreamsareprovidedintheIDT728981deviceallowing
acomplete128x128channelnon-blockingswitchmatrixtobeconstructed.
The serial interface (C4i) clock for the device is 4.096 MHz.
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin
Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP)
Operating Temperature Range -40°C to +85°C
•
Thereceivedserialdataisinternallyconvertedtoaparallelformatbytheon
chipserial-to-parallelconvertersandstoredsequentiallyina128-positionData
Memory.Byusinganinternalcounterthatisresetbytheinput8KHzframepulse,
F0i, the incoming serial data streams can be framed and sequentially ad-
dressed.
DESCRIPTION:
The IDT728981 is a ST-BUS® compatible digital switch controlled by a
microprocessor. TheIDT728981canhandleasmanyas128,64Kbit/sinput
andoutputchannels. Those128channelsaredividedinto4serialinputsand
FUNCTIONAL BLOCK DIAGRAM
ODE
C4i F0i
VCC GND
Timing
Unit
Output MUX
RX0
TX0
TX1
TX2
TX3
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
RX1
Data
Memory
RX2
RX3
Connection
Memory
Control Register
Microprocessor Interface
5703 drw01
DS
A0/
A5
CS
R/W
D0/
D7
DTA
JANUARY 2001
1
©
2001 Integrated Device Technology, Inc.
DSC-5703/1
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
PINCONFIGURATION
INDEX
INDEX
RX3
RX3
7
TX3
39
38
37
36
1
33
32
31
30
TX3
(1)
(1)
8
DNC
V
V
V
V
CC
CC
CC
CC
V
CC
DNC
2
3
4
(1)
9
(1)
DNC
V
V
V
V
CC
CC
DNC
DNC
(1)
(1)
10
11
12
13
14
DNC
(1)
(1)
35
34
33
32
CC
CC
DNC
GND
5
6
7
8
29
28
27
26
DNC
GND
V
CC
F0i
C4i
D
0
1
F0i
C4i
D0
D1
D2
D3
D4
D
A
A
A
0
1
2
25
24
23
9
D
2
3
A
0
15
16
17
31
30
29
10
D
A
A
1
2
D4
11
(1)
DNC
5703 drw03
DTA
RX0
RX1
RX2
RX3
40
39
38
37
36
35
34
33
32
31
30
29
28
1
5703 drw02
ODE
TX0
TX1
TX2
TX3
2
3
4
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
5
VCC
VCC
VCC
6
(1)
DNC
7
(1)
DNC
8
(1)
V
CC
CC
DNC
9
(1)
DNC
GND
V
10
11
12
13
F0i
C4i
D
D
D
0
A
A
0
1
1
2
27
26
14
15
A
A
A
A
2
D
D
D
D
D
3
4
5
6
7
25
24
23
22
21
16
17
18
19
20
3
4
5
NOTE:
1. DNC - Do Not Connect
DS
R/W
CS
5703 drw04
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
PINDESCRIPTIONS
TOP VIEW
SYMBOL
NAME
I/O
DESCRIPTION
GND
VCC
Ground.
Ground Rail.
VCC
+5.0 Volt Power Supply.
DTA
Data Acknowledgment
(Open Drain)
O
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
RX0-3
F0i
C4i
RX Input 0 to 3
Frame Pulse
Clock
I
I
I
I
I
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input identifies frame synchronization signals formatted to ST-BUS® specifications.
4.096 MHz serial clock for shifting data in and out of the data streams.
A0-A5
Address 0 to 5
Data Strobe
These lines provide the address to IDT728981 internal registers.
DS
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
R/W
CS
Read/Write
I
I
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Active LOW input enabling a microprocessor read or write of control register or internal memories.
Chip Select
D0-D7
Data Bus 0 to 7
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX0-3
ODE
TX Outputs 0 to 3
(Three-state Outputs)
O
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
Output Drive Enable
I
This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
2
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
modes such as: Processor mode or Connection mode and Output Drivers
Enabledorinthree-statecondition.
FUNCTIONALDESCRIPTION(Cont'd)
Datatobeoutputontheserialstreamsmaycomefromtwosources:Data
MemoryorConnectionMemory. TheConnectionMemoryis16bitswideand
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particularchannelinanoutputstreamsoastoprovideaone-to-onecorrespon-
dencebetweenConnectionandDataMemories. Thiscorrespondenceallows
forperchannelcontrolforeachTXoutputstream.
OUTPUT DRIVE ENABLE (ODE)
TheODEpinisthemasterthree-stateoutputcontrolpin. IftheODEinput
is held LOW all TX outputs will be placed in high impedance regardless
ConnectionMemoryHighprogramming.However,ifODEisHIGH,thecontents
ofConnectionMemoryHighcontroltheoutputstateonaper-channelbasis.
In Processor Mode, data output on the TX is taken from the Connection
MemoryLowandoriginatesfromthemicroprocessor(Figure2).Whereasin
ConnectionMode(Figure1),dataisreadfromDataMemoryusingtheaddress
in Connection Memory. Data destined for a particular channel on the serial
output stream is read during the previous channel time slot to allow time for
memoryaccessandinternalparallel-to-serialconversion.
DELAY THROUGH THE IDT728981
Thetransferofinformationfromtheinputserialstreamstotheoutputserial
streamsresultsinadelaythroughthedevice. ThedelaythroughtheIDT728981
devicevariesaccordingtothecombinationofinputandoutputstreamsandthe
movementwithinthestreamfromchanneltochannel. Datareceivedonaninput
streammustfirstbestoredinDataMemorybeforeitissentout.
CONNECTIONMODE
AsinformationenterstheIDT728981itmustfirstpassthroughaninternal
serial-to-parallelconverter. Likewise, beforedataleavesthedevice, itmust
passthroughtheinternalparallel-to-serialconverter. Thisdatapreparationhas
an effect on the channel positioning in the frame immediately following the
incomingframe—mainly,datacannotleaveinthesametimeslot. Therefore,
informationthatistobeoutputinthesamechannelpositionastheinformation
isinput,relativetotheframepulse,willbeoutputinthefollowingframe.
Whether information can be output during a following timeslot after the
informationenteredtheIDT728981dependsonwhichRXstreamthechannel
informationentersonandwhichTXstreamtheinformationleaveson. Thisis
causedbytheorderinwhichinputstreaminformationisplacedintoDataMemory
andtheorderinwhichstreaminformationisqueuedforoutput. Table1showsthe
allowableinput/outputstreamcombinationsfortheminimumtwochanneldelay.
InConnectionMode,theaddressesofinputsourceforalloutputchannels
are stored in the Connection Memory Low. The Connection Memory Low
locationsaremappedtocorresponding8-bitx32-channeloutput. Thecontents
oftheDataMemoryattheselectedaddressarethentransferredtotheparallel-
to-serialconverters. Byhavingtheoutputchanneltospecifytheinputchannel
throughtheConnectionMemory,inputchannelscanbebroadcasttoseveral
outputchannels.
PROCESSOR MODE
InProcessorModetheCPUwritesdatatospecificConnectionMemoryLow
locations which are to be output on the TX streams. The contents of the
ConnectionMemoryLowaretransferredtotheparallel-to-serialconverterone
channelbeforeitistobeoutputandaretransmittedeachframetotheoutputuntil
it is changed by the CPU.
CONTROL
Input
Output Stream
The Connection Memory High bits (Table 4) control the per-channel
functionsavailableintheIDT728981.Outputchannelsareselectedintospecific
0
1
1,2,3
3
Table 1. Input Stream to Output Stream Combinations that can Provide the
Minimum 2-Channel Delay
Data
Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
RX
TX
Connection
Memory
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A5 A4 A3 A2 A1 A0 HEX ADDRESS
LOCATION
Control Register(1)
Channel 0(2)
Channel 1(2)
Figure 1. Connection Mode
0
X
0
0
•
X
0
0
•
X
0
0
•
0
0
0
•
0
0
1
•
00-1F
1
20
21
•
1
1
•
Data
·
•
•
•
•
•
•
•
Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
TX
1
1
•
•
•
•
•
•
•
Connection
Memory
1
1
1
1
1
3F
Channel 31(2)
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
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Microprocessor
Figure 2. Processor Mode
Table 2. Address Mapping
3
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
IfPEisLOW,thenbit2and0ofeachConnectionMemoryHighlocationoperates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channelisinProcessorMode. Ifbit2oftheCMHisLOW,thenthecontentsof
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
istobeswitchedtoanoutput.
IftheODEinputpinisLOW,thenalltheserialoutputsarehigh-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
ordisables(ifLOW)theoutputstreamandchannel.
SOFTWARECONTROL
If the A5 address line input is LOW then the IDT728981 Internal Control
Registerisaddressed. IfA5inputlineishigh,thentheremainingaddressinput
linesareusedtoselectthe32possiblechannelsperinputoroutputstream. The
addressinputlinesandtheStreamAddressbits(STA)oftheControlregister
give the user the capability of selecting all positions of IDT728981 Data and
Connectionmemories.TheIDT728981memorymappingisillustratedinTable
2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
StreamAddressbits,SplitMemoryandProcessorModebits.InSplitMemory
mode(Bit7oftheControlregister)readsarefromtheDataMemoryandwrites
aretotheConnectionMemoryasspecifiedbytheMemorySelectBits(Bits4
and3oftheControlRegister). TheMemorySelectbitsallowtheConnection
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream
Address bits define internal memory subsections corresponding to input or
outputstreams.
The Processor Enable bit (bit 6) places EVERY output channel on every
outputstreaminProcessormode;i.e.,thecontentsoftheConnectionMemory
LOW(CML,seeTable5))areoutputontheTXoutputstreamsonceeveryframe
unlesstheODEinputpinisLOW.IfPEbitisHIGH,thentheIDT728981behaves
as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection
MemoryHigh(CMH)locationsweresettoHIGH,regardlessoftheactualvalue.
INITIALIZATION OF THE IDT728981
Oninitializationorpowerup,thecontentsoftheConnectionMemoryHigh
canbeinanystate. ThisisapotentiallyhazardousconditionwhenmultipleTX
outputsaretiedtogethertoformmatrices.TheODEpinshouldbeheldlowon
poweruptokeepalloutputsinthehighimpedanceconditionuntilthecontents
of the CMH are programmed.
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
intothehighimpedancestate. CareshouldbetakenthatnotwoconnectedTX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedancestatecontroltotheConnectionMemoryHighbitsoutputs.
Control Register
CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0
b
b
b
b
b
b
b
b
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
CR 4 CR 3
b
b
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS®
stream.
0
1
1
1
0
1
Connection Memory High
Connection Memory Low
Data Memory
CR 1 CR 0
Stream
0
b
b
0
0
1
1
0
1
0
1
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
Channel 1
Channel 1
Channel 1
1
2
3
External Address Bits A5-A0
100000
100001
100010
111111
5703 drw07
Figure 3. Address Mapping
4
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
Mode Control
Bits
Memory Select
Bits
Stream Address
Bits
(unused)
(unused)
7
6
5
4
3
2
1
0
Bit
Name
Description
7
SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
6
PE (Processor Mode)
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.
5
unused
4-3
MS1-MS0
0-0 - Not to be used.
(Memory Select Bits)
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2
unused
1-0
STA1-0
(Stream Address Bits)
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
subsection of memory made accessible for subsequent operations.
Table 3. Control Register Configuration
No Corresponding Memory
- These bits give 0s if read
CS (unused) OE
7
6
5
4
3
2
1
0
Bit
Name
Description
2
CS (Channel Source)
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
1
0
unused
OE (Output Enable)
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
Table 4. Connection Memory High Register
Stream Address
(unused)
Bits
Channel Address Bits
7
6
5
4
3
2
1
0
Bit
Name
Description
7
unused
6-5(1) Stream Address Bits
The number expressed in binary notation on these 2 bits are the number of the stream for the source of the connection.
Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2.
4-0(1) Channel Address Bits
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.
Table 5. Connection Memory Low Register
5
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
(1)
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDOPERATING
CONDITIONS
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min. Typ.(1) Max.
Unit
V
VCC - GND
-0.3
7
V
V
Positive Supply
InputVoltage
4.75
0
⎯
⎯
⎯
5.25
VCC
+85
Vi
VO
VoltageonDigitalInputs
GND - 0.3
GND - 0.3
VCC +0.3
VCC +0.3
40
VI
V
VoltageonDigitalOutputs
CurrentatDigitalOutputs
StorageTemperature
V
TOP
OperatingTemperature
Commercial
-40
°C
IO
mA
°C
W
TS
-65
+150
2
NOTE:
PD
PackagePowerDissapation
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject
to production testing.
NOTE:
1. Exceeding these values may cause permanent damage. Functional operation
under these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
⎯
2.0
⎯
⎯
⎯
2.4
10
Typ.(1)
7
Max.
10
Units
mA
V
Test Conditions
ICC
SupplyCurrent
OutputsUnloaded
VIH
InputHighVoltage
InputLowVoltage
InputLeakage
⎯
⎯
⎯
8
⎯
0.8
5
VIL
V
IIL
μA
pF
VI between GND and VCC
CI
InputCapacitance
OutputHighVoltage
OutputHighCurrent
OutputLowVoltage
OutputLowCurrent
HighImpedanceLeakage
OutputPinCapacitance
⎯
⎯
⎯
0.4
⎯
5
VOH
IOH
⎯
15
V
IOH = 10mA
Sourcing. VOH = 2.4V
IOL = 5mA
mA
V
VOL
IOL
⎯
5
⎯
10
mA
μA
pF
Sinking. VOL = 0.4V
VO between GND and VCC
IOZ
⎯
⎯
⎯
8
CO
⎯
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
S1isopencircuitexceptwhentestingoutput
levelsorhighimpedancestates.
R
L
Output
Pin
S
2
S
1
C
L
S2 is switched to VCC orGND whentesting
outputlevelsorhighimpedancestates.
GND
GND
5703 drw08
Figure 4. Output Load
6
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS (1) ⎯ CLOCK TIMING
Symbol
tCLK
Characteristics
Min.
220
95
Typ.(2)
244
122
122
20
Max.
300
150
150
⎯
Unit
ns
Clock Period(3)
tCH
Clock Width High
ns
tCL
Clock Width Low
110
⎯
ns
tCTT
tFPS
tFPH
tFPW
ClockTransitionTime
FramePulseSetupTime
FramePulseHoldTime
FramePulseWidth
ns
20
⎯
200
50
ns
0.020
⎯
μs
ns
⎯
244
⎯
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. Contents of Connection Memory are not lost if the clock stops, however, TX outputs go into the high impedance state.
C4i
F0i
Channel 31
Bit 0
Channel 0
Bit 7
Bit Cells
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Figure 5. Frame Alignment
tCLK
tCTT
tCTT
t
CHL
t
CH
tCL
C4i
(
(
) )
tFPS
t
FPH
tFPS
t
FPH
tFPW
F0i
5703 drw10
Figure 6. Clock Timing
7
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS (1) ⎯ SERIAL STREAM TIMING
Symbol
Characteristics
Min.
Typ.(2)
30
Max.
Unit
Test Conditions
RL = 1KΩ(3), CL = 150pF
CL = 150pF
tTAZ
TX0-3 Delay - Active to High Z
TX0-3 Delay - High Z to Active
TX0-3 Delay - Active to Active
TX0-3HoldTime
20
60
ns
tTZA
25
45
70
ns
tTAA
30
45
70
ns
CL = 150pF
tTOH
tOED
tSIS
25
⎯
⎯
70
ns
CL = 150pF
RL = 1KΩ(3), CL = 150pF
OutputDriverEnableDelay
SerialInputSetupTime
SerialInputHoldTime
⎯
⎯
90
45
ns
-40
⎯
-20
⎯
ns
tSIH
ns
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
ODE
Bit Cell Boundary
tOED
tOED
TX0-3
C4i
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tTAZ
Figure 8. Output Driver Enable
tTOH
TX0-3
TX0-3
tTZA
Bit Cell Boundaries
C4i
t
TAA
t
SIS
t
SIH
t
TOH
TX0-3
RX0-3
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5703 drw13
Figure 7. Serial Outputs and External Control
Figure 9. Serial Inputs
8
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
ACELECTRICALCHARACTERISTICS (1) ⎯ PROCESSORBUS
Symbol
tCSS
Characteristics
Min.
10
10
10
⎯
2.7
20
⎯
⎯
20
20
⎯
0
Typ.(2)
0
Max.
⎯
⎯
⎯
60
Unit
ns
Test Conditions
ChipSelectSetupTime
Read/WriteSetupTime
AddressSetupTime
tRWS
tADS
⎯
⎯
30
ns
ns
tAKD
AcknowledgmentDelayFast
Acknowledgment Delay Slow
FastWriteDataSetupTime
Slow Write Data Delay
ReadDataSetupTime
DataHoldTimeRead
ns
CL = 150pF
C4i cycles(4)
tAKD
⎯
⎯
2.0
⎯
⎯
10
7.2
⎯
1.7
0.5
⎯
⎯
60
cycles
ns
tFWS
tSWD
tRDS
tDHT
cycles
cycles
ns
C4i cycles
C4i cycles, CL = 150pF
RL = 1KΩ(3), CL = 150pF
tDHT
DataHoldTimeWrite
ns
tRDZ
ReadDatatoHighImpedance
Chip Select Hold Time
Read/WriteHoldTime
AddressHoldTime
30
ns
RL = 1KΩ(3), CL = 150pF
tCSH
tRWH
tADH
tAKH
⎯
⎯
⎯
20
⎯
⎯
⎯
40
ns
0
ns
0
ns
AcknowledgmentHoldTime
10
ns
RL = 1KΩ(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i.
DS
t
CSS
t
CSH
CS
t
RWS
ADS
t
RWH
R/W
t
t
ADH
A5-A0
t
AKD
t
AKH
DTA
t
RDS
t
RDZ
tSWD
tFWS
t
DHT
D7-D0
5703 drw14
Figure 10. Processor Bus
9
ORDERINGINFORMATION
IDT
XXXXX
XX
X
Device Type Package Process
Blank
-40ºC to +85ºC (Commercial)
JG
PG
Green Plastic Leaded Chip Carrier – Green (PLCC, J44-1)
Green Plastic Dip – Green (P40-1)
Green Plastic Quad Flatpack – Green (PQFP, DB44-1)
DBG
728981
128 x 128 – Time Slot Interchange Digital Switch
DATASHEETDOCUMENTHISTORY
5/23/2000
8/18/2000
01/24/2001
pgs. 1, 2, and 10.
pgs. 1, 2 and 10.
pgs. 1 and 6.
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10
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