72821L25TF [IDT]
TQFP-64, Tray;
| 型号： | 72821L25TF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-64, Tray |
| 文件： | 总16页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
DUAL CMOS SyncFIFO™
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72801/72811/72821/72831/72841/72851hasa9-bitinputdataport(DA0
-DA8,DB0-DB8)anda9-bitoutputdataport(QA0-QA8,QB0-QB8).Each
inputportiscontrolledbyafree-runningclock(WCLKA,WCLKB),andtwoWrite
Enablepins(WENA1,WENA2,WENB1,WENB2). Dataiswrittenintoeachof
thetwoarraysoneveryrisingclockedgeoftheWriteClock(WCLKA,WCLKB)
when the appropriate write enable pins are asserted.
FEATURES:
•
•
•
•
•
•
The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
forthree-stateoutputcontrol.
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
applications
• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841/72851
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full
(PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.
Ifnotprogrammed,theprogrammableflagsdefaulttoempty+7forPAEAand
PAEB, and full-7 for PAFA and PAFB.
TheIDT72801/72811/72821/72831/72841/72851architecturelendsitself
tomanyflexibleconfigurationssuchas:
• 2-levelprioritydatabuffering
• Separate control lines and data lines for each FIFO
• Separate Empty, Full, Programmable Almost-Empty and Almost-
Full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin
Quad Flatpack (STQFP)
•
Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• Bidirectional operation
• Width expansion
• Depthexpansion
These FIFOs is fabricated using high-performance submicron CMOS
technology.
DESCRIPTION:
TheIDT72801/72811/72821/72831/72841/72851aredualsynchronous
(clocked)FIFOs. ThedeviceisfunctionallyequivalenttotwoIDT72201/72211/
72221/72231/72241/72251 FIFOs in a single package with all associated
control,data,andflaglinesassignedtoseparatepins.
FUNCTIONAL BLOCK DIAGRAM
EFA
WCLKB
PAEA
PAFA
FFA
WCLKA
WENA1
WENA2
WENB1
DA0 - DA8
DB0 - DB8
LDA
LDB
WENB2
INPUT REGISTER
OFFSET REGISTER
OFFSET REGISTER
INPUT REGISTER
EFB
FLAG
LOGIC
WRITE CONTROL
LOGIC
FLAG
LOGIC
WRITE CONTROL
LOGIC
PAEB
PAFB
FFB
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
RAM ARRAY
256 x 9, 512 x 9,
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
WRITE POINTER
READ POINTER
READ POINTER
WRITE POINTER
READ CONTROL
LOGIC
READ CONTROL
LOGIC
OUTPUT REGISTER
OUTPUT REGISTER
RESET LOGIC
RESET LOGIC
RCLKB
RSA
RSB
OEA
OEB
RCLKA
RENA1
RENA2
RENB1
QB0 - QB8
QA0 - QA8
RENB2
3034 drw 01
IDT, IDT logo and the SyncFIFOlogo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
MARCH 2013
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3034/6
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
QB0
QA
QA
QA
QA
QA
QA
QA
QA
1
2
3
4
5
6
7
8
1
FFB
2
EFB
OEB
RENB2
RCLKB
RENB1
GND
3
4
5
6
7
8
V
CC
PAEB
V
CC
9
WENA2/LDA
WCLKA
WENA1
RSA
10
11
12
13
14
15
16
PAFB
DB
DB
DB
DB
DB
0
1
2
3
DA
DA
DA
8
7
6
4
3034 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
MARCH2013
2
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTIONS
TheIDT72801/72811/72821/72831/72841/72851stwoFIFOs, referred descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorrespond-
to as FIFO A and FIFO B, are identical in every respect. The following ing signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8
DB0-DB8
RSA, RSB
Name
ADataInputs
BDataInputs
Reset
I/O
Description
I
I
I
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to
the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.
WCLKA
WCLKB
WriteClock
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write
enable(s)areasserted.
WENA1
WENB1
WriteEnable1
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write
Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,
WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if FFA (FFB) is LOW.
WENA2/LDA
WENB2/LDB
WriteEnable2/
Load
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)
is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.
If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)
if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA (LDB) is held LOW to write or
readtheprogrammableflagoffsets.
QA0-QA8
QB0-QB8
ADataOutputs
BDataOutputs
ReadClock
O
O
I
9-bit data outputs from RAM array A.
9-bit data outputs from RAM array B.
RCLKA
RCLKB
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1
(RENB1) and RENA2 (RENB2) are asserted.
RENA1
RENB1
Read Enable 1
Read Enable 2
OutputEnable
EmptyFlag
I
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2
RENB2
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA
OEB
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the
outputsDA0-DA8(DB0-DB8)willbeinahigh-impedancestate.
EFA
EFB
O
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.
When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA
PAEB
Programmable
Almost-Empty
Flag
When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the
appropriateoffsetregister. ThedefaultoffsetatresetisEmpty+7. PAEA (PAEB)issynchronizedto
RCLKA (RCLKB).
PAFA
PAFB
Programmable
Almost-FullFlag
O
O
When PAFA (PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate
offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
FFA
FFB
VCC
Full Flag
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
+5V power supply pin.
Power
GND
Ground
0V ground pin.
MARCH 2013
3
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
Min.
4.5
0
Typ. Max. Unit
Symbol
Rating
Com'l & Ind'l
Unit
V
VCC
SupplyVoltage
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
(Com'l & Ind'l)
SupplyVoltage
(Com'l & Ind'l)
5.0
0
5.5
0
V
V
GND
VIH
VIL
TSTG
IOUT
StorageTemperature
DC Output Current
–55to+125
–50to+50
°C
mA
InputHighVoltage
(Com'l & Ind'l)
NOTE:
2.0
—
—
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
InputLowVoltage
(Com'l & Ind'l)
—
0
—
—
0.8
V
TA
OperatingTemperature
Commercial
70 °C
TA
OperatingTemperature
Industrial
–40
—
85 °C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
Commercial and Industrial(1)
Commercial and Industrial(1)
tCLK = 10, 15, 25 ns
tCLK = 10, 15, 25 ns
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
(2)
ILI
InputLeakageCurrent(AnyInput)
–1
—
1
–1
—
1
μA
(3)
ILO
OutputLeakageCurrent
–10
2.4
—
—
—
—
—
—
10
—
–10
2.4
—
—
—
—
—
—
10
—
μA
V
VOH
VOL
ICC1
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current (both FIFOs)
StandbyCurrent
0.4
60
10
0.4
80
10
V
(4,5,6,8)
—
—
mA
mA
(
)
4,7,8
ICC2
—
—
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 2*[1.7 + 0.7*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
8. ICC1 and ICC2 parameters are improved as compared to previous data sheets.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
InputCapacitance
VIN = 0V
10
pF
(1,2)
COUT
OutputCapacitance
VOUT = 0V
10
pF
NOTE:
1. With output deselected (OEA, OEB ≥ VIH).
2. Characterized values, not currently tested.
MARCH2013
4
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Com'l &
(1)
Commercial
Ind'l
IDT72801L10
IDT72811L10
IDT72821L10
IDT72831L10
IDT72841L10
IDT72851L10
IDT72801L15
IDT72811L15
IDT72821L15
IDT72831L15
IDT72841L15
IDT72851L15
IDT72801L25
IDT72811L25
IDT72821L25
IDT72831L25
IDT72841L25
IDT72851L25
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Min
Max.
100
6.5
—
Min
Max.
Min
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
—
2
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
25
10
10
6
Clock High Time
—
Clock Low Time
—
6
Data Setup Time
—
4
tDH
Data Hold Time
0.5
3
—
1
1
tENS
tENH
tRS
Enable Setup Time
—
4
6
Enable Hold Time
0.5
10
8
—
1
1
Reset Pulse Width(2)
—
15
10
10
—
0
15
15
15
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Setup Time
—
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z(3)
Output Enable to Output Valid
Output Enable to Output in High-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
8
—
—
0
10
—
3
6
3
3
tOHZ
tWFF
tREF
tPAF
3
6
3
8
3
—
—
—
6.5
6.5
6.5
—
—
—
10
10
10
—
—
—
Write Clock to Programmable
Almost-Full Flag
tPAE
Read Clock to Programmable
Almost-Empty Flag
—
5
6.5
—
—
6
10
—
—
—
10
18
15
—
—
ns
ns
ns
tSKEW1
tSKEW2
Skew Time Between Read Clock and
Write Clock for Empty Flag and Full Flag
Skew Time Between Read Clock and Write
Clock for Programmable Almost-Empty Flag
and Programmable Almost-Full Flag
14
—
15
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
AC TEST CONDITIONS
30pF*
In Pulse Levels
GND to 3.0V
3ns
680Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
3034 drw 03
1.5V
or equivalent circuit
SeeFigure1
Figure 1. Output Load
*Includesjigandscopecapacitances.
MARCH 2013
5
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
When either of the two Read Enable RENA1, RENA2 (RENB1, RENB2)
associatedwithFIFOA(B)isHIGH,theoutputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
WhenallthedatahasbeenreadfromFIFOA(B),theEmptyFlagEFA(EFB)
willgoLOW,inhibitingfurtherreadoperations. Onceavalidwriteoperationhas
beenaccomplished, EFA (EFB)willgoHIGHaftertREFandavalidreadcan
begin. TheReadEnablesRENA1,RENA2(RENB1,RENB2)areignoredwhen
FIFO A (B) is empty.
SIGNALDESCRIPTIONS
FIFOAandFIFOBareidenticalineveryrespect.Thefollowingdescription
explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine data inputs
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
OutputEnable(OEA,OEB)—WhenOutputEnableOEA(OEB)isenabled
(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheirrespective
outputregister. WhenOutputEnable OEA(OEB)isdisabled(HIGH),theQA
(QB)outputdatabusisinahigh-impedancestate.
CONTROLS:
Reset (RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA
(RSB)inputistakentoaLOWstate.DuringReset,theinternalreadandwrite
pointersassociatedwiththeFIFOaresettothefirstlocation.AResetisrequired
afterpower-upbeforeawriteoperationcantakeplace. TheFullFlagFFA(FFB)
andProgrammableAlmost-FullflagPAFA(PAFB)willberesettoHIGHafter
tRSF. TheEmptyFlagEFA(EFB)andProgrammableAlmost-EmptyflagPAEA
(PAEB) will be reset to LOW after tRSF. During Reset, the output register is
initializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual-
purpose pin. FIFO A (B) is configured at Reset to have programmable flags
ortohavetwowriteenables, whichallowsdepthexpansion. IfWENA2/LDA
(WENB2/LDB) issetHIGHatResetRSA=LOW(RSB = LOW),thispinoperates
as a second write enable pin.
If FIFO A (B) is configured to have two write enables, when Write Enable
1WENA1(WENB1)isLOWandWENA2/LDA(WENB2/LDB)isHIGH,datacanbe
loaded into the input register and RAM array on the LOW-to-HIGH transition
ofeveryWriteClockWCLKA(WCLKB). Dataisstoredinthearraysequentially
and independently of any ongoing read operation.
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is
initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
WCLKA(WCLKB). TheFullFlagFFA(FFB)andProgrammableAlmost-Full
flagPAFA(PAFB)aresynchronizedwithrespecttotheLOW-to-HIGHtransition
oftheWriteClockWCLKA(WCLKB).
Inthisconfiguration,whenWENA1(WENB1)isHIGHand/orWENA2/LDA
(WENB2/LDB)isLOW,theinputregisterofArrayAholdsthepreviousdataand
no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag FFA (FFB) will go LOW, inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,FFA(FFB)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WENA1,(WENB1)and
WENA2/LDA (WENB2/LDB) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when the WENA2/
LDA(WENB2/LDB)issetLOWatResetRSA = LOW(RSB=LOW). EachFIFO
containsfour8-bitoffsetregisterswhichcanbeloadedwithdataontheinputs,
orreadontheoutputs. SeeFigure3fordetailsofthesizeoftheregistersand
thedefaultvalues.
If FIFO A (B) is configured to have programmable flags, when the WENA1
(WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputsarewrittenintotheEmpty(LeastSignificantBit)Offsetregisteronthefirst
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transitionofWCLKA(WCLKB),intotheFull(LeastSignificantBit)Offsetregister
onthethirdtransition, andintotheFull(MostSignificantBit)Offsetregisteron
thefourthtransition. ThefifthtransitionofWCLKA(WCLKB)againwritestothe
Empty(LeastSignificantBit)Offsetregister.
The Write and Read Clocks can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags, WENA1 (WENB1) is the only enable control pin. In this
configuration,whenWENA1(WENB1)isLOW,datacanbeloadedintotheinput
registerofRAMArrayA(B)ontheLOW-to-HIGHtransitionofeveryWriteClock
WCLKA(WCLKB). DataisstoredinArrayA(B)sequentiallyandindependently
of any ongoing read operation.
Inthisconfiguration,whenWENA1(WENB1)isHIGH,theinputregisterholds
the previous data and no new data is allowed to be loaded into the register.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write
operations. Uponthecompletionofavalidreadcycle,theFFA(FFB)willgoHIGH
aftertWFF,allowingavalidwritetobegin. WENA1(WENB1)isignoredwhenFIFO
A (B) is full.
However,writingalloffsetregistersdoesnothavetooccuratonetime. One
ortwooffsetregisterscanbewrittenandthenbybringingLDA(LDB)HIGH,FIFO
A (B) is returned to normal read/write operation. When LDA (LDB) is set LOW,
andWENA1(WENB1)isLOW,thenextoffsetregisterinsequenceiswritten.
ThecontentsoftheoffsetregisterscanbereadontheQA(QB)outputs when
WENA2/LDA(WENB2/LDB)issetLOWandbothReadEnablesRENA1,RENA2
(RENB1,RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransition
of the Read Clock RCLKA (RCLKB).
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on
theLOW-to-HIGHtransitionofRCLKA(RCLKB). TheEmptyFlagEFA(EFB)
andProgrammableAlmost-EmptyFlagPAEA(PAEB)aresynchronizedwith
respecttotheLOW-to-HIGHtransitionof RCLKA(RCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
Enables RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array
A(B)totheoutputregisterontheLOW-to-HIGHtransitionoftheReadClock
RCLKA (RCLKB).
MARCH2013
6
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
A read and write should not be performed simultaneously to the offset
registers.
LDA WENA1
LDB WENB1
WCLKA
WCLKB
OPERATION ON FIFO A
OPERATION ON FIFO B
0
0
Empty Offset (LSB)
OUTPUTS:
Empty Offset (MSB)
FullOffset(LSB)
Full Offset (MSB)
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations,when ArrayA(B)isfull. Ifnoreadsareperformedafterreset,FFA
(FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes
totheIDT72811'sFIFOA(B);1,024writestotheIDT72821'sFIFOA(B);2,048
writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A
(B); or 8,192 writes to the IDT72851's FIFO A (B).
0
1
1
0
1
NoOperation
WriteIntoFIFO
NoOperation
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe
WriteClockWCLKA(WCLKB).
1
EmptyFlag(EFA,EFB)—EFA(EFB)willgoLOW,inhibitingfurtherread
operations,whenthereadpointerisequaltothewritepointer,indicatingthat
Array A (B) is empty.
EFA(EFB)is synchronizedwithrespecttotheLOW-to-HIGHtransitionof
the Read Clock RCLKA (RCLKB).
NOTE:
1. For the purposes of this table, WENA2 and WENB2 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and
RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-
HIGH transition of RCLKA (RCLKB).
Figure 2. Writing to Offset Registers for FIFOs A and B
72821 - DUAL 1,024 x 9
72801 - DUAL 256 x 9
72811 - DUAL 512 x 9
8
8
8
8
7
7
0
0
0
0
8
8
8
8
0
0
0
0
8
8
8
8
0
0
0
0
7
7
7
7
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
1
1
(MSB)
(MSB)
0
0
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
1
1
(MSB)
0
(MSB)
0
72831 - DUAL 2,048 x 9
72841 - DUAL 4,096 x 9
72851 - DUAL 8,192 x 9
8
8
8
8
7
0
0
0
0
8
8
8
8
0
0
0
0
8
8
8
8
0
0
0
0
7
7
7
7
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
3
4
2
(MSB)
(MSB)
(MSB)
0
0
0
7
Full Offset (LSB)
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
Default Value 007H
3
4
2
(MSB)
(MSB)
(MSB)
0
0
0
3034 drw 04
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
MARCH 2013
7
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will
ProgrammableAlmost–EmptyFlag(PAEA,PAEB)—PAEA(PAEB)will
goLOWwhentheamountofdatainArrayA(B)reachesthealmost-fullcondition. goLOWwhenthereadpointeris"n+1"locationslessthanthewritepointer. The
IfnoreadsareperformedafterReset,PAFA(PAFB)willgoLOWafter(256-m) offset"n"isdefinedintheEmptyOffset registers. Ifnoreadsareperformedafter
writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO Reset,PAEA(PAEB)willgoHIGHafter"n+1"writestoFIFOA(B).
A(B);(1,024-m)writestotheIDT72821'sFIFOA(B);(2,048-m)writestothe
IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or words.
(8,192-m) writes to the IDT72851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe of the Read Clock RCLKA (RCLKB).
Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
IfthereisnoEmptyoffsetspecified,PAEA(PAEB)willgoLOWatEmpty+7
PAEA(PAEB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
Data Outputs (QA0 –QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data
registers.
outputsformemoryarrayA,QB0 -QB8aretheninedataoutputsformemory
array B.
IfthereisnoFulloffsetspecified,PAFA(PAFB)willgoLOWatFull-7words.
PAFA(PAFB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
ofWCLKA(WCLKB).
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A
FFA
FFB
PAFA
PAFB
PAEA
PAEB
EFA
EFB
NUMBER OF WORDS IN ARRAY B
72801
72811
72821
0
1 to n(1)
0
1 to n(1)
0
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
1 to n(1)
(n+1) to (256-(m+1))
(256-m)(2) to 255
256
(n+1) to (512-(m+1))
(512-m)(2) to 511
512
(n+1) to (1,024-(m+1))
(1,024-m)(2) to 1,023
1,024
H
H
H
L
NUMBER OF WORDS IN ARRAY A
FFA
FFB
PAFA
PAFB
PAEA
PAEB
EFA
EFB
NUMBER OF WORDS IN ARRAY B
72831
72841
72851
0
0
0
H
H
H
H
L
H
H
H
L
L
L
L
1 to n(1)
1 to n(1)
1 to n(1)
H
H
H
H
(n+1) to (2,048-(m+1))
(2,048-m)(2) to 2,047
2,048
(n+1) to (4,096-(m+1))
(4,096-m)(2) to 4,095
4,096
(n+1) to (8,192-(m+1))
(8,192-m)(2) to 8,191
8,192
H
H
H
L
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
MARCH2013
8
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
RSA (RSB)
tRSS
tRSS
tRSS
t
RSR
RSR
RENA1, RENA2
(RENB1, RENB2)
t
WENA1
(WENB1)
tRSR
(1)
WENA2/LDA
(WENB2/LDB)
tRSF
EFA, PAEA
(EFB, PAEB)
tRSF
FFA, PAFA
(FFB, PAFB)
tRSF
(2)
OEA (OEB) = 1
QA
(QB
0
- QA
8
0
- QB8)
3034 drw 05
OEA (OEB) = 0
NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW
during reset will make the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 4. Reset Timing
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tDH
tDS
DA
(DB
0
- DA
8
0
- DB8)
DATA IN VALID
t
ENH
ENH
t
ENS
WENA1
(WENB1)
NO OPERATION
NO OPERATION
t
tENS
WENA2 (WENB2)
(If Applicable)
t
WFF
tWFF
FFA
(FFB)
(1)
SKEW1
t
RCLKA (RCLKB)
RENA1, RENA2
(RENB1, RENB2)
3034 drw 06
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.
Figure 5. Write Cycle Timing
MARCH 2013
9
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
NO OPERATION
tREF
tREF
EFA (EFB)
tA
QA
(QB
0
- QA
8
VALID DATA
0
- QB8)
tOLZ
tOHZ
tOE
OEA (OEB)
(1)
SKEW1
t
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2 (WENB2)
3034 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
Figure 6. Read Cycle Timing
WCLKA (WCLKB)
tDS
DA
(DB
0
- DA
8
D1
D2
D3
0
- DB8)
D0
(First Valid Write)
tENS
WENA1 (WENB1)
tENS
WENA2 (WENB2)
(If Applicable)
(1)
tFRL
tSKEW1
RCLKA (RCLKB)
tREF
EFA (EFB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
tA
QA
(QB
0
- QA
8
D0
D1
0
- QB8)
tOLZ
tOE
OEA (OEB)
NOTE:
3034 drw 08
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1V or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. First Data Word Latency Timing
MARCH2013
10
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
NO WRITE
NO WRITE
NO WRITE
WCLKA
(WCLKB)
tSKEW1
tSKEW1
tDS
tDH
DA
(DB
0
- DA
8
0
- DB8)
t
WFF
t
WFF
tWFF
FFA (FFB)
(1)
tENH
tENS
tENS
WENA1
(WENB1)
(1)
ENS
tENS
tENH
t
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
tENH
tENH
tENS
tENS
RENA1
(RENB2)
tA
OEA
(OEB)
LOW
tA
QA
(QB
0
- QA
8
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
0
- QB8)
3034 drw 09
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLKA (WCLKB)
tDS
tDS
DA
(DB
0
- DA
8
DATA WRITE 1
DATA WRITE 2
0
- DB8)
tENS
tENH
tENS
tENH
WENA1, (WENB1)
tENS
tENH
tENH
tENS
WENA2 (WENB2)
(If Applicable)
(1)
FRL
(1)
FRL
t
t
tSKEW1
tSKEW1
RCLKA (RLCKB)
tREF
tREF
tREF
EFA (EFB)
RENA1, RENA2
(RENB1, RENB2)
LOW
OEA (OEB)
tA
QA
0
-QA
8
DATA IN OUTPUT REGISTER
DATA READ
(QB
0
-QB
8
)
3034 drw 10
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
MARCH 2013
11
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
(4)
WCLKA
(WCLKB)
tENH
tENS
WENA1
(WENB1)
tENS
tENH
WENA2 (WENB2)
(If Applicable)
t
PAF
(2)
Full - (m+1) words in FIFO(1)
PAFA
(PAFB)
Full - m words in FIFO
(3)
SKEW2
t
tPAF
RCLKA (RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
3034 drw 11
NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m)
words for the IDT72851.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the
rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
Figure 10. Programmable Full Flag Timing
tCLKH
tCLKL
WCLKA (WCLKB)
tENS
tENH
WENA1
(WENB1)
tENS
tENH
WENA2 (WENB2)
(If Applicable)
PAEA,
PAEB
n words in FIFO (1)
n+1 words in FIFO
(2)
tSKEW2
t
PAE
tPAE
(3)
RCLKA (RCLKB)
tENH
tENS
3034 drw 12
RENA1, RENA2
(RENB1, RENB2)
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the
rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
Figure 11. Programmable Empty Flag Timing
MARCH2013
12
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKL
WCLKA (WCLKB)
tENH
tENS
LDA (LDB)
tENS
WENA1 (WENB1)
tDH
tDS
DA
(DB
0
- DA
7
0
- DB7)
3034 drw 13
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
Figure 12. Write Offset Register Timing
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENH
tENS
LDA (LDB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
QA
(QB
0
- QA
7
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
DATA IN OUTPUT REGISTER
0
- QB7)
FULL OFFSET
(MSB)
3034 drw 14
Figure 13. Read Offset Register Timing
MARCH 2013
13
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
can be grounded (see Figure 14). In this configuration, the Write Enable 2/
Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin
operates as a control to load and read the programmable flag offsets.
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
Device Configuration, the Read Enable 2 RENA2(RENB2) control input
RSA (RSB)
WCLKA (WCLKB)
WENA1 (WENB1)
RCLKA (RCLKB)
RENA1 (RENB1)
IDT
72801
72811
72821
72831
72841
72851
WENA2/LDA (WENB2/LDB)
OEA (OEB)
QA - QA (QB0 - QB8)
0
8
DA0
- DA
8
(DB
FFA (FFB)
PAFA (PAFB)
0 - DB8)
EFA (EFB)
PAEA (PAEB)
FIFO
A (B)
RENA2 (RENB2)
3034 drw 15
Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs
configured as a single device
WIDTH EXPANSION CONFIGURATION — Word width may be in- be attained by adding additional IDT72801/72811/72821/72831/72841/
creased simply by connecting the corresponding input control signals of 72851s.
FIFOsA andB. A compositeflagshouldbecreatedfor eachoftheendpoint
When these devices are in a Width Expansion Configuration, the Read
status flags EFA and EFB, also FFA and FFB). The partial status flags Enable 2 (RENA2 and RENB2) control inputs can be grounded (see
PAEA, PAFB, PAEAand PAFBcan be detected from any one device. Figure 15). In this configuration, the Write Enable 2/Load (WENA2/LDA,
Figure15demonstratesan18-bitwordwidthusingthetwoFIFOscontained WENB2/LDB) pins are set LOW at Reset so that the pin operates as a
in one IDT72801/72811/72821/72831/72841/72851. Any word width can controltoloadandreadtheprogrammableflagoffsets.
9
RESET
DB0 - DB8
RCLKA
RSB
RSA
EFA
EFB
EMPTY FLAG
READ CLOCK
DATA IN
18
9
DA0 - DA8
RAM
ARRAY
B
RAM
ARRAY
A
RCLKB
WRITE CLOCK
WCLKB
WCLKA
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
RENB1
OEB
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
READ ENABLE
RENA1
WENB1
OEA1
WENA1
WRITE ENABLE
OUTPUT ENABLE
WRITE ENABLE/LOAD
2WENB2/LDB
WENA2/LDA
FFA
FFB
QB0 - QB8
DATA OUT
18
9
FULL FLAG
RENA2
RENB2
QA0 - QA8
3034 drw 16
9
Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/
72821/72831/72841/72851 configured for an 18-bit width-expansion
MARCH2013
14
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
accordingtotype,sendingonekindtoFIFOAandtheotherkindtoFIFOB.Then,
at theoutputs,eachdatatypeistransferredtoitsappropriatedestination.Additional
IDT72801/72811/72821/72831/72841/72851s permit more than two priority
levels.Prioritybufferingisparticularlyusefulinnetworkapplications.
TWO PRIORITY DATA BUFFER
CONFIGURATION
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
72851canbeusedtoprioritizetwodifferenttypesofdatasharedonasystembus.
When writing from the bus to the FIFO, control logic sorts the intermixed data
Image Processing
RAM ARRAY A
Card
Clock
RCLKA
WCLKA
OEA
Address
Control
WENA1
RENA
9
9
DA0-DA8
Q
A0-QA8
Data
I/O Data
RENA2
WENA2
VCC
Processor
Clock
IDT
72801
72811
72821
72831
72841
72851
Address
Control
Voice Processing
Card
Data
9
9
RAM ARRAY B
Clock
RCLKB
WCLKB
WENB1
OEB2
Address
Control
RAM
RENB1
I/O Data
D
B0-DB8
Data
Q
B0-QB8
9
9
RENB2
WENB2
3034 drw 17
VCC
Figure 16. Block Diagram of Two Priority Configuration
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
BIDIRECTIONAL CONFIGURATION
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
be used to buffer data flow in two directions. In the example that follows, a
RAM ARRAY A
V
CC
RENA2
WENA2
RCLKA
WCLKA
OEA
WENA1
RENA1
9
Peripheral
Controller
DA0-DA8
QA0-QA8
Processor
Clock
9
IDT
DMA Clock
72801
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72821
72831
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72851
Address
Control
Address
Control
I/O Data
Data
Data
RAM ARRAY B
9
9
RCLKB
WENB1
RENB1
RAM
9
WCLKB
OEB
QB0-QB8
3034 drw 18
DB0-DB8
RENB2
9
9
WENB2
Figure 17. Block Diagram of Bidirectional Configuration
MARCH 2013
15
DEPTH EXPANSION — IDT72801/72811/72821/72831/72841/72851 accessfromonedevicetothenextinasequentialmanner. TheseFIFOsoperate
can be adapted to applications that require greater than 256/512/1,024/ intheDepthExpansionconfigurationwhenthefollowingconditionsaremet:
2,048/4,096/8,192 words. The existence of double enable pins on the read
1. WENA2/LDAand WENB2/LDBpins are held HIGH during Reset so
and write ports allow depth expansion. The Write Enable 2/Load (WENA2, that these pins operate as second Write Enables.
WENB2) pins are used as a second write enables in a depth expansion
configuration, thus the Programmable flags are set to the default values.
2. External logic is used to control the flow of data.
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN-
Depth expansion is possible by using one enable input for system control CHRONOUSFIFOsUSINGTHERINGCOUNTERAPPROACH"fordetails
whiletheotherenableinputiscontrolledbyexpansionlogictodirecttheflow of this configuration.
of data. A typical application would have the expansion logic alternate data
ORDERING INFORMATION
XXXXX
X
X
XX
XX
X
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
BLANK
8
Tube or Tray
Tape and Reel
BLANK
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
(1)
I
(2)
G
Green
PF
TF
Thin Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack(STQFP, PP64-1)
Commercial Only
Commercial and Industrial
Commercial and Industrial
Clock Cycle Time
(tCLK), Speed in
Nanoseconds
10
15
25
L
Low Power
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256 x 9 Dual SyncFIFO
512 x 9 Dual SyncFIFO
1,024 x 9 Dual SyncFIFO
2,048 x 9 Dual SyncFIFO
4,096 x 9 Dual SyncFIFO
72831
72841
72851
8,192 x 9 Dual SyncFIFO
3034 drw 19
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
04/24/2001
02/10/2006
01/13/2009
03/20/2013
pgs. 4, 5 and 16.
pgs. 1 and 16.
pg. 16.
pg. 1, 3, 7 and 16.
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800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
16
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