71V632S6PFI [IDT]

Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
71V632S6PFI
型号: 71V632S6PFI
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Cache SRAM, 64KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

时钟 静态存储器 内存集成电路
文件: 总19页 (文件大小:272K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
64K x 32  
3.3VSynchronousSRAM  
PipelinedOutputs  
IDT71V632  
BurstCounter,SingleCycleDeselect  
Features  
withfullsupportofthePentium™andPowerPC™processorinterfaces.  
Thepipelinedburstarchitectureprovidescost-effective3-1-1-1second-  
arycache performance forprocessors upto117MHz.  
The IDT71V632 SRAM contains write, data, address, and control  
registers.Internallogicallows theSRAMtogenerateaself-timedwrite  
baseduponadecisionwhichcanbeleftuntiltheextremeendofthewrite  
cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V632canprovide fourcycles ofdata for  
asingleaddresspresentedtotheSRAM.Aninternalburstaddresscounter  
acceptsthefirstcycleaddressfromtheprocessor,initiatingtheaccess  
sequence.Thefirstcycleofoutputdatawillbepipelinedforonecyclebefore  
it is available on the next rising clock edge. If burst mode operation is  
selected(ADV=LOW),thesubsequentthreecyclesofoutputdatawillbe  
availabletotheuseronthenextthreerisingclockedges.Theorderofthese  
threeaddresseswillbedefinedbytheinternalburstcounterandtheLBO  
inputpin.  
64K x 32 memory configuration  
Supports high system speed:  
Commercial:  
A4 4.5ns clockaccess time (117MHz)  
CommercialandIndustrial:  
– 5 5ns clockaccess time (100MHz)  
– 6 6ns clockaccess time (83MHz)  
– 7 7ns clockaccess time (66MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC64K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V632SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboarddensity  
inbothdesktopandnotebookapplications.  
Description  
TheIDT71V632isa3.3Vhigh-speedSRAMorganizedas64Kx32  
PinDescriptionSummary  
0
15  
A –A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chips Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
1,  
2,  
3,  
4
BW BW BW BW  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0–I/O31  
Data Input/Output  
DD DDQ  
V , V  
3.3V  
Power  
Power  
SS SSQ  
V , V  
Array Ground, I/O Ground  
N/A  
3619 tbl 01  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3619/03  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Pin Definitions(1)  
Symbol  
Pin Function  
I/O  
Active  
Description  
Address Inputs  
I
N/A  
Synchronous Address inputs. The address register is triggered by a combination  
A0A15  
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.  
Address Status  
(Cache Controller)  
I
LOW  
Synchronous Address Status from Cache Controller.ADSC is an active LOW  
input that is used to load the address registers with new addresses. ADSC is  
NOT GATED by CE.  
ADSC  
Synchronous Address Status from Processor. ADSP is an active LOW input that  
Address Status  
(Processor)  
I
I
LOW  
LOW  
ADSP  
ADV  
is used to load the address registers with new addresses. ADSP is gated by  
CE.  
Burst Address Advance  
Synchronous Address Advance. ADV is an active LOW input that is used to  
advance the internal burst counter, controlling burst access after the initial  
address is loaded. When this input is HIGH the burst counter is not incremented;  
that is, there is no address advance.  
Byte Write Enable  
I
I
LOW  
LOW  
Synchronous byte write enable gates the byte write inputs BW1BW4. If BWE is  
LOW at the rising edge of CLK then BWX inputs are passed to the next stage in  
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of  
CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will  
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked  
and only GW can initiate a write cycle.  
BWE  
Individual Byte  
Write Enables  
Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8),  
etc. Any active byte write causes all outputs to be disabled. ADSP LOW  
disables all byte writes. BW1BW4 must meet specified setup and hold times  
with respect to CLK.  
BW1BW4  
Chip Enable  
Clock  
I
I
I
I
LOW  
N/A  
Synchronous chip enable. CE is used with CS0 and CS1 to enable the  
IDT71V632. CE also gates ADSP.  
CE  
CLK  
CS0  
CS1  
This is the clock input. All timing references for the device are made with respect  
to this input.  
Chip Select 0  
Chip Select 1  
HIGH  
LOW  
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable  
the chip.  
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable  
the chip.  
Synchronous global write enable. This input will write all four 8-bit data bytes  
when LOW on the rising edge of CLK. GW supercedes individual byte write  
enables.  
Global Write Enable  
I
LOW  
GW  
Data Input/Output  
Linear Burst Order  
I/O  
I
N/A  
Synchronous data input/output (I/O) pins. Both the data input path and data output  
path are registered and triggered by the rising edge of CLK.  
I/O0–I/O31  
LOW  
Asynchronous burst order selection DC input. When LBO is HIGH the Interleaved  
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst  
sequence is selected. LBO is a static DC input and must not change state while  
the device is operating.  
LBO  
Output Enable  
I
LOW  
Asynchronous output enable. When OE is LOW the data output drivers are  
enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O  
pins are in a high-impedence state.  
OE  
VDD  
VDDQ  
VSS  
VSSQ  
NC  
Power Supply  
Power Supply  
Ground  
N/A  
N/A  
N/A  
N/A  
N/A  
I
N/A  
N/A  
N/A  
N/A  
N/A  
HIGH  
3.3V core power supply inputs.  
3.3V I/O power supply inputs.  
Core ground pins.  
Ground  
I/O ground pins.  
No Connect  
Sleep Mode  
NC pins are not electrically connected to the chip.  
ZZ  
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power  
down the IDT71V632 to its lowest power consumption level. Data retention is  
guaranteed in Sleep Mode.  
3619 tbl 02  
NOTE:  
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.  
6.422  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
FunctionalBlockDiagram  
LBO  
ADV  
INTERNAL  
ADDRESS  
CE  
CLK  
2
Burst  
Logic  
64K x 32  
BIT  
MEMORY  
ARRAY  
Binary  
Counter  
16  
ADSC  
A0*  
A1*  
Q0  
Q1  
CLR  
.
ADSP  
2
CLK EN  
A0, A1  
A2–A15  
ADDRESS  
REGISTER  
A0–A15  
GW  
32  
32  
16  
Byte 1  
Write Register  
BWE  
Byte 1  
Write Driver  
BW1  
BW2  
8
8
Byte 2  
Write Register  
Byte 2  
Write Driver  
Byte 3  
Write Register  
Byte 3  
Write Driver  
BW3  
8
8
Byte 4  
Write Register  
Byte 4  
Write Driver  
4
BW  
OUTPUT  
REGISTER  
CE  
Q
D
CS0  
CS1  
Enable  
DATA INPUT  
REGISTER  
Register  
CLK EN  
Powerdown  
ZZ  
D
Q
Enable  
Delay  
Register  
OE  
OUTPUT  
BUFFER  
OE  
32  
I/O0–I/O31  
3619 drw 01  
6.42  
3
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
AbsoluteMaximumRatings(1)  
RecommendedOperating  
TemperatureandSupplyVoltage  
Symbol  
Rating  
Value  
Unit  
SS  
DD  
DDQ  
V
Grade  
Temperature  
0°C to +70°C  
–40°C to +85°C  
V
V
(2)  
TERM  
Terminal Voltage with  
Respect to GND  
–0.5 to +4.6  
V
V
Commercial  
Industrial  
0V  
0V  
3.3V+10/-5% 3.3V+10/-5%  
(3)  
TERM  
DD  
Terminal Voltage with  
Respect to GND  
–0.5 to V +0.5  
V
V
3.3V+10/-5% 3.3V+10/-5%  
3619 tbl 03  
oC  
oC  
oC  
W
A
T
Operating Temperature  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
0 to +70  
–55 to +125  
–55 to +125  
1.0  
BIAS  
T
RecommendedDCOperating  
Conditions  
STG  
T
T
P
OUT  
I
DC Output Current  
50  
mA  
Symbol  
Parameter  
Min.  
3.135  
3.135  
0
Max.  
3.63  
3.63  
0
Unit  
V
3619 tbl 05  
DD  
V
Core Supply Voltage  
I/O Supply Voltage  
Ground  
NOTES:  
DDQ  
V
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated  
in the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability.  
2. VDD, VDDQ and Input terminals only.  
SS, SSQ  
V
V
V
Input Hig h Vo ltag e Inp uts  
Input High Voltage I/O  
Inp ut Low Vo ltage  
2.0  
5.0(1)  
V
IH  
V
(2)  
IH  
V
DDQ  
+0.3  
2.0  
V
V
3. I/O terminals.  
–0.3(3)  
0.8  
V
IL  
V
3619 tbl 04  
NOTES:  
1. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.  
2. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.  
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.  
Capacitance  
(TA = +25°C, f = 1.0MHz, TQFP package)  
Symbol  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
Max. Unit  
IN  
C
IN  
V = 3dV  
6
7
pF  
I/O  
C
OUT  
V
= 3dV  
pF  
3619 tbl 06  
NOTE:  
1. This parameter is guaranteed by device characterization, but not production  
tested.  
6.442  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
PinConfiguration  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
1
80  
NC  
I/O15  
I/O14  
VDDQ  
VSSQ  
I/O13  
I/O12  
I/O11  
I/O10  
VSSQ  
VDDQ  
I/O9  
I/O8  
VSS  
NC  
VDD  
ZZ(2)  
I/O7  
NC  
2
79  
I/O16  
I/O17  
VDDQ  
VSSQ  
I/O18  
I/O19  
I/O20  
I/O21  
VSSQ  
VDDQ  
3
78  
4
77  
5
76  
75  
74  
73  
6
7
8
9
72  
71  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
70  
69  
68  
67  
66  
I/O22  
I/O23  
VDD/NC(1)  
VDD  
PK100-1  
65  
64  
NC  
VSS  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
I/O24  
I/O25  
VDDQ  
VSSQ  
I/O26  
I/O27  
I/O28  
I/O29  
VSSQ  
VDDQ  
I/O30  
I/O31  
NC  
I/O6  
VDDQ  
VSSQ  
I/O5  
I/O4  
I/O3  
I/O2  
VSSQ  
VDDQ  
I/O1  
I/O0  
NC  
31  
33 34 35 36  
38 39 40 41 42 43 44 45 46 47 48 49 50  
37  
32  
3619 drw 02  
TopViewTQFP  
NOTES:  
1. Pin 14 can either be directly connected to VDD or not connected.  
2. Pin 64 can be left unconnected and the device will always remain in active mode.  
6.42  
5
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
SynchronousTruthTable(1,2)  
Address  
Used  
Operation  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Read Cycle, Begin Burst  
CE  
H
L
CS0  
X
X
L
CS1 ADSP ADSC ADV  
GW  
X
X
X
X
X
X
X
H
H
H
H
L
BWE  
X
X
X
X
X
X
X
H
L
BWX OE(3) CLK  
I/O  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
DOUT  
Hi-Z  
DOUT  
DOUT  
Hi-Z  
DIN  
None  
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
None  
None  
L
L
None  
L
X
L
X
X
L
None  
L
L
External  
External  
External  
External  
External  
External  
External  
Next  
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Read Cycle, Begin Burst  
L
L
L
H
L
Read Cycle, Begin Burst  
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
Read Cycle, Begin Burst  
L
L
L
L
Read Cycle, Begin Burst  
L
L
L
L
H
X
X
L
Write Cycle, Begin Burst  
L
L
L
L
Write Cycle, Begin Burst  
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT  
Hi-Z  
DOUT  
Hi-Z  
DOUT  
Hi-Z  
DOUT  
Hi-Z  
DIN  
Next  
L
H
L
Next  
L
Next  
L
H
L
Next  
L
Next  
L
H
L
Next  
L
Next  
L
H
X
X
X
X
L
Next  
L
Next  
L
X
L
X
L
DIN  
Next  
L
H
L
DIN  
Next  
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT  
Hi-Z  
DOUT  
Hi-Z  
DOUT  
Hi-Z  
DOUT  
Hi-Z  
DIN  
H
L
H
L
H
L
H
X
X
X
X
X
L
X
L
DIN  
H
L
DIN  
X
X
DIN  
3619 tbl 07  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. ZZ = LOW for this table.  
3. OE is an asynchronous input.  
6.462  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Synchronous WriteFunction Truth Table(1)  
1
2
3
4
BW  
Operation  
GW  
H
H
L
BWE  
H
L
BW  
X
H
X
L
BW  
BW  
Read  
Read  
X
H
X
L
X
H
X
L
X
H
X
L
Write all Bytes  
Write all Bytes  
Write Byte 1(2)  
Write Byte 2(2)  
Write Byte 3(2)  
Write Byte 4(2)  
X
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
L
H
3619 tbl 08  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. Multiple bytes may be selected during the same cycle.  
AsynchronousTruthTable(1)  
Operation(2)  
OE  
ZZ  
I/O Status  
Power  
Active  
Active  
Active  
0
31  
Read  
Read  
L
L
Data Out (I/O - I/O )  
H
X
X
X
L
High-Z  
0
31  
Write  
L
High-Z — Data In (I/O - I/O )  
Deselected  
Sleep  
L
High-Z  
High-Z  
Standby  
Sleep  
H
3619 tbl 09  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.  
InterleavedBurstSequence Table (LBO=VDD)  
Sequence 1  
Sequence 2  
Sequence 3  
Sequence 4  
A1  
0
A0  
0
A1  
0
A0  
1
A1  
1
A0  
0
A1  
1
A0  
1
First Address  
Second Address  
Third Address  
Fourth Address(1)  
NOTE:  
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
3619 tbl 10  
1. Upon completion of the Burst sequence the counter wraps around to its initial state.  
Linear Burst Sequence Table (LBO=VSS)  
Sequence 1  
Sequence 2  
Sequence 3  
Sequence 4  
A1  
0
A0  
0
A1  
0
A0  
1
A1  
1
A0  
0
A1  
1
A0  
1
First Address  
Second Address  
Third Address  
Fourth Address(1)  
NOTE:  
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
3619 tbl 11  
1. Upon completion of the Burst sequence the counter wraps around to its initial state.  
6.42  
7
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
DC Electrical Characteristics Over the Operating Temperature and  
Supply Voltage Range(VDD = 3.3V +10/-5%)  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
5
Unit  
µA  
µA  
µA  
V
|ILI|  
Input Leakage Current  
VDD = Max., VIN = 0V to VDD  
|ILZZ|  
ZZ and LBO Input Leakage Current(1) VDD = Max., VIN = 0V to VDD  
30  
5
|ILO  
Output Leakage Current  
|
CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max.  
VOL (3.3V) Output Low Voltage  
VOH (3.3V) Output High Voltage  
IOL = 5mA, VDD = Min.  
IOH = –5mA, VDD = Min.  
0.4  
2.4  
V
3619 tbl 12  
NOTE:  
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.  
DC Electrical Characteristics Over the Operating Temperature and  
Supply Voltage Range(1) (VHD = VDDQ – 0.2V, VLD = 0.2V)  
SA4(3,4)  
S5  
S6  
S7  
Symbol  
Parameter  
Test Conditions  
Com'l.  
Ind.  
Com'l.  
Ind.  
Com'l.  
Ind.  
Com'l.  
Ind.  
Unit  
IDD  
Operating Power  
Supply Current  
Device Selected, Outputs Open,  
VDD = Max., VIN > VIH or < VIL,  
f = fMAX  
220  
70  
200  
200  
180  
180  
160  
160  
mA  
(2)  
ISB  
Standby Power  
Supply Current  
Device Deselected, Outputs Open,  
65  
15  
10  
65  
15  
10  
60  
15  
10  
60  
15  
10  
55  
15  
10  
55  
15  
10  
mA  
mA  
DD  
IN IH IL  
= Max., V > V or < V ,  
(2)  
V
f = fMAX  
ISB1 Full Standby Power  
Supply Current  
Device Deselected, Outputs Open,  
15  
DD  
IN  
HD  
LD  
V
= Max., V > V or < V ,  
f = 0(2)  
HD DD  
ZZ > V , V = Max.  
Full Sleep Mode  
Power Supply Current  
10  
mA  
IZZ  
3619 tbl 13  
NOTES:  
1. All values are maximum guaranteed values.  
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.  
3. SA4 speed grade corresponds to a tCD of 4.5 ns.  
4. 0°C to +70°C temperature range only.  
+3.3V  
AC Test Loads  
VDDQ/2  
317  
I/O  
50  
5pF*  
I/O  
Z0 = 50Ω  
351Ω  
3619 drw 03  
Figure 1. AC Test Load  
3619 drw 04  
* Including scope and jig capacitance.  
6
Figure 2. High-Impedence Test Load  
5
4
3
2
1
(for tOHZ, tCHZ, tOLZ, and tDC1)  
tCD  
(Typical, ns)  
AC Test Conditions  
Input Pulse Levels  
0 to 3.0V  
Input Rise/Fall Times  
2ns  
1.5V  
Input Timing Reference Levels  
Output Timing Reference Levels  
AC Test Load  
20 30 50  
80 100  
Capacitance (pF)  
200  
1.5V  
3619 drw 05  
See Figures 1 and 2  
Figure 3. Lumped Capacitive Load, Typical Derating  
3619 tbl 14  
6.482  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
AC Electrical Characteristics  
(VDD, VDDQ = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)  
71V632SA4(5,6)  
71V632S5  
71V632S6  
71V632S7  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
CLOCK PARAMETERS  
CYC  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
Clock Cycle Time  
8.5  
3.5  
3.5  
10  
4
12  
4.5  
4.5  
15  
5
ns  
ns  
ns  
(1)  
CH  
t
Clock High Pulse Width  
Clock Low Pulse Width  
(1)  
CL  
t
4
5
OUTPUT PARAMETERS  
____  
____  
____  
____  
CD  
t
Clock High to Valid Data  
4.5  
5
6
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
____  
CDC  
t
Clock High to Data Change  
Clock High to Output Active  
Clock High to Data High-Z  
1.5  
0
1.5  
0
2
0
2
0
(2)  
____  
____  
____  
____  
CLZ  
t
(2)  
CHZ  
t
1.5  
4
1.5  
5
2
5
2
6
____  
____  
____  
____  
OE  
t
Output Enable Access Time  
Output Enable Low to Data Active  
Output Enable High to Data High-Z  
4
5
5
6
(2)  
(2)  
____  
____  
____  
____  
OLZ  
t
0
0
0
0
____  
____  
____  
____  
OHZ  
t
4
4
5
6
SETUP TIMES  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
SA  
t
Address Setup Time  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
SS  
t
Address Status Setup Time  
Data in Setup Time  
SD  
t
SW  
t
Write Setup Time  
SAV  
t
Address Advance Setup Time  
Chip Enable/Select Setup Time  
SC  
t
HOLD TIMES  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
HA  
t
Address Hold Time  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
HS  
t
Address Status Hold Time  
Data In Hold Time  
HD  
t
HW  
t
Write Hold Time  
HAV  
t
Address Advance Hold Time  
Chip Enable/Select Hold Time  
HC  
t
SLEEP MODE AND CONFIGURATION PARAMETERS  
____  
____  
____  
____  
____  
____  
____  
____  
____  
ZZPW  
t
ZZ Pulse Width  
100  
100  
34  
100  
100  
40  
100  
100  
50  
100  
100  
50  
ns  
ns  
(3)  
ZZR  
t
ZZ Recovery Time  
Configuration Set-up Time  
(4)  
CFG  
t
ns  
3619 tbl 15  
NOTES:  
1. Measured as HIGH above 2.0V and LOW below 0.8V.  
2. Transition is measured ±200mV from steady-state.  
3. Device must be deselected when powered-up from sleep mode.  
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.  
5. The 71V632SA4 speed grade corresponds to a tCD of 4.5ns.  
6. 0°C to +70°C temperature range only.  
6.42  
9
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Pipelined Read Cycle(1,2)  
6.1402  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)  
6.42  
11  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)  
.
6.1422  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)  
6.42  
13  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)  
6.1442  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Non-Burst Read Cycle Timing Waveform  
CLK  
ADSP  
ADSC  
Av  
Aw  
Ax  
Ay  
Az  
ADDRESS  
GW, BWE, BWx  
CE, CS1  
CS0  
OE  
(Av)  
(Aw)  
(Ax)  
(Ay)  
DATAOUT  
,
3619 drw 11  
NOTES:  
1. ZZ input is LOW, ADV is HIGH and LBO is Don’t Care for this cycle.  
2. (AX) represents the data for address AX, etc.  
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.  
6.42  
15  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Non-Burst Write Cycle Timing Waveform  
CLK  
ADSP  
ADSC  
Av  
Aw  
Ax  
Ay  
Az  
ADDRESS  
GW  
CE, CS1  
0
CS  
(Av)  
(Aw)  
(Ax)  
(Ay)  
(Az)  
IN  
DATA  
,
3619 drw 12  
NOTES:  
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don’t Care for this cycle.  
2. (AX) represents the data for address AX, etc.  
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.  
4. For write cycles, ADSP and ADSC have different limitations.  
6.1462  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
100-pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline  
6.42  
17  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
OrderingInformation  
IDT 71V632  
X
S
PF  
X
Process/  
Temperature  
Range  
Device  
Type  
Power  
Speed  
Package  
Blank Commercial (0°C to +70°C)  
I
Industrial (–40°C to +85°C)  
PF  
Plastic Thin Quad Flatpack, 100 pin (PK100-1)  
A4*  
5
6
Synchronous Access Time in nanoseconds  
7
* Commercial only.  
PART NUMBER  
71V632SA4PF  
71V632S5PF  
71V632S6PF  
71V632S7PF  
SPEED IN MEGAHERTZ  
117 MHz  
tCD PARAMETER  
CLOCK CYCLE TIME  
4.5 ns  
5 ns  
8.5 ns  
10 ns  
12 ns  
15 ns  
100 MHz  
83 MHz  
6 ns  
66 MHz  
7 ns  
3619 drw 13  
6.1482  
IDT71V632, 64K x 32, 3.3V Synchronous SRAM  
with Pipelined Outputs and Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
DatasheetDocumentHistory  
9/9/99  
Updatedtonewformat  
Revisedspeedofferingsto66–117MHz  
Addednon-burstreadandwritecycletimingdiagrams  
AddedDatasheetDocumentHistory  
Pg. 1, 8, 9, 17  
Pg. 15, 16  
Pg. 18  
09/30/99  
04/04/00  
08/09/00  
Pg. 1, 4, 8, 9, 17  
Pg. 17  
Addedindustrialtemperaturerangeofferings  
Added100pinTQFPpackageDiagramOutline  
Notrecommendedfornewdesigns  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
for Tech Support:  
sramhelp@idt.com  
800-544-7726, x4033  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
6.42  
19  

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