71V416S15PHGI8 [IDT]
3.3V CMOS Static RAM;
| 型号： | 71V416S15PHGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS Static RAM PC 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V416S
IDT71V416L
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Features
Description
◆
256K x 16 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise.
Equal access and cycle times
TheIDT71V416isa4,194,304-bithigh-speedStaticRAMorganized
as 256K x 16. It is fabricated using high-performance, high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speed memory needs.
◆
◆
– CommercialandIndustrial:10/12/15ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
◆
◆
TheIDT71V416hasanoutputenablepinwhichoperatesasfastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71V416areLVTTL-compatibleandoperationisfroma
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring
no clocks or refresh for operation.
◆
◆
◆
◆
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mmx9mmpackage.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mmpackage.
◆
Green parts available, see ordering information
FunctionalBlockDiagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 - A17
High
8
8
8
8
Byte
I/O 15
I/O 8
Output
Chip
Select
Buffer
Buffer
CS
High
Byte
Write
Sense
Amps
and
Write
Drivers
4,194,304-bit
Memory
Array
Buffer
16
Write
Enable
Buffer
Low
Byte
8
8
8
8
WE
I/O 7
I/O 0
Output
Buffer
Low
Byte
Write
Buffer
BHE
BLE
Byte
Enable
Buffers
3624 drw 01
NOVEMBER 2016
1
©2016 Integrated Device Technology, Inc.
DSC-3624/11
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations - SOJ/TSOP
Pin Configurations - 48 BGA
71V416BE
A
0
1
2
A
17
16
44
43
BE48
A
1
A
48- BGA
A
2
3
3
4
5
6
A15
OE
42
41
40
1
2
3
4
5
6
A
A
4
BHE
BLE
A
B
C
D
E
F
A
A
A
0
3
5
A
1
A
2
NC
BLE
OE
CS
39
38
I/O
I/O
I/O
0
1
2
I/O15
I/O14
I/O13
I/O12
7
8
9
I/O0
A
A
A
4
I/O8
BHE
CS
37
36
35
34
I/O1
I/O2
I/O3
I/O4
I/O5
6
7
I/O10
I/O11
I/O12
I/O13
WE
I/O9
I/O
3
10
11
12
13
14
15
16
17
18
19
20
21
22
PHG44
PBG44
VDD
VSS
V
V
SS
DD
A
17
V
V
DD
SS
33
32
31
30
VDD
VSS
I/O11
I/O10
I/O
I/O
I/O
I/O
4
5
6
7
NC
A
A
A
A
16
15
13
10
I/O
I/O
NC*
9
I/O
6
7
A
A
14
12
I/O14
I/O15
29
28
27
26
25
24
23
8
WE
A
A
G
H
I/O
NC
A
14
13
12
5
A
6
7
NC
A
8
A
9
A
11
NC
A
A
A11
3624 tbl 11
A
A
8
9
A10
Top View
3624 drw 02
*Pin 28 can either be a NC or connected to Vss
Top View
SOJCapacitance
(TA = +25°C, f = 1.0MHz)
PinDescriptions
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
A
0
- A17
Address Inputs
Chip Select
Input
Input
Input
Input
Input
Input
I/O
CS
C
IN
V
7
8
pF
Write Enable
WE
OE
C
I/O
V
pF
3624 tbl 02
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
BHE
BLE
48BGACapacitance
(TA = +25°C, f = 1.0MHz)
I/O - I/O15
0
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
VDD
Pwr
CIN
V
6
7
pF
VSS
Ground
Gnd
3624 tbl 01
CI/O
V
pF
3624 tbl 02b
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
2
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupply
Voltage
Symbol
Rating
Value
Unit
V
V
DD
Supply Voltage Relative to VSS
Terminal Voltage Relative to
-0.5 to +4.6
-0.5 to VDD+0.5
Grade
Commercial
Industrial
Temperature
0OC to +70OC
–40OC to +85OC
V
SS
VDD
V
V
IN,
V
OUT
V
SS
0V
0V
See Below
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
oC
oC
W
See Below
T
STG
-55 to +125
3624 tbl 05
P
T
1
I
OUT
DC Output Current
50
mA
3624 tbl 04
RecommendedDCOperating
Conditions
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
0
Unit
V
V
DD
SS
IH
IL
V
V
____
V
DD+0.3(1)
V
Input High Voltage
Input Low Voltage
2.0
V
-0.3(2)
____
V
0.8
V
3624 tbl 06
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Truth Table(1)
I/O0-I/O
7
I/O8-I/O15
High-Z
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
CS
H
L
OE
X
L
WE
BLE
X
BHE
X
X
High-Z
H
H
H
L
L
H
L
DATAOUT
High-Z
High-Z
L
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
L
DATAOUT
DATAIN
DATAIN
High-Z
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
L
L
H
X
DATAIN
High-Z
L
H
X
X
High-Z
L
H
H
High-Z
High-Z
3624 tbl 03
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.42
3
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V416
Symbol
Parameter
Input Leakage Current
Test Conditions
Min.
___
Max.
Unit
µA
µA
V
|ILI
|
V
CC = Max., VIN =
V
SS to VDD
5
5
___
___
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
DD = Max., CS = VIH, VOUT = VSS to VDD
VOL
I
I
OL = 8mA, VDD = Min.
OH = -4mA, VDD = Min.
0.4
___
VOH
2.4
V
3624 tbl 07
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V416S/L10
Com'l. Ind.
200 200
71V416S/L12
Com'l. Ind.
180 180
71V416S/L15
Com'l.
170
160
50
Ind.
170
160
50
Symbol
Parameter
Unit
ICC
Dynamic Operating Current
S
L
S
L
S
L
mA
(4)
(4)
CS < VLC, Outputs Open, VDD = Max., f = fMAX
180
70
180
70
50
20
10
170
60
170
60
ISB
Dynamic Standby Power Supply Current
mA
CS > VHC, Outputs Open, VDD = Max., f = fMAX
50
45
45
40
40
ISB1
Full Standby Power Supply Current (static)
20
20
20
20
20
mA
CS > VHC, Outputs Open, VDD = Max., f = 0(4)
10
10
10
10
10
3624 tbl 08
NOTES:
IDT71V416S/71V416L
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
AC Test Loads
3.3V
320
+1.5V
Ω
50Ω
OUT
DATA
I/O
Z0 = 50Ω
5pF*
350Ω
30pF
3624 drw 03
3624 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
5
4
3
•
AC Test Conditions
∆tAA,
tACS
(Typical, ns)
Input Pulse Levels
GND to 3.0V
1.5ns
•
•
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
2
1
•
1.5V
•
•
•
1.5V
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
3624 drw 05
Figures 1,2 and 3
3624 tbl 09
Figure 3. Output Capacitive Derating
6.42
4
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10
71V416S/L12
71V416S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
t
t
t
t
t
t
t
t
t
t
t
RC
Read Cycle Time
10
____
12
____
15
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Address Access Time
Chip Select Access Time
10
12
15
____
____
____
ACS
10
____
12
____
15
____
(1)
CLZ
CHZ
OE
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
4
____
4
____
4
____
(1)
5
6
7
____
____
____
5
____
6
____
7
____
(1)
OLZ
0
____
0
____
0
____
(1)
OHZ
OH
BE
5
____
6
____
7
____
4
____
4
____
4
____
5
____
6
____
7
____
(1)
BLZ
BHZ
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
0
____
0
____
0
____
(1)
5
6
7
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
t
t
t
t
WC
AW
CW
BW
AS
Write Cycle Time
10
8
12
8
15
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
8
8
8
8
0
0
WR
WP
DW
DH
OW
Address Hold from End of Write
Write Pulse Width
0
0
0
8
8
10
7
Data Valid to End of Write
Data Hold Time
5
6
0
0
0
(1)
(1)
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
3
____
3
____
3
____
WHZ
6
7
7
ns
3624 tbl 10
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
3624 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC
ADDRESS
t
OH
tAA
OE
(3)
tOHZ
t
OE
(3)
tOLZ
CS
(2)
tACS
(3)
(3)
tCHZ
t
CLZ
BLE
BHE,
(2)
t
BE
(3)
(3)
BHZ
t
tBLZ
DATAOUT
DATAOUT VALID
3624 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
(2)
(5)
(5)
tCW
t
CHZ
tBW
BHE
,
BLE
WE
tWR
t
BHZ
tWP
tAS
(5)
tWHZ
(5)
tOW
PREVIOUS DATA VALID (3)
DATA VALID
DATAOUT
DATAIN
tDH
t
DW
DATAIN VALID
3624 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.42
6
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)
t
WC
ADDRESS
CS
tAW
(2)
tAS
tCW
tBW
BHE, BLE
WE
tWP
tWR
DATAOUT
DATAIN
tDH
t
DW
DATAIN VALID
3624 drw 09
Timing Waveform of Write Cycle No. 3
(BHE, BLE Controlled Timing)(1,3)
tWC
ADDRESS
CS
tAW
(2)
tCW
tAS
tBW
BHE, BLE
t
WP
tWR
WE
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
3624 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.42
7
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
OrderingInformation
X
X
71V416
X
XX
XXX
X
Process/
Temperature
Range
Device
Type
Power Speed
Package
Blank
8
Tube or Tray
Tape and Reel
Blank Commercial (0°C to +70°C)
I
Industrial (-40°C to +85°C)
Green
G
Y
PH
BE
44-pin, 400-mil SOJ (PBG44)
44-pin TSOP Type II (PHG44)
48 Ball Grid Array (BE48, BEG48)
10
12
15
Speed in nanoseconds
Standard Power
Low Power
S
L
3624 drw 11a
OrderablePartInformation
Speed
(ns)
Pkg.
Pkg.
Type
Temp.
Grade
Speed
Pkg.
Pkg.
Type
Temp.
Grade
Orderable Part ID
Orderable Part ID
Code
(ns)
Code
10
71V416L10BE
BE48
BEG48
BEG48
PHG44
PHG44
PHG44
PHG44
PBG44
PBG44
BE48
CABGA
CABGA
CABGA
TSOP
TSOP
TSOP
TSOP
SOJ
C
C
C
C
C
I
10
71V416S10BE
BE48
BE48
CABGA
CABGA
CABGA
CABGA
TSOP
TSOP
TSOP
TSOP
SOJ
C
C
C
C
C
C
I
71V416L10BEG
71V416L10BEG8
71V416L10PHG
71V416L10PHG8
71V416L10PHGI
71V416L10PHGI8
71V416L10YG
71V416S10BE8
71V416S10BEG
71V416S10BEG8
71V416S10PHG
71V416S10PHG8
71V416S10PHGI
71V416S10PHGI8
71V416S10YG
BEG48
BEG48
PHG44
PHG44
PHG44
PHG44
PBG44
PBG44
BE48
I
C
C
C
C
C
C
I
I
71V416L10YG8
71V416L12BE
SOJ
C
C
C
C
C
C
I
12
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
TSOP
TSOP
TSOP
TSOP
SOJ
71V416S10YG8
71V416S12BE
SOJ
71V416L12BE8
71V416L12BEG
71V416L12BEG8
71V416L12BEGI
71V416L12BEGI8
71V416L12BEI
71V416L12BEI8
71V416L12PHG
71V416L12PHG8
71V416L12PHGI
71V416L12PHGI8
71V416L12YG
BE48
12
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
TSOP
TSOP
TSOP
TSOP
SOJ
BEG48
BEG48
BEG48
BEG48
BE48
71V416S12BE8
71V416S12BEG
71V416S12BEG8
71V416S12BEI
71V416S12BEI8
71V416S12PHG
71V416S12PHG8
71V416S12PHGI
71V416S12PHGI8
71V416S12YG
BE48
BEG48
BEG48
BE48
I
I
BE48
I
BE48
I
PHG44
PHG44
PHG44
PHG44
PBG44
PBG44
PBG44
PBG44
C
C
I
PHG44
PHG44
PHG44
PHG44
PBG44
PBG44
PBG44
PBG44
C
C
I
I
I
C
C
I
C
C
I
71V416L12YG8
71V416L12YGI
71V416L12YGI8
SOJ
71V416S12YG8
71V416S12YGI
71V416S12YGI8
SOJ
SOJ
SOJ
SOJ
I
SOJ
I
3624 tbl 12a
3624 tbl 12b
6.42
8
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
OrderablePartInformation(con't)
Speed
(ns)
Pkg.
Pkg.
Type
Temp.
Grade
Speed
(ns)
Pkg.
Pkg.
Type
Temp.
Grade
Orderable Part ID
Orderable Part ID
Code
Code
15
71V416S15BE
BE48
BE48
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
TSOP
TSOP
TSOP
TSOP
SOJ
C
C
C
C
I
15
71V416L15BE
BE48
BE48
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
CABGA
TSOP
C
C
C
C
I
71V416S15BE8
71V416S15BEG
71V416S15BEG8
71V416S15BEGI
71V416S15BEGI8
71V416S15BEI
71V416S15BEI8
71V416S15PHG
71V416S15PHG8
71V416S15PHGI
71V416S15PHGI8
71V416S15YG
71V416L15BE8
71V416L15BEG
71V416L15BEG8
71V416L15BEGI
71V416L15BEGI8
71V416L15BEI
71V416L15BEI8
71V416L15PHG
71V416L15PHG8
71V416L15PHGI
71V416L15PHGI8
71V416L15YGI
71V416L15YGI8
BEG48
BEG48
BEG48
BEG48
BE48
BEG48
BEG48
BEG48
BEG48
BE48
I
I
I
I
BE48
I
BE48
I
PHG44
PHG44
PHG44
PHG44
PBG44
PBG44
PBG44
PBG44
C
C
I
PHG44
PHG44
PHG44
PHG44
PBG44
PBG44
C
C
I
TSOP
I
TSOP
C
C
I
TSOP
I
71V416S15YG8
71V416S15YGI
71V416S15YGI8
SOJ
SOJ
I
SOJ
SOJ
I
SOJ
I
3624 tbl 12c
3624 tbl 12d
DatasheetDocumentHistory
08/5/99
Updatedtonewformat
Pg 6
RevisedfootnotefortCW onWriteCycleNo. 1diagram
AddedIndustrialtemperaturerangeoffering
AddedDatasheetDocumentHistory
08/31/99
Pg. 1–9
Pg. 9
Pg. 6
03/24/00
08/10/00
ChangednotetoWritecycleNo.1accordingtofootnotes
Add 48 ball grid array package offering
Pg. 1
Pg. 2
Pg. 8
Pg. 8
Pg. 8
Correct TTL to LVTTL
09/11/ 02
11/26/02
07/31/03
10/13/03
UpdatedTBDinformationforthe48BGACapacitancetable
Added"DieRevision"toorderinginformation
Updatednote, L10speedgradecommercialtemperatureonlyandupdateddiesteppingfromYFtoY.
Updatedorderinginformation.Referto71V416YSand71V416YLdatasheetforlatestgenerationdie
step.
01/30/04
02/01/13:
Pg. 8
Pg. 1
Pg. 8
Pg. 2
Added"Restrictedhazardoussubstancedevice"toorderinginformation
RemovedIDTreferencetofabrication
RemoveddierevisioninformationfromtheOrderingInformation
Updatedtheorderablepartnumbersforallpinconfigurations
Addedthecorrectedconfigurationtitleforthe48BGApinconfiguration
ReformattedSOJ/TSOPpins&labels. Nochangeinfunctionality. Itremainsthesame
UpdatedtheIndustrialvaluesandthefootnotereferencesintheDCElectricaltable
UpdatedthefootnotereferencesintheACElectricaltable
11/18/16:
Pg.4
Pg. 5
Pg. 8
Pg. 8-9
UpdatedtheorderablepartnumbersintheOrderingInformation
Addedorderablepartinformationtables
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