71V016SA20BFG8 [IDT]
3.3V CMOS Static RAM;
| 型号： | 71V016SA20BFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS Static RAM 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V016SA
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
Description
◆
64K x 16 advanced high-speed CMOS Static RAM
TheIDT71V016isa1,048,576-bithigh-speedStaticRAMorganized
as64Kx16.Itisfabricatedusinghigh-perfomance,high-reliabilityCMOS
technology.Thisstate-of-the-arttechnology,combinedwithinnovative
circuitdesigntechniques,providesacost-effectivesolutionforhigh-speed
memoryneeds.
◆
Equal access and cycle times
— Commercial:10/12/15/20ns
— Industrial:10/12/15/20ns
One Chip Select plus one Output Enable pin
◆
◆
Bidirectional data inputs and outputs directly
TheIDT71V016hasanoutputenablepinwhichoperatesasfastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71V016areLVTTLcompatibleandoperationisfroma
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring
no clocks or refresh for operation.
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
◆
◆
◆
◆
Available in 44-pin Plastic SOJ, 44-pin TSOP, and
TheIDT71V016ispackagedinaJEDECstandard44-pinPlasticSOJ,
a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
48-Ball Plastic FBGA packages
Functional Block Diagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 – A15
I/O15
High
8
8
Chip
Enable
Buffer
Byte
CS
I/O
Buffer
I/O8
Sense
Amps
and
Write
Drivers
16
64K x 16
Memory
Array
Write
Enable
Buffer
WE
I/O7
I/O0
Low
Byte
I/O
8
8
Buffer
BHE
BLE
Byte
Enable
Buffers
3834 drw 01
AUGUST 2013
1
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3834/13
©
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
1
2
3
4
5
6
A
B
C
D
E
F
A
0
3
5
A
1
A
2
NC
BLE
OE
A
4
1
A
A
A
5
6
7
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
A2
3
I/O
I/O
8
9
A
A
A
A
A
4
I/O
I/O
0
BHE
I/O10
I/O11
I/O12
I/O13
NC
CS
A
1
4
OE
A0
5
BHE
BLE
I/O15
I/O14
I/O13
I/O12
6
7
I/O
I/O
1
2
CS
I/O
I/O
I/O
6
0
7
VSS
NC
NC
3
VDD
1
8
2
9
VDD
NC
I/O
4
5
VSS
I/O3
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
V
DD
V
V
SS
DD
VSS
I/O14
I/O15
NC
A14
A15
A13
A10
I/O
I/O
I/O
6
7
I/O
I/O
I/O
I/O
WE
4
I/O11
I/O10
5
G
H
A12
WE
6
I/O
I/O
9
8
7
A
8
A9
A
11
NC
NC
A15
A14
A13
A12
A
A
A
A
8
3834 tbl 02a
FBGA (BF48-1)
Top View
9
10
11
NC
NC
Pin Description
3834 drw 02
SOJ/TSOP
Top View
Truth Table(1)
CS
H
L
OE
X
L
WE
X
BLE
BHE
X
I/O
0
-I/O
7
I/O
8
-I/O15
Function
Deselected – Standby
X
L
High-Z
High-Z
High-Z
H
H
H
L
H
L
DATAOUT
High-Z
Low Byte Read
High Byte Read
Word Read
L
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
L
DATAOUT
DATAIN
DATAIN
High-Z
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
L
L
H
X
H
DATAIN
High-Z
L
H
X
X
High-Z
L
H
High-Z
High-Z
3834 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
2
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage
Symbol
Rating
Value
–0.5 to +4.6
–0.5 to VDD+0.5
–55 to +125
–55 to +125
1.25
Unit
V
V
DD
Supply Voltage Relative to VSS
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
SS
VDD
V
IN, VOUT Terminal Voltage Relative to VSS
V
0V
0V
See Below
TBIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
oC
oC
W
See Below
T
P
STG
3834 tbl 04
T
I
OUT
DC Output Current
50
mA
Recommended DC Operating
Conditions
3834 tbl 03
NOTE:
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
Symbol
Parameter
Min.
3.15
3.0
Typ.
Max.
Unit
V
(1)
V
DD
DD
Supply Voltage
3.3
3.6
(2)
V
Supply Voltage
Ground
3.3
3.6
V
Vss
0
0
0
V
Capacitance
____
V
IH
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(3)
0.8
V
(TA = +25°C, f = 1.0MHz, SOJ package)
–0.3(4)
V
____
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
V
IL
Symbol
3834 tbl 05
C
IN
V
6
7
pF
NOTES:
1. For 71V016SA10 only.
2. For all speed grades except 71V016SA10.
C
I/O
V
pF
3834 tbl 06
3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V016SA
Symbol
Parameter
Input Leakage Current
Test Condition
DD = Max., VIN = VSS to VDD
Min.
Max.
Unit
µA
µA
V
___
___
___
|ILI|
V
V
5
5
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
DD = Max., CS = VIH, VOUT = VSS to VDD
VOL
I
I
OL = 8mA, VDD = Min.
OH = –4mA, VDD = Min.
0.4
__ _
VOH
2.4
V
3834 tbl 07
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V016SA10
71V016SA12
71V016SA15
71V016SA20
Com'l Ind'l Com'l
Ind'l
160
--
Com'l
130
Ind'l
Com'l
120
Ind'l
120
--
Symbol
Parameter
Dynamic Operating Current
Unit
Max.
160
65
170
--
150
60
130
--
mA
ICC
(3)
Typ.(4)
55
50
CS ≤ VLC, Outputs Open, VDD = Max., f = fMAX
Dynamic Standby Power Supply Current
mA
I
SB
45
10
50
10
40
10
45
10
35
10
35
10
30
10
30
10
(3)
CS ≥ VHC, Outputs Open, VDD = Max., f = fMAX
Full Standby Power Supply Current (static)
CS ≥ VHC, Outputs Open, VDD = Max., f = 0(3)
mA
ISB1
3834 tbl 08
NOTES:
1. Allvaluesaremaximumguaranteedvalues.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are based on characterization data for H step only measured at 3.3V, 25°C and with equal read and write cycles.
3
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3834 tbl 09
AC Test Loads
3.3V
+1.5V
320Ω
50Ω
OUT
DATA
Z0 = 50Ω
I/O
5pF*
350Ω
30pF
3834 drw 03
3834 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
•
ΔtAA,
t
ACS
5
4
3
2
1
(Typical, ns)
•
•
•
•
•
•
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
3834 drw 05
Figure 3. Output Capacitive Derating
4
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V016SA10
71V016SA12
71V016SA15
71V016SA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
20
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
10
12
15
20
____
____
____
____
t
Chip Select Access Time
Chip Select Low to Output in Low-Z
10
12
15
20
____
____
____
____
(1)
CLZ
4
4
5
5
t
____
____
____
____
(1)
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
t
CHZ
____
____
____
____
tOE
5
6
7
8
____
____
____
____
(1)
(1)
0
0
0
0
tOLZ
____
____
____
____
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
ns
t
OHZ
OH
BE
t
4
—
4
—
4
—
4
—
____
t
—
5
—
6
—
7
8
____
____
____
____
(1)
0
0
0
0
tBLZ
(1)
____
____
____
____
Byte Enable High to Output in High-Z
5
6
6
8
ns
tBHZ
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
BW
AS
WR
WP
DW
DH
Write Cycle Time
10
7
12
8
15
10
10
10
0
20
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
t
7
8
t
7
8
t
0
0
t
Address Hold from End of Write
Write Pulse Width
0
0
0
0
t
7
8
10
7
12
9
t
Data Valid to End of Write
Data Hold Time
5
6
t
0
0
0
0
____
____
____
____
(1)
Write Enable High to Output in Low-Z
3
3
3
3
tOW
____
____
____
____
(1)
WHZ
Write Enable Low to Output in High-Z
5
6
6
8
ns
t
3834 tbl 10
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
3834 drw 06
2. Deviceiscontinuouslyselected,CSisLOW.
3. OE, BHE, and BLE are LOW.
5
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC
ADDRESS
OE
tAA
t
OH
(3)
tOHZ
tOE
(3)
tOLZ
CS
(2)
t
ACS
(3)
(3)
(3)
t
CHZ
t
CLZ
BLE
BHE,
(2)
t
BE
(3)
t
BHZ
t
BLZ
DATAOUT
DATA OUTVALID
3834 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. AddressmustbevalidpriortoorcoincidentwiththelaterofCS, BHE,or BLE transitionLOW;otherwisetAA isthelimitingparameter.
3. Transitionismeasured±200mVfromsteadystate.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
t
AW
CS
(2)
(5)
(5)
t
CW
t
CHZ
tBW
BHE BLE
,
tWR
t
BHZ
t
WP
WE
tAS
(5)
t
WHZ
(5)
t
OW
(3)
DATAOUT
DATAIN
PREVIOUS DATA VALID
DATA VALID
tDH
t
DW
DATAIN VALID
3834 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuously HIGH. If during a WEcontrolled write cycle OEis LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OEis HIGH during aWE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. Duringthisperiod, I/Opinsareintheoutputstate, andinputsignalsmustnotbeapplied.
4. Ifthe CSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
t
WC
ADDRESS
t
AW
CS
(2)
t
AS
tCW
t
BW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
3834 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
t
WC
ADDRESS
tAW
CS
(2)
t
CW
tAS
tBW
BHE, BLE
t
WP
tWR
WE
DATAOUT
DATAIN
tDH
t
DW
DATAIN VALID
3834 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuously HIGH. If during a WEcontrolled write cycle OEis LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OEis HIGH during aWE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. Duringthisperiod, I/Opinsareintheoutputstate, andinputsignalsmustnotbeapplied.
4. Ifthe CSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
7
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
8
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
01/07/00
Updatedtonewformat
Pg. 1, 3, 5, 8
Pg. 2
Pg. 6
Pg. 7
Pg. 9
AddedIndustrialTemperaturerangeofferings
Numbered I/Os and address pins on FBGA Top View
RevisedfootnotesonWriteCycleNo. 1diagram
Revised footnotes on Write Cycle No. 2 and No. 3 diagrams
AddedDatasheetDocumentHistory
08/30/00
Pg. 3
Tighten ICC and ISB.
Pg. 5
Tighten tCLZ, tCHZ, tOHZ, tBHZ and tWHZ
08/22/01
06/20/02
01/30/04
09/27/06
02/14/07
06/26/07
10/13/08
10/11/11
08/13/13
Pg. 8
Pg. 8
Pg. 8
Pg. 8
Pg.8
Pg.3
Pg.8
Pg.1,8
Pg.1,3,5,8
Removed footnote "available in 15ns and 20ns only"
Addedtapeandreelfieldtoorderinginformation
Added"Restrictedhazardoussubstancedevice"toorderinginformation.
Correctedorderinginformation,changedpositionofIandG.
AddedHstepgenerationtodatasheetorderinginformation.
ChangedtypicalparametersforICC,DCelectricalcharacteristicstable.
Removed "IDT" from orderable part number
UpdateddatasheetwithremovalofObsoleteHSApartnumber.
Added10nsforIndustrialTemperaturerangeofferings.
for Tech Support:
sramhelp@idt.com
408-284-4532
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9
相关型号：
71V016SA20BFIG
Standard SRAM, 64KX16, 20ns, CMOS, PBGA48, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, FBGA-48
IDT
71V016SA20BFIG8
Standard SRAM, 64KX16, 20ns, CMOS, PBGA48, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, FBGA-48
IDT
©2020 ICPDF网 联系我们和版权申明