71256TTSA15YGI
更新时间：2024-09-18 14:49:47
品牌：IDT
描述：Standard SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOJ-28
概述
规格参数
数据手册71256TTSA15YGI 概述
Standard SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOJ-28 SRAM
71256TTSA15YGI 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOJ |
| 包装说明： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOJ-28 | 针数： | 28 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.41 | 风险等级： | 5.63 |
| 最长访问时间： | 15 ns | I/O 类型： | COMMON |
| JESD-30 代码： | R-PDSO-J28 | JESD-609代码： | e3 |
| 长度： | 17.9324 mm | 内存密度： | 262144 bit |
| 内存集成电路类型： | STANDARD SRAM | 内存宽度： | 8 |
| 功能数量： | 1 | 端子数量： | 28 |
| 字数： | 32768 words | 字数代码： | 32000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 32KX8 |
| 输出特性： | 3-STATE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOJ | 封装等效代码： | SOJ28,.34 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 并行/串行： | PARALLEL | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 3.556 mm | 最大待机电流： | 0.015 A |
| 最小待机电流： | 4.5 V | 子类别： | SRAMs |
| 最大压摆率： | 0.15 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | MATTE TIN |
| 端子形式： | J BEND | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 7.5184 mm | Base Number Matches： | 1 |
71256TTSA15YGI 数据手册
通过下载71256TTSA15YGI数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CMOS Static RAM
256K (32K x 8-Bit)
IDT71256SA/TTSA
Features
Description
◆
32K x 8 advanced high-speed CMOS static RAM
TheIDT71256SA isa262,144-bithigh-speedStaticRAMorganized
as32Kx8.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOS technology. This state-of-the-art technology, combined with
innovativecircuitdesigntechniques,providesacost-effectivesolutionfor
high-speedmemoryneeds.
◆
Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
Equal access and cycle times
◆
– CommercialandIndustrial:12/15/20/25ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
◆
TheIDT71256SAhasanoutputenablepinwhichoperatesasfastas
6ns,withaddress accesstimesasfastas12ns. Allbidirectionalinputsand
outputsoftheIDT71256SA areTTL-compatibleandoperationisfroma
single5Vsupply. Fullystaticasynchronouscircuitryisused,requiringno
clocksorrefreshforoperation.
◆
TTL-compatible
Low power consumption via chip deselect
Commercial product available in 28-pin 300- and 600-mil
◆
◆
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
Industrial product available in 28-pin 300 mil Plastic SOJ
TheIDT71256SAispackagedin28-pin300-and600-milPlasticDIP,
28-pin300milPlasticSOJandTSOP.
◆
and TSOP packages
FunctionalBlockDiagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
262,144-BIT
MEMORY
ARRAY
ADDRESS
DECODER
A10
A11
A12
A13
A14
,
8
8
I/O0 - I/O
7
I/O CONTROL
2948 drw 01
CS
WE
OE
CONTROL
LOGIC
OCTOBER 2008
1
DSC-2948/09
©2007IntegratedDeviceTechnology,Inc.
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
PinConfigurations
Symbol
Rating
Value
Unit
1
V
WE
CC
28
A
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
14
12
V
CC
Supply Voltage
-0.5 to +7.0
V
2
3
27
26
25
24
Relative to GND
7
6
5
4
3
2
1
0
A
A
13
8
4
VTERM
Terminal Voltage
Relative to GND
-0.5 to VCC+0.5
V
5
A
9
6
23
22
A11
TBIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
1.0
oC
oC
W
SO28-5
P28-2
P28-1
7
OE
TSTG
8
21
20
A10
9
CS
P
T
10
11
12
13
14
19
18
I/O
I/O
I/O
I/O
I/O
7
0
1
2
6
5
4
3
IOUT
DC Output Current
50
mA
17
16
15
2948 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
GND
,
2948 drw 02
DIP/SOJ
Top View
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A10
CS
I/O
I/O
I/O
I/O
A11
Truth Table(1,2)
7
A9
6
A8
Function
DATAOUT Read Data
DATAIN Write Data
High-Z Outputs Disabled
High-Z Deselected - Standby (ISB
High-Z Deselected - Standby (ISB1)
I/O
CS
OE
WE
A13
5
WE
4
L
L
H
VCC
I/O3
GND
SO28-8
A14
L
X
H
X
X
L
2
A12
I/O
I/O
I/O
2
,
3
A
A
A
A
A
7
6
5
4
3
1
L
H
4
0
5
A0
A1
A2
H
X
)
6
7
8
(3)
HC
V
X
2948 drw 02a
2948 tbl 03
NOTES:
TSOP
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC –0.2V.
3. Other inputs ≥VHC or ≤VLC.
Top View
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Parameter
Supply Voltage
GND Ground
Min. Typ.
Max.
5.5
0
Unit
V
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
Vcc
V
CC
4.5
0
5.0
0V
4.5V ± 5.5V
4.5V ± 5.5V
0
V
0V
____
V
IH
Input High Voltage
Input Low Voltage
2.2
V
CC +0.5
V
2948 tbl 01
VIL
-0.5(1)
0.8
V
____
2948 tbl 04
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
2
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
IDT71256SA
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
CC = Max., VIN = GND to VCC
CC = Max., CS = VIH, VOUT = GND to VCC
OL = 8mA, VCC = Min.
OH = -4mA, VCC = Min.
Min.
Max.
5
Unit
µA
µA
V
___
|
V
___
___
|
V
5
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
2948 tbl 05
DCElectricalCharacteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)
Symbol
Parameter
71256SA12
71256SA15
71256SA20
71256SA25
Unit
ICC
Dynamic Operating Current
CS < VIL, Outputs Open, VCC = Max., f = fMAX
160
150
145
145
mA
(2)
I
SB
Standby Power Supply Current (TTL Level)
CS > VIH, Outputs Open, VCC = Max., f = fMAX
50
15
40
15
40
15
40
15
mA
mA
(2)
ISB1
Standby Power Supply Current (CMOS Level)
CS > VHC, Outputs Open, VCC = Max., f = 0(2),
VIN < VLC or VIN > VHC
2948 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Capacitance
AC Test Conditions
Input Pulse Levels
(TA = +25°C, f = 1.0MHz, SOJ package)
GND to 3.0V
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max.
Unit
Input Rise/Fall Times
3ns
1.5V
CIN
V
7
pF
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
CI/O
V
7
pF
2948 tbl 08
See Figures 1 and 2
NOTE:
2948 tbl 07
1. This parameter is guaranteed by device characterization, but not production
tested.
5V
5V
480Ω
480Ω
OUT
DATA
OUT
DATA
5pF*
255Ω
30pF*
255Ω
.
,
2948 drw 03
2948 drw 04
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
6.42
3
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%)
71256SA12
71256SA15
71256SA20
Min. Max.
71256SA25
Min. Max.
Min. Max.
Min.
Max.
Symbol
Parameter
Unit
Read Cycle
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
12
15
20
25
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
12
15
20
25
____
____
____
____
t
Chip Select Access Time
12
15
20
25
____
____
____
____
(1)
CL Z
Chip Select to Output in Low-Z
Chip Selectto Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
4
4
4
4
t
(1)
0
6
0
7
0
10
0
11
ns
ns
ns
ns
ns
ns
ns
tCHZ
____
____
____
____
tOE
6
7
10
11
(1)
(1)
____
____
____
____
0
0
3
0
0
3
0
0
3
0
0
3
tOLZ
6
6
8
10
tOHZ
____
____
____
____
tOH
____
____
____
____
(1)
PU
0
0
0
0
t
____
____
____
____
(1)
PD
12
15
20
25
t
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
12
9
9
0
8
0
6
0
4
15
10
10
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
10
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
t
7
11
0
13
0
t
0
(1)
OW
____
____
____
____
Output Active from End-of-Write
4
4
4
t
(1)
WHZ
Write Enable to Output in High-Z
0
6
0
6
0
10
0
11
ns
t
2948 tbl 09
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
4
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tAA
OE
CS
tOE
(5)
tOLZ
(5)
(3)
tOHZ
tACS
(5)
(5)
tCLZ
tCHZ
HIGH IMPEDANCE
DATAOUT
DATA OUT VALID
tPD
tPU
I
CC
SB
V
CC SUPPLY
CURRENT
I
2948 drw 05
,
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
2948 drw 06
,
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
(2)
tWR
tAS
tWP
WE
(5)
CHZ
(5)
t
tWHZ
(5)
OW
t
HIGH IMPEDANCE
(3)
(3)
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
2948 drw 07
,
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
tWR
tCW
tAS
WE
tDW
tDH
DATAIN
DATAIN VALID
2948 drw 08
,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information — Commercial
X
71256
SA
XX
XXX
X
TT
Device
Type
Power Speed Package
Process/
Temperature
Range
Blank
G
Commercial (0°C to +70°C)
Restricted Hazardous Substance Device
P
TP
Y
600-mil Plastic DIP (P28-1) only 25ns available
300-mil Plastic DIP (P28-2)
300-mil SOJ (SO28-5)
PZ
TSOP Type I (SO28-8)
12
15
20
25
,
Speed in nanoseconds
First generation or current die step
Current generation die step optional
Blank
TT
2948 drw 09
Ordering Information — Industrial
71256
SA
XX
XXX
X
X
TT
Device
Type
Power Speed
Package
Process/
Temperature
Range
I
Industrial (-40°C to +85°C)
G
Restricted hazardous substance device
,
Y
PZ
300-mil SOJ (SO28-5)
TSOP Type I (SO28-8)
12
15
20
25
Speed in nanoseconds
Blank
TT
First generation or current die step
Current generation die step optional
2948 drw 10
6.42
7
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
1/7/00
Updatedtonewformat
Pp. 1, 3, 4, 7
Pg. 6
RevisedIndustrialTemperaturerangeofferings
RemovedNoteNo.1forWriteCyclediagrams,renumberedfootnotesandnotes
AddedDatasheetDocumentHistory
Pg. 8
08/09/00
02/01/01
09/30/04
02/20/07
10/13/08
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
Pg. 7
Pg. 7
Pg. 7
Added"Restrictedhazardoussubstancedevice"toorderinginformations.
AddedTTgenerationdiesteptodatasheetorderinginformation.
removed"IDT"fromorderablepartnumber
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
71256TTSA15YGI 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 71256TTSA20TPG | IDT | Application Specific SRAM, 32KX8, 20ns, CMOS, PDIP28 | 获取价格 |
|
| 71256TTSA25PZG | IDT | Application Specific SRAM, 32KX8, 25ns, CMOS, PDSO28 | 获取价格 |
|
| 71256TTSA25PZGI | IDT | Application Specific SRAM, 32KX8, 25ns, CMOS, PDSO28 | 获取价格 |
|
| 71256TTSA25Y | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDSO28 | 获取价格 |
|
| 71256TTSA25YG | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOJ-28 | 获取价格 |
|
| 71256TTSA25YGI | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOJ-28 | 获取价格 |
|
| 71259-004HLF | AMPHENOL | Board Connector, LEAD FREE | 获取价格 |
|
| 71259-006HLF | AMPHENOL | Board Connector, LEAD FREE | 获取价格 |
|
| 71259-008H | AMPHENOL | Board Stacking Connector, 8 Contact(s), 2 Row(s), Male, Straight, Solder Terminal | 获取价格 |
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| 71259-008HLF | AMPHENOL | Board Connector, LEAD FREE | 获取价格 |
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